[SystemZ] Bugfix in SystemZTargetLowering::combineIntDIVREM()

Make sure to not unroll a vector division/remainder (with a constant splat
divisor) after type legalization, since the scalar type may then be illegal.

Review: Ulrich Weigand
https://reviews.llvm.org/D62036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360965 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 15f4237fe95be9b15a8a9365bbe4987716103936..8245a236afbd30d099eaeda6f4b92d852f7b58d5 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -5841,7 +5841,7 @@ SDValue SystemZTargetLowering::combineIntDIVREM(
   // since it is not Legal but Custom it can only happen before
   // legalization. Therefore we must scalarize this early before Combine
   // 1. For widened vectors, this is already the result of type legalization.
-  if (VT.isVector() && isTypeLegal(VT) &&
+  if (DCI.Level == BeforeLegalizeTypes && VT.isVector() && isTypeLegal(VT) &&
       DAG.isConstantIntBuildVectorOrConstantInt(N->getOperand(1)))
     return DAG.UnrollVectorOp(N);
   return SDValue();

diff --git a/test/CodeGen/SystemZ/vec-rem.ll b/test/CodeGen/SystemZ/vec-rem.ll
new file mode 100644 (file)
index 0000000..6f5da95
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-rem.ll
@@ -0,0 +1,13 @@
+; Verify that we do not create illegal scalar urems after type legalization.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13
+
+define <16 x i8> @main(i16 %arg) {
+bb:
+  %tmp6 = insertelement <16 x i16> undef, i16 %arg, i32 0
+  %tmp7 = shufflevector <16 x i16> %tmp6, <16 x i16> undef, <16 x i32> zeroinitializer
+  %tmp8 = insertelement <16 x i8> <i8 undef, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i8 undef, i32 0
+  %tmp11 = urem <16 x i16> %tmp7, <i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265>
+  %tmp12 = trunc <16 x i16> %tmp11 to <16 x i8>
+  ret <16 x i8> %tmp12
+}