gn build: (manually) merge r373527

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373534 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn b/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
index b05e0891d124e7935c5363d29a325cabb6943e33..0c27c11e2e0ba0a089253d671d81edf7ef06e485 100644 (file)
--- a/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
+++ b/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
@@ -30,6 +30,15 @@ tablegen("AArch64GenGlobalISel") {
   td_file = "AArch64.td"
 }
 
+tablegen("AArch64GenGICombiner") {
+  visibility = [ ":LLVMAArch64CodeGen" ]
+  args = [
+    "-gen-global-isel-combiner",
+    "-combiners=AArch64PreLegalizerCombinerHelper",
+  ]
+  td_file = "AArch64.td"
+}
+
 tablegen("AArch64GenMCPseudoLowering") {
   visibility = [ ":LLVMAArch64CodeGen" ]
   args = [ "-gen-pseudo-lowering" ]
@@ -48,6 +57,7 @@ static_library("LLVMAArch64CodeGen") {
     ":AArch64GenCallingConv",
     ":AArch64GenDAGISel",
     ":AArch64GenFastISel",
+    ":AArch64GenGICombiner",
     ":AArch64GenGlobalISel",
     ":AArch64GenMCPseudoLowering",
     ":AArch64GenRegisterBank",

diff --git a/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn b/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
index 01219543d2db726960267d1d9a04fb7dc3a36ac5..9f5043faeed8c6e69d8135586abe97c21f65cacc 100644 (file)
--- a/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
+++ b/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
@@ -30,6 +30,7 @@ executable("llvm-tblgen") {
     "ExegesisEmitter.cpp",
     "FastISelEmitter.cpp",
     "FixedLenDecoderEmitter.cpp",
+    "GICombinerEmitter.cpp",
     "GlobalISelEmitter.cpp",
     "InfoByHwMode.cpp",
     "InstrDocsEmitter.cpp",