Found by inspection when looking at the debug output of MCA.
This problem was latent, and none of the upstream models were affected by it.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357000
91177308-0d34-0410-b5e6-
96231b3b80d8
public:
DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI,
unsigned MaxDispatchWidth, RetireControlUnit &R,
- RegisterFile &F)
- : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
- CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) {}
+ RegisterFile &F);
bool isAvailable(const InstRef &IR) const override;
} else {
// Remove the leading 1 from the resource group mask.
NormalizedMask ^= PowerOf2Floor(NormalizedMask);
+ UsedResourceGroups |= (A.first ^ NormalizedMask);
}
for (unsigned J = I + 1; J < E; ++J) {
namespace llvm {
namespace mca {
+DispatchStage::DispatchStage(const MCSubtargetInfo &Subtarget,
+ const MCRegisterInfo &MRI,
+ unsigned MaxDispatchWidth, RetireControlUnit &R,
+ RegisterFile &F)
+ : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
+ CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) {
+ if (!DispatchWidth)
+ DispatchWidth = Subtarget.getSchedModel().IssueWidth;
+}
+
void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
ArrayRef<unsigned> UsedRegs,
unsigned UOps) const {
SummaryView::SummaryView(const MCSchedModel &Model, ArrayRef<MCInst> S,
unsigned Width, bool EmitBottleneckAnalysis)
- : SM(Model), Source(S), DispatchWidth(Width), LastInstructionIdx(0),
+ : SM(Model), Source(S), DispatchWidth(Width?Width: Model.IssueWidth),
+ LastInstructionIdx(0),
TotalCycles(0), NumMicroOps(0), BPI({0, 0, 0, 0, 0}),
ResourcePressureDistribution(Model.getNumProcResourceKinds(), 0),
ProcResourceUsage(Model.getNumProcResourceKinds(), 0),
const MCSchedModel &SM = STI->getSchedModel();
- unsigned Width = SM.IssueWidth;
- if (DispatchWidth)
- Width = DispatchWidth;
-
// Create an instruction builder.
mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
// Create a context to control ownership of the pipeline hardware.
mca::Context MCA(*MRI, *STI);
- mca::PipelineOptions PO(Width, RegisterFileSize, LoadQueueSize,
+ mca::PipelineOptions PO(DispatchWidth, RegisterFileSize, LoadQueueSize,
StoreQueueSize, AssumeNoAlias,
EnableBottleneckAnalysis);
if (PrintSummaryView)
Printer.addView(llvm::make_unique<mca::SummaryView>(
- SM, Insts, Width, EnableBottleneckAnalysis));
+ SM, Insts, DispatchWidth, EnableBottleneckAnalysis));
if (PrintInstructionInfoView)
Printer.addView(