Make 80MHz PSRAM work as well, add testcase for weirdness reported on esp32 forums...

diff --git a/components/esp32/clk.c b/components/esp32/clk.c
index f9be8dac5798eac870c9a8a2a0a9c40c144c8625..4472629e8eb248bfc10a6fa5241c028eac795f33 100644 (file)
--- a/components/esp32/clk.c
+++ b/components/esp32/clk.c
@@ -174,7 +174,10 @@ void esp_perip_clk_init(void)
                               DPORT_LEDC_CLK_EN |
                               DPORT_UHCI1_CLK_EN |
                               DPORT_TIMERGROUP1_CLK_EN |
+//80MHz SPIRAM uses SPI2 as well; it's initialized before this is called. Do not disable the clock for that if this is enabled.
+#if !CONFIG_SPIRAM_SPEED_80M
                               DPORT_SPI_CLK_EN_2 |
+#endif
                               DPORT_PWM0_CLK_EN |
                               DPORT_I2C_EXT1_CLK_EN |
                               DPORT_CAN_CLK_EN |
@@ -196,6 +199,7 @@ void esp_perip_clk_init(void)
                               DPORT_WIFI_CLK_SDIO_HOST_EN |
                               DPORT_WIFI_CLK_EMAC_EN;
     }
+
     /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
      * the current is not reduced when disable I2S clock.
      */

diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c
index d6653d116724e12a7eaa41813d7510650a822519..6be905d141f5c762b9dc67848272c5788b992f88 100644 (file)
--- a/components/esp32/spiram_psram.c
+++ b/components/esp32/spiram_psram.c
@@ -94,9 +94,6 @@ typedef enum {
 
 static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
 
-//For now, we only use F40M + S40M, and we don't have to go through gpio matrix
-#define ENABLE_GPIO_MATRIX_SPI   1
-
 /* dummy_len_plus values defined in ROM for SPI flash configuration */
 extern uint8_t g_rom_spiflash_dummy_len_plus[];
 
@@ -528,9 +525,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
     }
     CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_SETUP_M);
 
-#if ENABLE_GPIO_MATRIX_SPI
     psram_gpio_config(mode);
-#endif
     WRITE_PERI_REG(GPIO_ENABLE_W1TS_REG, BIT(PSRAM_CS_IO)| BIT(PSRAM_CLK_IO));
     PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CS_IO], 2);
     PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], 2);

diff --git a/components/esp32/test/test_spiram_cache_flush.c b/components/esp32/test/test_spiram_cache_flush.c
index 3d6f75f1fa56082c94fecdd6527c887dc3e3925e..a99f7226dbee771b100c3a1266541f11f0ffc30c 100644 (file)
--- a/components/esp32/test/test_spiram_cache_flush.c
+++ b/components/esp32/test/test_spiram_cache_flush.c
@@ -56,6 +56,7 @@ TEST_CASE("Spiram cache flush on mmap", "[spiram][ignore]")
     void *mem[2];
     res[0]=0; res[1]=0;
 #if CONFIG_SPIRAM_USE_CAPS_ALLOC
+    printf("Allocating SPI RAM chunk...\n");
     mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
     mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
 #else
@@ -101,6 +102,7 @@ TEST_CASE("Spiram cache flush on write/read", "[spiram][ignore]")
     void *mem[2];
     res[0]=0; res[1]=0;
 #if CONFIG_SPIRAM_USE_CAPS_ALLOC
+    printf("Allocating SPI RAM chunk...\n");
     mem[0]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
     mem[1]=heap_caps_malloc(TSTSZ, MALLOC_CAP_SPIRAM);
 #else
@@ -175,3 +177,7 @@ IRAM_ATTR TEST_CASE("Spiram memcmp weirdness at 80MHz", "[spiram][ignore]") {
 
 
 #endif  //CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MEMMAP
+
+
+
+