[PowerPC] Sign-extend negative constant stores

Second part of https://reviews.llvm.org/D40348.
Revision r318436 has extended all constants feeding a store to 64 bits
to allow for CSE on the SDAG. However, negative constants were zero extended
which made the constant being loaded appear to be a positive value larger than
16 bits. This resulted in long sequences to materialize such constants
rather than simply a "load immediate". This patch just sign-extends those
updated constants so that they remain 16-bit signed immediates if they started
out that way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320368 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 3fe9fe734993d00f03570f08328eb4fe7a708cb0..af2ea6950894acfb1e91f262e098531bef8eada2 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -12228,8 +12228,12 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
     EVT VT = N->getOperand(1).getValueType();
     if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() &&
         isa<ConstantSDNode>(N->getOperand(1)) && VT == MVT::i32) {
-      SDValue Const64 = DAG.getConstant(N->getConstantOperandVal(1), dl,
-                                        MVT::i64);
+      // Need to sign-extended to 64-bits to handle negative values.
+      EVT MemVT = cast<StoreSDNode>(N)->getMemoryVT();
+      uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1),
+                                    MemVT.getSizeInBits());
+      SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64);
+
       // DAG.getTruncStore() can't be used here because it doesn't accept
       // the general (base + offset) addressing mode.
       // So we use UpdateNodeOperands and setTruncatingStore instead.

diff --git a/test/CodeGen/PowerPC/testComparesigeui.ll b/test/CodeGen/PowerPC/testComparesigeui.ll
index a77cea72cfa9cba60f78d038c5ab8c527439adff..ac55500432f1b421bba47935a27d0ef94b825c22 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigeui.ll
+++ b/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -105,10 +105,8 @@ entry:
   store i32 %conv1, i32* @glob
   ret void
 ; CHECK-LABEL: @test_igeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], 0
-; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535
-; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535
-; CHECK: stw [[REG3]]
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
 ; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesllgeui.ll b/test/CodeGen/PowerPC/testComparesllgeui.ll
index 856d3a0f3cc430bbc348332c04c077c4e3753d18..9e971b140de4fa852f8559645e08a92391ec5e05 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgeui.ll
+++ b/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -105,10 +105,8 @@ entry:
   store i32 %sub, i32* @glob
   ret void
 ; CHECK-LABEL: @test_llgeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], 0
-; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535
-; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535
-; CHECK: stw [[REG3]]
+; CHECK: li [[REG1:r[0-9]+]], -1
+; CHECK: stw [[REG1]]
 ; CHECK: blr
 }