const AArch64Subtarget &ST,
const MachineInstr *First,
const MachineInstr *Second) {
+ assert((First || Second) && "At least one instr must be specified");
unsigned FirstOpcode =
- First ? First->getOpcode()
- : static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
+ First ? First->getOpcode()
+ : static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
unsigned SecondOpcode =
- Second ? Second->getOpcode()
- : static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
+ Second ? Second->getOpcode()
+ : static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
if (ST.hasArithmeticBccFusion())
// Fuse CMN, CMP, TST followed by Bcc.
FuseInc
} FuseKind;
+ assert((First || Second) && "At least one instr must be specified");
unsigned FirstOpcode = First
- ? First->getOpcode()
- : static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
- unsigned SecondOpcode =
- Second ? Second->getOpcode()
- : static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
+ ? First->getOpcode()
+ : static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
+ unsigned SecondOpcode = Second
+ ? Second->getOpcode()
+ : static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
switch (SecondOpcode) {
default:
// For now, assume targets can only fuse with the branch.
SUnit &ExitSU = DAG->ExitSU;
MachineInstr *Branch = ExitSU.getInstr();
- if (!shouldScheduleAdjacent(ST, nullptr, Branch))
+ if (!Branch || !shouldScheduleAdjacent(ST, nullptr, Branch))
return;
for (SDep &PredDep : ExitSU.Preds) {