]> granicus.if.org Git - llvm/commitdiff
Fix comment typos.
authorGeoff Berry <gberry@codeaurora.org>
Mon, 8 May 2017 15:33:08 +0000 (15:33 +0000)
committerGeoff Berry <gberry@codeaurora.org>
Mon, 8 May 2017 15:33:08 +0000 (15:33 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302432 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/TargetSchedule.td
utils/TableGen/SubtargetEmitter.cpp

index d342e4fe2613556d5aff434c440f4400bc66a63f..7b00c9420e3532c13d98309fc33e2fe55096667a 100644 (file)
@@ -334,7 +334,7 @@ class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
 }
 
 // Directly associate a new SchedRead type with a delay and optional
-// pipeline bypess. For use with InstRW or ItinRW.
+// pipeline bypass. For use with InstRW or ItinRW.
 class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead,
   ProcReadAdvance<cycles, writes>;
 
index 30516ef5d10de648af03a2a0c49f3491895a0b2a..1903f405d85986bd513792057dc58772193ead57 100644 (file)
@@ -415,7 +415,7 @@ EmitStageAndOperandCycleData(raw_ostream &OS,
   BypassTable += " 0, // No itinerary\n";
 
   // For each Itinerary across all processors, add a unique entry to the stages,
-  // operand cycles, and pipepine bypess tables. Then add the new Itinerary
+  // operand cycles, and pipeline bypass tables. Then add the new Itinerary
   // object with computed offsets to the ProcItinLists result.
   unsigned StageCount = 1, OperandCycleCount = 1;
   std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;