[AMDGPU] Use InliningThresholdMultiplier for inline hint

AMDGPU uses multiplier 9 for the inline cost. It is taken into account
everywhere except for inline hint threshold. As a result we are penalizing
functions with the inline hint making them less probable to be inlined
than those without the hint. Defaults are 225 for a normal function and
325 for a function with an inline hint. Currently we have effective
threshold 225 * 9 = 2025 for normal functions and just 325 for those with
the hint. That is fixed by this patch.

Differential Revision: https://reviews.llvm.org/D62707

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362239 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AMDGPUInline.cpp b/lib/Target/AMDGPU/AMDGPUInline.cpp
index 22c7c0d51f4574e3024a442b917aff29665837b0..72388a195de6bf96b8b9d744b39ce6123a72ed60 100644 (file)
--- a/lib/Target/AMDGPU/AMDGPUInline.cpp
+++ b/lib/Target/AMDGPU/AMDGPUInline.cpp
@@ -111,7 +111,8 @@ unsigned AMDGPUInliner::getInlineThreshold(CallSite CS) const {
     Callee->hasFnAttribute(Attribute::InlineHint);
   if (InlineHint && Params.HintThreshold && Params.HintThreshold > Thres
       && !Caller->hasFnAttribute(Attribute::MinSize))
-    Thres = Params.HintThreshold.getValue();
+    Thres = Params.HintThreshold.getValue() *
+            TTIWP->getTTI(*Callee).getInliningThresholdMultiplier();
 
   const DataLayout &DL = Caller->getParent()->getDataLayout();
   if (!Callee)

diff --git a/test/Transforms/Inline/AMDGPU/inline-hint.ll b/test/Transforms/Inline/AMDGPU/inline-hint.ll
new file mode 100644 (file)
index 0000000..f1cc19b
--- /dev/null
+++ b/test/Transforms/Inline/AMDGPU/inline-hint.ll
@@ -0,0 +1,77 @@
+; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-inline --inline-threshold=1 --inlinehint-threshold=2 < %s | FileCheck %s
+
+define hidden <16 x i32> @div_hint(<16 x i32> %x, <16 x i32> %y) #0 {
+entry:
+  %div.1 = udiv <16 x i32> %x, %y
+  %div.2 = udiv <16 x i32> %div.1, %y
+  %div.3 = udiv <16 x i32> %div.2, %y
+  %div.4 = udiv <16 x i32> %div.3, %y
+  %div.5 = udiv <16 x i32> %div.4, %y
+  %div.6 = udiv <16 x i32> %div.5, %y
+  %div.7 = udiv <16 x i32> %div.6, %y
+  %div.8 = udiv <16 x i32> %div.7, %y
+  %div.9 = udiv <16 x i32> %div.8, %y
+  %div.10 = udiv <16 x i32> %div.9, %y
+  %div.11 = udiv <16 x i32> %div.10, %y
+  %div.12 = udiv <16 x i32> %div.11, %y
+  %div.13 = udiv <16 x i32> %div.12, %y
+  %div.14 = udiv <16 x i32> %div.13, %y
+  %div.15 = udiv <16 x i32> %div.14, %y
+  %div.16 = udiv <16 x i32> %div.15, %y
+  %div.17 = udiv <16 x i32> %div.16, %y
+  %div.18 = udiv <16 x i32> %div.17, %y
+  %div.19 = udiv <16 x i32> %div.18, %y
+  ret <16 x i32> %div.19
+}
+
+; CHECK-LABEL: define amdgpu_kernel void @caller_hint
+; CHECK-NOT: call
+; CHECK: udiv
+; CHECK: ret void
+define amdgpu_kernel void @caller_hint(<16 x i32> addrspace(1)* nocapture %x, <16 x i32> addrspace(1)* nocapture readonly %y) {
+entry:
+  %tmp = load <16 x i32>, <16 x i32> addrspace(1)* %x, align 4
+  %tmp1 = load <16 x i32>, <16 x i32> addrspace(1)* %y, align 4
+  %div.i = tail call <16 x i32> @div_hint(<16 x i32> %tmp, <16 x i32> %tmp1) #0
+  store <16 x i32> %div.i, <16 x i32> addrspace(1)* %x, align 4
+  ret void
+}
+
+define hidden <16 x i32> @div_nohint(<16 x i32> %x, <16 x i32> %y) {
+entry:
+  %div.1 = udiv <16 x i32> %x, %y
+  %div.2 = udiv <16 x i32> %div.1, %y
+  %div.3 = udiv <16 x i32> %div.2, %y
+  %div.4 = udiv <16 x i32> %div.3, %y
+  %div.5 = udiv <16 x i32> %div.4, %y
+  %div.6 = udiv <16 x i32> %div.5, %y
+  %div.7 = udiv <16 x i32> %div.6, %y
+  %div.8 = udiv <16 x i32> %div.7, %y
+  %div.9 = udiv <16 x i32> %div.8, %y
+  %div.10 = udiv <16 x i32> %div.9, %y
+  %div.11 = udiv <16 x i32> %div.10, %y
+  %div.12 = udiv <16 x i32> %div.11, %y
+  %div.13 = udiv <16 x i32> %div.12, %y
+  %div.14 = udiv <16 x i32> %div.13, %y
+  %div.15 = udiv <16 x i32> %div.14, %y
+  %div.16 = udiv <16 x i32> %div.15, %y
+  %div.17 = udiv <16 x i32> %div.16, %y
+  %div.18 = udiv <16 x i32> %div.17, %y
+  %div.19 = udiv <16 x i32> %div.18, %y
+  ret <16 x i32> %div.19
+}
+
+; CHECK-LABEL: define amdgpu_kernel void @caller_nohint
+; CHECK-NOT: udiv
+; CHECK: tail call <16 x i32> @div_nohint
+; CHECK: ret void
+define amdgpu_kernel void @caller_nohint(<16 x i32> addrspace(1)* nocapture %x, <16 x i32> addrspace(1)* nocapture readonly %y) {
+entry:
+  %tmp = load <16 x i32>, <16 x i32> addrspace(1)* %x
+  %tmp1 = load <16 x i32>, <16 x i32> addrspace(1)* %y
+  %div.i = tail call <16 x i32> @div_nohint(<16 x i32> %tmp, <16 x i32> %tmp1)
+  store <16 x i32> %div.i, <16 x i32> addrspace(1)* %x
+  ret void
+}
+
+attributes #0 = { inlinehint }