[PowerPC] Automatically generate vec_buildvector_loadstore.ll . NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369703 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
index aef43b41a2676b35e5836398ba36fb0a7a5bcb72..0a00dc4477b69162adbe1e4423914bd7f3c96767 100644 (file)
--- a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
+++ b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -disable-ppc-ilp-pref  | FileCheck %s
 ; Formerly this did byte loads and word stores.
 @a = external global <16 x i8>
@@ -5,8 +6,20 @@
 @c = external global <16 x i8>
 
 define void @foo() nounwind ssp {
-; CHECK: foo:
-; CHECK-NOT: stw
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 3, a@l
+; CHECK-NEXT:    lis 4, a@ha
+; CHECK-NEXT:    lvx 2, 4, 3
+; CHECK-NEXT:    li 3, .LCPI0_0@l
+; CHECK-NEXT:    lis 4, .LCPI0_0@ha
+; CHECK-NEXT:    lvx 3, 4, 3
+; CHECK-NEXT:    vxor 4, 4, 4
+; CHECK-NEXT:    li 3, c@l
+; CHECK-NEXT:    lis 4, c@ha
+; CHECK-NEXT:    vperm 2, 4, 2, 3
+; CHECK-NEXT:    stvx 2, 4, 3
+; CHECK-NEXT:    blr
 entry:
     %tmp0 = load <16 x i8>, <16 x i8>* @a, align 16
   %tmp180.i = extractelement <16 x i8> %tmp0, i32 0 ; <i8> [#uses=1]
@@ -33,5 +46,4 @@ entry:
 
 return:                ; preds = %bb2
        ret void
-; CHECK: blr
 }