[mips][msa] Add intrinsics that map to pseudo-instructions.

Unlike the previously added intrinsics, these do not map to a single instruction
on MIPS32. They are provided for regularity (to round out the .[bhw] variants
of the same operation) and compatibility with GCC.

Includes:
  copy_[us].d, fill.d, insert.d, insve.d

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@193237 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/clang/Basic/BuiltinsMips.def b/include/clang/Basic/BuiltinsMips.def
index 7711c1d6fdedcd770047c3eac56bd1eb0444cb9f..2f18ed3f8435d5b27d78c7890aa8f50951d7927c 100644 (file)
--- a/include/clang/Basic/BuiltinsMips.def
+++ b/include/clang/Basic/BuiltinsMips.def
@@ -378,10 +378,12 @@ BUILTIN(__builtin_msa_clti_u_d, "V2SLLiV2ULLiIUi", "nc")
 BUILTIN(__builtin_msa_copy_s_b, "iV16ScIUi", "nc")
 BUILTIN(__builtin_msa_copy_s_h, "iV8SsIUi", "nc")
 BUILTIN(__builtin_msa_copy_s_w, "iV4SiIUi", "nc")
+BUILTIN(__builtin_msa_copy_s_d, "LLiV2SLLiIUi", "nc")
 
 BUILTIN(__builtin_msa_copy_u_b, "iV16UcIUi", "nc")
 BUILTIN(__builtin_msa_copy_u_h, "iV8UsIUi", "nc")
 BUILTIN(__builtin_msa_copy_u_w, "iV4UiIUi", "nc")
+BUILTIN(__builtin_msa_copy_u_d, "LLiV2ULLiIUi", "nc")
 
 BUILTIN(__builtin_msa_ctcmsa, "vIii", "n")
 
@@ -490,6 +492,7 @@ BUILTIN(__builtin_msa_ffqr_d, "V2dV4Si", "nc")
 BUILTIN(__builtin_msa_fill_b, "V16Sci", "nc")
 BUILTIN(__builtin_msa_fill_h, "V8Ssi", "nc")
 BUILTIN(__builtin_msa_fill_w, "V4Sii", "nc")
+BUILTIN(__builtin_msa_fill_d, "V2SLLiLLi", "nc")
 
 BUILTIN(__builtin_msa_flog2_w, "V4fV4f", "nc")
 BUILTIN(__builtin_msa_flog2_d, "V2dV2d", "nc")
@@ -617,10 +620,12 @@ BUILTIN(__builtin_msa_ilvr_d, "V2LLiV2LLiV2LLi", "nc")
 BUILTIN(__builtin_msa_insert_b, "V16ScV16ScIUii", "nc")
 BUILTIN(__builtin_msa_insert_h, "V8SsV8SsIUii", "nc")
 BUILTIN(__builtin_msa_insert_w, "V4SiV4SiIUii", "nc")
+BUILTIN(__builtin_msa_insert_d, "V2SLLiV2SLLiIUiLLi", "nc")
 
 BUILTIN(__builtin_msa_insve_b, "V16ScV16ScIUiV16Sc", "nc")
 BUILTIN(__builtin_msa_insve_h, "V8SsV8SsIUiV8Ss", "nc")
 BUILTIN(__builtin_msa_insve_w, "V4SiV4SiIUiV4Si", "nc")
+BUILTIN(__builtin_msa_insve_d, "V2SLLiV2SLLiIUiV2SLLi", "nc")
 
 BUILTIN(__builtin_msa_ld_b, "V16Scv*Ii", "nc")
 BUILTIN(__builtin_msa_ld_h, "V8Ssv*Ii", "nc")

diff --git a/test/CodeGen/builtins-mips-msa.c b/test/CodeGen/builtins-mips-msa.c
index 51508ee8ac5b8344d1ca1d3f492a033dae5927be..31ee79a5a089238e968f30fe3b8ba6381457eb53 100644 (file)
--- a/test/CodeGen/builtins-mips-msa.c
+++ b/test/CodeGen/builtins-mips-msa.c
@@ -52,6 +52,7 @@ void test(void) {
   v2f64 v2f64_r;
 
   int int_r;
+  long long ll_r;
   int int_a = 0;
 
   v16i8_r = __builtin_msa_add_a_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8>  @llvm.mips.add.a.b(
@@ -272,10 +273,12 @@ void test(void) {
   int_r = __builtin_msa_copy_s_b(v16i8_a, 1); // CHECK: call i32 @llvm.mips.copy.s.b(
   int_r = __builtin_msa_copy_s_h(v8i16_a, 1); // CHECK: call i32 @llvm.mips.copy.s.h(
   int_r = __builtin_msa_copy_s_w(v4i32_a, 1); // CHECK: call i32 @llvm.mips.copy.s.w(
+  ll_r  = __builtin_msa_copy_s_d(v2i64_a, 1); // CHECK: call i64 @llvm.mips.copy.s.d(
 
   int_r = __builtin_msa_copy_u_b(v16u8_a, 1); // CHECK: call i32 @llvm.mips.copy.u.b(
   int_r = __builtin_msa_copy_u_h(v8u16_a, 1); // CHECK: call i32 @llvm.mips.copy.u.h(
   int_r = __builtin_msa_copy_u_w(v4u32_a, 1); // CHECK: call i32 @llvm.mips.copy.u.w(
+  ll_r  = __builtin_msa_copy_u_d(v2i64_a, 1); // CHECK: call i64 @llvm.mips.copy.u.d(
 
   __builtin_msa_ctcmsa(1, int_a); // CHECK: call void @llvm.mips.ctcmsa(
 
@@ -382,6 +385,7 @@ void test(void) {
   v16i8_r = __builtin_msa_fill_b(3); // CHECK: call <16 x i8>  @llvm.mips.fill.b(
   v8i16_r = __builtin_msa_fill_h(3); // CHECK: call <8  x i16> @llvm.mips.fill.h(
   v4i32_r = __builtin_msa_fill_w(3); // CHECK: call <4  x i32> @llvm.mips.fill.w(
+  v2i64_r = __builtin_msa_fill_d(3); // CHECK: call <2  x i64> @llvm.mips.fill.d(
 
   v4f32_r = __builtin_msa_flog2_w(v8f16_a); // CHECK: call <4 x float>  @llvm.mips.flog2.w(
   v2f64_r = __builtin_msa_flog2_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.flog2.d(
@@ -509,10 +513,12 @@ void test(void) {
   v16i8_r = __builtin_msa_insert_b(v16i8_r, 1, 25); // CHECK: call <16 x i8>  @llvm.mips.insert.b(
   v8i16_r = __builtin_msa_insert_h(v8i16_r, 1, 25); // CHECK: call <8  x i16> @llvm.mips.insert.h(
   v4i32_r = __builtin_msa_insert_w(v4i32_r, 1, 25); // CHECK: call <4  x i32> @llvm.mips.insert.w(
+  v2i64_r = __builtin_msa_insert_d(v2i64_r, 1, 25); // CHECK: call <2  x i64> @llvm.mips.insert.d(
 
   v16i8_r = __builtin_msa_insve_b(v16i8_r, 1, v16i8_a); // CHECK: call <16 x i8>  @llvm.mips.insve.b(
   v8i16_r = __builtin_msa_insve_h(v8i16_r, 1, v8i16_a); // CHECK: call <8  x i16> @llvm.mips.insve.h(
   v4i32_r = __builtin_msa_insve_w(v4i32_r, 1, v4i32_a); // CHECK: call <4  x i32> @llvm.mips.insve.w(
+  v2i64_r = __builtin_msa_insve_d(v2i64_r, 1, v2i64_a); // CHECK: call <2  x i64> @llvm.mips.insve.d(
 
   v16i8_r = __builtin_msa_ld_b(&v16i8_a, 1); // CHECK: call <16 x i8>  @llvm.mips.ld.b(
   v8i16_r = __builtin_msa_ld_h(&v8i16_a, 2); // CHECK: call <8  x i16> @llvm.mips.ld.h(