Simplify DefaultCPU in ARMTargetInfo

Simplifying the convoluted CPU handling in ARMTargetInfo.

The default base CPU on ARM is ARM7TDMI, arch ARMv4T, and
ARMTargetInfo had a different one. This wasn't visible from
Clang because the driver selects the defaults and sets the
Arch/CPU features directly, but the constructor depended
on the CPU, which was never used.

This patch corrects the mistake and greatly simplifies
how CPU is dealt with (essentially by removing the duplicated
DefaultCPU field).

Tests updated.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@249699 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 4397c7a677fd7b8cfe8f154d203d61bdd47b768c..1f576d96220381b148e060e92640041a2e505cba 100644 (file)
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -4086,7 +4086,6 @@ class ARMTargetInfo : public TargetInfo {
 
   std::string ABI, CPU;
 
-  StringRef DefaultCPU;
   StringRef CPUProfile;
   StringRef CPUAttr;
 
@@ -4097,7 +4096,7 @@ class ARMTargetInfo : public TargetInfo {
   } FPMath;
 
   unsigned ArchISA;
-  unsigned ArchKind;
+  unsigned ArchKind = llvm::ARM::AK_ARMV4T;
   unsigned ArchProfile;
   unsigned ArchVersion;
 
@@ -4235,13 +4234,11 @@ class ARMTargetInfo : public TargetInfo {
   void setArchInfo() {
     StringRef ArchName = getTriple().getArchName();
 
-    ArchISA    = llvm::ARM::parseArchISA(ArchName);
-    DefaultCPU = getDefaultCPU(ArchName);
-
-    unsigned ArchKind = llvm::ARM::parseArch(ArchName);
-    if (ArchKind == llvm::ARM::AK_INVALID)
-      // set arch of the CPU, either provided explicitly or hardcoded default
-      ArchKind = llvm::ARM::parseCPUArch(CPU);
+    ArchISA     = llvm::ARM::parseArchISA(ArchName);
+    CPU         = llvm::ARM::getDefaultCPU(ArchName);
+    unsigned AK = llvm::ARM::parseArch(ArchName);
+    if (AK != llvm::ARM::AK_INVALID)
+      ArchKind = AK;
     setArchInfo(ArchKind);
   }
 
@@ -4262,8 +4259,7 @@ class ARMTargetInfo : public TargetInfo {
   void setAtomic() {
     // when triple does not specify a sub arch, 
     // then we are not using inline atomics
-    bool ShouldUseInlineAtomic = DefaultCPU.empty() ? 
-                                 false :
+    bool ShouldUseInlineAtomic =
                    (ArchISA == llvm::ARM::IK_ARM   && ArchVersion >= 6) ||
                    (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
     // Cortex M does not support 8 byte atomics, while general Thumb2 does. 
@@ -4291,10 +4287,6 @@ class ARMTargetInfo : public TargetInfo {
     return CPUAttr.equals("6T2") || ArchVersion >= 7;
   }
 
-  StringRef getDefaultCPU(StringRef ArchName) const {
-    return llvm::ARM::getDefaultCPU(ArchName);
-  }
-
   StringRef getCPUAttr() const {
     // For most sub-arches, the build attribute CPU name is enough.
     // For Cortex variants, it's slightly different.
@@ -4340,7 +4332,7 @@ class ARMTargetInfo : public TargetInfo {
 
 public:
   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
-      : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
+      : TargetInfo(Triple), FPMath(FP_Default),
         IsAAPCS(true), LDREX(0), HW_FP(0) {
     BigEndian = IsBigEndian;
 
@@ -4353,7 +4345,7 @@ public:
       break;
     }
 
-    // cache arch related info
+    // Cache arch related info.
     setArchInfo();
 
     // {} in inline assembly are neon specifiers, not assembly variant
@@ -4389,8 +4381,8 @@ public:
         setABI("aapcs");
         break;
       case llvm::Triple::GNU:
-       setABI("apcs-gnu");
-       break;
+        setABI("apcs-gnu");
+      break;
       default:
         if (Triple.getOS() == llvm::Triple::NetBSD)
           setABI("apcs-gnu");

diff --git a/test/Preprocessor/init.c b/test/Preprocessor/init.c
index a2f5bf72544a164d1188b047d857ed2b40e77cab..7ddb9464d4fd14d82a46cdf5abbc2657a1c531ce 100644 (file)
--- a/test/Preprocessor/init.c
+++ b/test/Preprocessor/init.c
@@ -1198,7 +1198,7 @@
 // ARM:#define __APCS_32__ 1
 // ARM-NOT:#define __ARMEB__ 1
 // ARM:#define __ARMEL__ 1
-// ARM:#define __ARM_ARCH_6J__ 1
+// ARM:#define __ARM_ARCH_4T__ 1
 // ARM-NOT:#define __ARM_BIG_ENDIAN 1
 // ARM:#define __BIGGEST_ALIGNMENT__ 8
 // ARM:#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
@@ -1338,7 +1338,6 @@
 // ARM:#define __SIZE_MAX__ 4294967295U
 // ARM:#define __SIZE_TYPE__ unsigned int
 // ARM:#define __SIZE_WIDTH__ 32
-// ARM:#define __THUMB_INTERWORK__ 1
 // ARM:#define __UINT16_C_SUFFIX__ {{$}}
 // ARM:#define __UINT16_MAX__ 65535
 // ARM:#define __UINT16_TYPE__ unsigned short
@@ -1389,7 +1388,7 @@
 // ARM-BE:#define __APCS_32__ 1
 // ARM-BE:#define __ARMEB__ 1
 // ARM-BE-NOT:#define __ARMEL__ 1
-// ARM-BE:#define __ARM_ARCH_6J__ 1
+// ARM-BE:#define __ARM_ARCH_4T__ 1
 // ARM-BE:#define __ARM_BIG_ENDIAN 1
 // ARM-BE:#define __BIGGEST_ALIGNMENT__ 8
 // ARM-BE:#define __BIG_ENDIAN__ 1
@@ -1529,7 +1528,6 @@
 // ARM-BE:#define __SIZE_MAX__ 4294967295U
 // ARM-BE:#define __SIZE_TYPE__ unsigned int
 // ARM-BE:#define __SIZE_WIDTH__ 32
-// ARM-BE:#define __THUMB_INTERWORK__ 1
 // ARM-BE:#define __UINT16_C_SUFFIX__ {{$}}
 // ARM-BE:#define __UINT16_MAX__ 65535
 // ARM-BE:#define __UINT16_TYPE__ unsigned short
@@ -1580,8 +1578,8 @@
 // ARMEABISOFTFP:#define __APCS_32__ 1
 // ARMEABISOFTFP-NOT:#define __ARMEB__ 1
 // ARMEABISOFTFP:#define __ARMEL__ 1
-// ARMEABISOFTFP:#define __ARM_ARCH 6
-// ARMEABISOFTFP:#define __ARM_ARCH_6J__ 1
+// ARMEABISOFTFP:#define __ARM_ARCH 4
+// ARMEABISOFTFP:#define __ARM_ARCH_4T__ 1
 // ARMEABISOFTFP-NOT:#define __ARM_BIG_ENDIAN 1
 // ARMEABISOFTFP:#define __ARM_EABI__ 1
 // ARMEABISOFTFP:#define __ARM_PCS 1
@@ -1725,7 +1723,6 @@
 // ARMEABISOFTFP:#define __SIZE_TYPE__ unsigned int
 // ARMEABISOFTFP:#define __SIZE_WIDTH__ 32
 // ARMEABISOFTFP:#define __SOFTFP__ 1
-// ARMEABISOFTFP:#define __THUMB_INTERWORK__ 1
 // ARMEABISOFTFP:#define __UINT16_C_SUFFIX__ {{$}}
 // ARMEABISOFTFP:#define __UINT16_MAX__ 65535
 // ARMEABISOFTFP:#define __UINT16_TYPE__ unsigned short
@@ -1776,8 +1773,8 @@
 // ARMEABIHARDFP:#define __APCS_32__ 1
 // ARMEABIHARDFP-NOT:#define __ARMEB__ 1
 // ARMEABIHARDFP:#define __ARMEL__ 1
-// ARMEABIHARDFP:#define __ARM_ARCH 6
-// ARMEABIHARDFP:#define __ARM_ARCH_6J__ 1
+// ARMEABIHARDFP:#define __ARM_ARCH 4
+// ARMEABIHARDFP:#define __ARM_ARCH_4T__ 1
 // ARMEABIHARDFP-NOT:#define __ARM_BIG_ENDIAN 1
 // ARMEABIHARDFP:#define __ARM_EABI__ 1
 // ARMEABIHARDFP:#define __ARM_PCS 1
@@ -1921,7 +1918,6 @@
 // ARMEABIHARDFP:#define __SIZE_TYPE__ unsigned int
 // ARMEABIHARDFP:#define __SIZE_WIDTH__ 32
 // ARMEABIHARDFP-NOT:#define __SOFTFP__ 1
-// ARMEABIHARDFP:#define __THUMB_INTERWORK__ 1
 // ARMEABIHARDFP:#define __UINT16_C_SUFFIX__ {{$}}
 // ARMEABIHARDFP:#define __UINT16_MAX__ 65535
 // ARMEABIHARDFP:#define __UINT16_TYPE__ unsigned short
@@ -1972,7 +1968,7 @@
 // ARM-NETBSD:#define __APCS_32__ 1
 // ARM-NETBSD-NOT:#define __ARMEB__ 1
 // ARM-NETBSD:#define __ARMEL__ 1
-// ARM-NETBSD:#define __ARM_ARCH_6J__ 1
+// ARM-NETBSD:#define __ARM_ARCH_4T__ 1
 // ARM-NETBSD:#define __ARM_DWARF_EH__ 1
 // ARM-NETBSD:#define __ARM_EABI__ 1
 // ARM-NETBSD-NOT:#define __ARM_BIG_ENDIAN 1
@@ -2114,7 +2110,6 @@
 // ARM-NETBSD:#define __SIZE_MAX__ 4294967295U
 // ARM-NETBSD:#define __SIZE_TYPE__ long unsigned int
 // ARM-NETBSD:#define __SIZE_WIDTH__ 32
-// ARM-NETBSD:#define __THUMB_INTERWORK__ 1
 // ARM-NETBSD:#define __UINT16_C_SUFFIX__ {{$}}
 // ARM-NETBSD:#define __UINT16_MAX__ 65535
 // ARM-NETBSD:#define __UINT16_TYPE__ unsigned short