[RDF] Move normalize(RegisterRef) to PhysicalRegisterInfo

Remove the duplicate from DFG and make some members of PRI private.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295351 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index f99a0645507c63d642bfb5477149e690b75a41d6..73fa0b3e5a3ddd0a91779cddaa8c6446ef2cc5fa 100644 (file)
--- a/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -230,7 +230,7 @@ void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA,
   for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) {
     DEBUG(dbgs() << "\t\t[DefNode]: " << Print<NodeAddr<DefNode *>>(DA, *DFG)
                  << "\n");
-    RegisterRef DR = DFG->normalizeRef(DA.Addr->getRegRef(*DFG));
+    RegisterRef DR = DFG->getPRI().normalize(DA.Addr->getRegRef(*DFG));
 
     auto UseSet = LV->getAllReachedUses(DR, DA);
 

diff --git a/lib/Target/Hexagon/RDFGraph.cpp b/lib/Target/Hexagon/RDFGraph.cpp
index 4b5c212a7f8c8e442262dc711441db70e61291dd..600a516319668537b13e420f3014f3bd285edda0 100644 (file)
--- a/lib/Target/Hexagon/RDFGraph.cpp
+++ b/lib/Target/Hexagon/RDFGraph.cpp
@@ -981,30 +981,14 @@ RegisterRef DataFlowGraph::makeRegRef(const MachineOperand &Op) const {
   return RegisterRef(PRI.getRegMaskId(Op.getRegMask()), LaneBitmask::getAll());
 }
 
-RegisterRef DataFlowGraph::normalizeRef(RegisterRef RR) const {
-  // FIXME copied from RegisterAggr
-  if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
-    return RR;
-  const TargetRegisterClass *RC = PRI.RegInfos[RR.Reg].RegClass;
-  LaneBitmask RCMask = RC != nullptr ? RC->LaneMask : LaneBitmask(0x00000001);
-  LaneBitmask Common = RR.Mask & RCMask;
-
-  RegisterId SuperReg = PRI.RegInfos[RR.Reg].MaxSuper;
-// Ex: IP/EIP/RIP
-//  assert(RC != nullptr || RR.Reg == SuperReg);
-  uint32_t Sub = PRI.getTRI().getSubRegIndex(SuperReg, RR.Reg);
-  LaneBitmask SuperMask = PRI.getTRI().composeSubRegIndexLaneMask(Sub, Common);
-  return RegisterRef(SuperReg, SuperMask);
-}
-
 RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
   if (AR.Reg == BR.Reg) {
     LaneBitmask M = AR.Mask & BR.Mask;
     return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef();
   }
 #ifndef NDEBUG
-  RegisterRef NAR = normalizeRef(AR);
-  RegisterRef NBR = normalizeRef(BR);
+  RegisterRef NAR = PRI.normalize(AR);
+  RegisterRef NBR = PRI.normalize(BR);
   assert(NAR.Reg != NBR.Reg);
 #endif
   // This isn't strictly correct, because the overlap may happen in the

diff --git a/lib/Target/Hexagon/RDFGraph.h b/lib/Target/Hexagon/RDFGraph.h
index a10dad587569d4c6d1ef31cde095ef37812a2f16..92c317c4d3c59f4a9797ed5f8f02e5cf8d67570d 100644 (file)
--- a/lib/Target/Hexagon/RDFGraph.h
+++ b/lib/Target/Hexagon/RDFGraph.h
@@ -745,7 +745,6 @@ namespace rdf {
 
     RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const;
     RegisterRef makeRegRef(const MachineOperand &Op) const;
-    RegisterRef normalizeRef(RegisterRef RR) const;
     RegisterRef restrictRef(RegisterRef AR, RegisterRef BR) const;
 
     NodeAddr<RefNode*> getNextRelated(NodeAddr<InstrNode*> IA,

diff --git a/lib/Target/Hexagon/RDFLiveness.cpp b/lib/Target/Hexagon/RDFLiveness.cpp
index 0dab15e9a690ba3157b076eaa5e78f6fd08334e9..fbc6301437f0e0e10bfe9fcad10d57f24f39c99e 100644 (file)
--- a/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/lib/Target/Hexagon/RDFLiveness.cpp
@@ -377,7 +377,7 @@ void Liveness::computePhiInfo() {
         NodeAddr<UseNode*> A = DFG.addr<UseNode*>(UN);
         uint16_t F = A.Addr->getFlags();
         if ((F & (NodeAttrs::Undef | NodeAttrs::PhiRef)) == 0) {
-          RegisterRef R = DFG.normalizeRef(getRestrictedRegRef(A));
+          RegisterRef R = PRI.normalize(getRestrictedRegRef(A));
           RealUses[R.Reg].insert({A.Id,R.Mask});
         }
         UN = A.Addr->getSibling();
@@ -522,7 +522,7 @@ void Liveness::computePhiInfo() {
 
     for (NodeAddr<UseNode*> UA : PUs) {
       std::map<NodeId,RegisterAggr> &PUM = PhiUp[UA.Id];
-      RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(UA));
+      RegisterRef UR = PRI.normalize(getRestrictedRegRef(UA));
       for (const std::pair<NodeId,RegisterAggr> &P : PUM) {
         bool Changed = false;
         const RegisterAggr &MidDefs = P.second;
@@ -656,7 +656,7 @@ void Liveness::computeLiveIns() {
         auto PrA = DFG.addr<BlockNode*>(PUA.Addr->getPredecessor());
         RefMap &LOX = PhiLOX[PrA.Addr->getCode()];
 
-        RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(PUA));
+        RegisterRef UR = PRI.normalize(getRestrictedRegRef(PUA));
         for (const std::pair<RegisterId,NodeRefSet> &T : RUs) {
           // Check if T.first aliases UR?
           LaneBitmask M;
@@ -980,7 +980,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
     for (NodeAddr<UseNode*> UA : IA.Addr->members_if(DFG.IsUse, DFG)) {
       if (UA.Addr->getFlags() & NodeAttrs::Undef)
         continue;
-      RegisterRef RR = DFG.normalizeRef(UA.Addr->getRegRef(DFG));
+      RegisterRef RR = PRI.normalize(UA.Addr->getRegRef(DFG));
       for (NodeAddr<DefNode*> D : getAllReachingDefs(UA))
         if (getBlockWithRef(D.Id) != B)
           LiveIn[RR.Reg].insert({D.Id,RR.Mask});

diff --git a/lib/Target/Hexagon/RDFRegisters.cpp b/lib/Target/Hexagon/RDFRegisters.cpp
index fc5ad0aedb101618f68274ca91fa3b9e393a7bd2..74d6ba53be7d3b29811a2b932fea9fc6d066e126 100644 (file)
--- a/lib/Target/Hexagon/RDFRegisters.cpp
+++ b/lib/Target/Hexagon/RDFRegisters.cpp
@@ -49,6 +49,21 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
           RegMasks.insert(Op.getRegMask());
 }
 
+RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const {
+  if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
+    return RR;
+  const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass;
+  LaneBitmask RCMask = RC != nullptr ? RC->LaneMask : LaneBitmask(0x00000001);
+  LaneBitmask Common = RR.Mask & RCMask;
+
+  RegisterId SuperReg = RegInfos[RR.Reg].MaxSuper;
+// Ex: IP/EIP/RIP
+//  assert(RC != nullptr || RR.Reg == SuperReg);
+  uint32_t Sub = TRI.getSubRegIndex(SuperReg, RR.Reg);
+  LaneBitmask SuperMask = TRI.composeSubRegIndexLaneMask(Sub, Common);
+  return RegisterRef(SuperReg, SuperMask);
+}
+
 std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
   // Do not include RR in the alias set.
   std::set<RegisterId> AS;
@@ -73,6 +88,14 @@ std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
 bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const {
   assert(TargetRegisterInfo::isPhysicalRegister(RA.Reg));
   assert(TargetRegisterInfo::isPhysicalRegister(RB.Reg));
+
+  RegisterRef NA = normalize(RA);
+  RegisterRef NB = normalize(RB);
+  if (NA.Reg == NB.Reg)
+    return (NA.Mask & NB.Mask).any();
+
+  // The code below relies on the fact that RA and RB do not share a common
+  // super-register.
   MCRegUnitMaskIterator UMA(RA.Reg, &TRI);
   MCRegUnitMaskIterator UMB(RB.Reg, &TRI);
   // Reg units are returned in the numerical order.
@@ -186,21 +209,6 @@ bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const {
 }
 
 
-RegisterRef RegisterAggr::normalize(RegisterRef RR) const {
-  if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
-    return RR;
-  const TargetRegisterClass *RC = PRI.RegInfos[RR.Reg].RegClass;
-  LaneBitmask RCMask = RC != nullptr ? RC->LaneMask : LaneBitmask(0x00000001);
-  LaneBitmask Common = RR.Mask & RCMask;
-
-  RegisterId SuperReg = PRI.RegInfos[RR.Reg].MaxSuper;
-// Ex: IP/EIP/RIP
-//  assert(RC != nullptr || RR.Reg == SuperReg);
-  uint32_t Sub = PRI.getTRI().getSubRegIndex(SuperReg, RR.Reg);
-  LaneBitmask SuperMask = PRI.getTRI().composeSubRegIndexLaneMask(Sub, Common);
-  return RegisterRef(SuperReg, SuperMask);
-}
-
 bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
   if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
     // XXX SLOW
@@ -213,7 +221,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
     }
   }
 
-  RegisterRef NR = normalize(RR);
+  RegisterRef NR = PRI.normalize(RR);
   auto F = Masks.find(NR.Reg);
   if (F != Masks.end()) {
     if ((F->second & NR.Mask).any())
@@ -241,7 +249,7 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
   }
 
   // Always have a cover for empty lane mask.
-  RegisterRef NR = normalize(RR);
+  RegisterRef NR = PRI.normalize(RR);
   if (NR.Mask.none())
     return true;
   auto F = Masks.find(NR.Reg);
@@ -262,7 +270,7 @@ RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
     return *this;
   }
 
-  RegisterRef NR = normalize(RR);
+  RegisterRef NR = PRI.normalize(RR);
   auto F = Masks.find(NR.Reg);
   if (F == Masks.end())
     Masks.insert({NR.Reg, NR.Mask});
@@ -301,7 +309,7 @@ RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
     return *this;
   }
 
-  RegisterRef NR = normalize(RR);
+  RegisterRef NR = PRI.normalize(RR);
   auto F = Masks.find(NR.Reg);
   if (F == Masks.end())
     return *this;

diff --git a/lib/Target/Hexagon/RDFRegisters.h b/lib/Target/Hexagon/RDFRegisters.h
index bad0e70091a567f4aa59d3c21ae1f51b8409a9f2..e344f479e4c71fb88f199cf5338c9b37f68ebf2e 100644 (file)
--- a/lib/Target/Hexagon/RDFRegisters.h
+++ b/lib/Target/Hexagon/RDFRegisters.h
@@ -91,6 +91,7 @@ namespace rdf {
     const uint32_t *getRegMaskBits(RegisterId R) const {
       return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
     }
+    RegisterRef normalize(RegisterRef RR) const;
 
     bool alias(RegisterRef RA, RegisterRef RB) const {
       if (!isRegMaskId(RA.Reg))
@@ -101,7 +102,7 @@ namespace rdf {
 
     const TargetRegisterInfo &getTRI() const { return TRI; }
 
-//  private:
+  private:
     struct RegInfo {
       unsigned MaxSuper = 0;
       const TargetRegisterClass *RegClass = nullptr;
@@ -146,7 +147,6 @@ namespace rdf {
     typedef MapType::const_iterator iterator;
     iterator begin() const { return Masks.begin(); }
     iterator end() const { return Masks.end(); }
-    RegisterRef normalize(RegisterRef RR) const;
 
   private:
     MapType Masks;