ARM: make sure we use all entries in a vector before forming a vpaddl.

Otherwise there's some mismatch, and we'll either form an illegal type or an
illegal node.

Thanks to Eli Friedman for pointing out the problem with my original solution.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301036 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index df840d723e3b962fb4db9c07eaa9da1dce0546a4..382f881f774133ebc0f2f23572fd9da54f8807f2 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -9480,11 +9480,11 @@ AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1,
       return SDValue();
   }
 
-  // Don't generate vpaddl+vmovn; we'll match it to vpadd later. Also don't try
-  // to handle an i8 -> i32 situation (or similar). vpaddl can only double the
-  // size.
-  if (2 * Vec.getValueType().getVectorElementType().getSizeInBits() !=
-      VT.getVectorElementType().getSizeInBits())
+  // Don't generate vpaddl+vmovn; we'll match it to vpadd later. Also make sure
+  // we're using the entire input vector, otherwise there's a size/legality
+  // mismatch somewhere.
+  if (nextIndex != Vec.getValueType().getVectorNumElements() ||
+      Vec.getValueType().getVectorElementType() == VT.getVectorElementType())
     return SDValue();
 
   // Create VPADDL node.

diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll
index 9720f801029d96a5c9dc4e3a695a2c0941e8545f..3409d37a31f4c6929ffc1f1dc67c959b17b7c02e 100644 (file)
--- a/test/CodeGen/ARM/vpadd.ll
+++ b/test/CodeGen/ARM/vpadd.ll
@@ -495,6 +495,15 @@ define <2 x i8> @fromExtendingExtractVectorElt_2i8(<8 x i8> %in) {
   ret <2 x i8> %x
 }
 
+define <2 x i16> @fromExtendingExtractVectorElt_2i16(<8 x i16> %in) {
+; CHECK-LABEL: fromExtendingExtractVectorElt_2i16:
+; CHECK:    vadd.i32
+ %tmp1 = shufflevector <8 x i16> %in, <8 x i16> undef, <2 x i32> <i32 0, i32 2>
+ %tmp2 = shufflevector <8 x i16> %in, <8 x i16> undef, <2 x i32> <i32 1, i32 3>
+ %x = add <2 x i16> %tmp2, %tmp1
+ ret <2 x i16> %x
+}
+
 
 declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
 declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone