]> granicus.if.org Git - llvm/commitdiff
Use range for loops. NFCI.
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 19 Jun 2017 13:24:12 +0000 (13:24 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 19 Jun 2017 13:24:12 +0000 (13:24 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305693 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/DAGISelMatcherGen.cpp

index aafc1157893e29ecc82787b9f7e09c9a3a8b8299..d239f96d2a6015362e9e4aa5669891992767dda8 100644 (file)
@@ -848,8 +848,7 @@ EmitResultInstructionAsOperand(const TreePatternNode *N,
     if (II.HasOneImplicitDefWithKnownVT(CGT) != MVT::Other)
       HandledReg = II.ImplicitDefs[0];
 
-    for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
-      Record *Reg = Pattern.getDstRegs()[i];
+    for (Record *Reg : Pattern.getDstRegs()) {
       if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue;
       ResultVTs.push_back(getRegisterValueType(Reg, CGT));
     }
@@ -972,8 +971,7 @@ void MatcherGen::EmitResultCode() {
         HandledReg = II.ImplicitDefs[0];
     }
 
-    for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i) {
-      Record *Reg = Pattern.getDstRegs()[i];
+    for (Record *Reg : Pattern.getDstRegs()) {
       if (!Reg->isSubClassOf("Register") || Reg == HandledReg) continue;
       ++NumSrcResults;
     }