ret i1 %cmp
}
+; (add (zext (add nuw X, C2)), C) --> (zext (add nuw X, C2 + C))
+
define i64 @test41(i32 %a) {
; CHECK-LABEL: @test41(
; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 %a, 15
ret i64 %sub
}
+; (add (zext (add nuw X, C2)), C) --> (zext (add nuw X, C2 + C))
+
+define <2 x i64> @test41vec(<2 x i32> %a) {
+; CHECK-LABEL: @test41vec(
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw <2 x i32> %a, <i32 15, i32 15>
+; CHECK-NEXT: [[SUB:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[SUB]]
+;
+ %add = add nuw <2 x i32> %a, <i32 16, i32 16>
+ %zext = zext <2 x i32> %add to <2 x i64>
+ %sub = add <2 x i64> %zext, <i64 -1, i64 -1>
+ ret <2 x i64> %sub
+}
+
+define <2 x i64> @test41vec_and_multiuse(<2 x i32> %a) {
+; CHECK-LABEL: @test41vec_and_multiuse(
+; CHECK-NEXT: [[ADD:%.*]] = add nuw <2 x i32> %a, <i32 16, i32 16>
+; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[ADD]] to <2 x i64>
+; CHECK-NEXT: [[TMP1:%.*]] = add nuw <2 x i32> %a, <i32 15, i32 15>
+; CHECK-NEXT: [[SUB:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
+; CHECK-NEXT: [[EXTRAUSE:%.*]] = add nuw nsw <2 x i64> [[ZEXT]], [[SUB]]
+; CHECK-NEXT: ret <2 x i64> [[EXTRAUSE]]
+;
+ %add = add nuw <2 x i32> %a, <i32 16, i32 16>
+ %zext = zext <2 x i32> %add to <2 x i64>
+ %sub = add <2 x i64> %zext, <i64 -1, i64 -1>
+ %extrause = add <2 x i64> %zext, %sub
+ ret <2 x i64> %extrause
+}
+
define i32 @test42(i1 %C) {
; CHECK-LABEL: @test42(
; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 1123, i32 133