[AArch64] IDSAR6 register assembler support

The IDSAR6 system register has been introduced to identify the
v8.3-a Javascript data type conversion and v8.2-a dot product
support.

Differential Revision: https://reviews.llvm.org/D37068

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312225 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64SystemOperands.td b/lib/Target/AArch64/AArch64SystemOperands.td
index c8db6d5824a359b659e731d188e13cb653ddf1a6..df939add70faae9176ab5185e62287f3c2136cee 100644 (file)
--- a/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/lib/Target/AArch64/AArch64SystemOperands.td
@@ -342,6 +342,9 @@ def : ROSysReg<"ID_ISAR2_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b010>;
 def : ROSysReg<"ID_ISAR3_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b011>;
 def : ROSysReg<"ID_ISAR4_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b100>;
 def : ROSysReg<"ID_ISAR5_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b101>;
+def : ROSysReg<"ID_ISAR6_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b111> {
+  let Requires = [{ {AArch64::HasV8_2aOps} }];
+}
 def : ROSysReg<"ID_AA64PFR0_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b000>;
 def : ROSysReg<"ID_AA64PFR1_EL1",     0b11, 0b000, 0b0000, 0b0100, 0b001>;
 def : ROSysReg<"ID_AA64DFR0_EL1",     0b11, 0b000, 0b0000, 0b0101, 0b000>;

diff --git a/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s b/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
new file mode 100644 (file)
index 0000000..c3dd8d8
--- /dev/null
+++ b/test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
+
+  mrs x0, ID_ISAR6_EL1
+// CHECK: mrs x0, ID_ISAR6_EL1        // encoding: [0xe0,0x02,0x38,0xd5]
+// CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, ID_ISAR6_EL1
+// CHECK-REQ-NEXT:         ^

diff --git a/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt b/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
new file mode 100644 (file)
index 0000000..106b007
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+
+# CHECK: mrs x0, ID_ISAR6_EL1
+0xe0,0x02,0x38,0xd5