[X86][AVX2] Removed FIXME comment and regenerated test.

The comment talked about replacing vpmovzxwd+vpslld+vpsrad with vpmovsxwd - which isn't valid as we're sign extending a <8 x i1> bool vector not an all/nobits <8 x i16>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292948 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/pr14204.ll b/test/CodeGen/X86/pr14204.ll
index 3b60ad885d556428d86ebc4ee2848f0dd7714c71..ab467d6ad96dacff2aaaa8c4e49d9549511c69b9 100644 (file)
--- a/test/CodeGen/X86/pr14204.ll
+++ b/test/CodeGen/X86/pr14204.ll
@@ -1,9 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s
 
-; FIXME: vpmovsxwd should be generated instead of vpmovzxwd followed by
-; SLL/SRA.
-
 define <8 x i32> @foo(<8 x i1> %bar) nounwind readnone {
 ; CHECK-LABEL: foo:
 ; CHECK:       # BB#0:
@@ -11,7 +8,6 @@ define <8 x i32> @foo(<8 x i1> %bar) nounwind readnone {
 ; CHECK-NEXT:    vpslld $31, %ymm0, %ymm0
 ; CHECK-NEXT:    vpsrad $31, %ymm0, %ymm0
 ; CHECK-NEXT:    retq
-;
   %s = sext <8 x i1> %bar to <8 x i32>
   ret <8 x i32> %s
 }