ARM: Add mappings for ACLE prefetch intrinsics

Implement __pld, __pldx, __pli and __plix builtin intrinsics as specified in
ARM ACLE 2.0.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@215599 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Headers/arm_acle.h b/lib/Headers/arm_acle.h
index a0fd6894ab9692f442abbb4bdd12d1d41bbdb0ff..286bc20e1236dc05f626f7f4524bcdbc16c81a49 100644 (file)
--- a/lib/Headers/arm_acle.h
+++ b/lib/Headers/arm_acle.h
@@ -66,6 +66,29 @@ static __inline__ void __attribute__((always_inline, nodebug)) __yield(void) {
 }
 #endif
 
+/* 8.6 Memory prefetch intrinsics */
+/* 8.6.1 Data prefetch */
+#define __pld(addr) __pldx(0, 0, 0, addr)
+
+#if __ARM_32BIT_STATE
+#define __pldx(access_kind, cache_level, retention_policy, addr) \
+  __builtin_arm_prefetch(addr, access_kind, 1)
+#else
+#define __pldx(access_kind, cache_level, retention_policy, addr) \
+  __builtin_arm_prefetch(addr, access_kind, cache_level, retention_policy, 1)
+#endif
+
+/* 8.6.2 Instruction prefetch */
+#define __pli(addr) __plix(0, 0, addr)
+
+#if __ARM_32BIT_STATE
+#define __plix(cache_level, retention_policy, addr) \
+  __builtin_arm_prefetch(addr, 0, 0)
+#else
+#define __plix(cache_level, retention_policy, addr) \
+  __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0)
+#endif
+
 /* 8.7 NOP */
 static __inline__ void __attribute__((always_inline, nodebug)) __nop(void) {
   __builtin_arm_nop();

diff --git a/test/CodeGen/arm_acle.c b/test/CodeGen/arm_acle.c
index 8550c58b3677aab999a268b791b850677cfa6d3f..8a23df836e4eb249850a22ff2750079ff249c7cd 100644 (file)
--- a/test/CodeGen/arm_acle.c
+++ b/test/CodeGen/arm_acle.c
@@ -62,6 +62,35 @@ void test_sevl(void) {
   __sevl();
 }
 
+/* 8.6 Memory prefetch intrinsics */
+/* 8.6.1 Data prefetch */
+// ARM-LABEL: test_pld
+// ARM: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 1)
+void test_pld() {
+  __pld(0);
+}
+
+// ARM-LABEL: test_pldx
+// AArch32: call void @llvm.prefetch(i8* null, i32 1, i32 3, i32 1)
+// AArch64: call void @llvm.prefetch(i8* null, i32 1, i32 1, i32 1)
+void test_pldx() {
+  __pldx(1, 2, 0, 0);
+}
+
+/* 8.6.2 Instruction prefetch */
+// ARM-LABEL: test_pli
+// ARM: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 0)
+void test_pli() {
+  __pli(0);
+}
+
+// ARM-LABEL: test_plix
+// AArch32: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 0)
+// AArch64: call void @llvm.prefetch(i8* null, i32 0, i32 1, i32 0)
+void test_plix() {
+  __plix(2, 0, 0);
+}
+
 /* 8.7 NOP */
 // ARM-LABEL: test_nop
 // AArch32: call void @llvm.arm.hint(i32 0)

diff --git a/test/Sema/arm_acle.c b/test/Sema/arm_acle.c
index 866626fc38cb73e198a5344c177e04a71a704762..2d1d68a88691c172617a26f0e1ff280ad2ef1ed0 100644 (file)
--- a/test/Sema/arm_acle.c
+++ b/test/Sema/arm_acle.c
@@ -30,3 +30,10 @@ int32_t test_ssat_const_diag(int32_t t, const int32_t v) {
 int32_t test_usat_const_diag(int32_t t, const int32_t v) {
   return __usat(t, v);  // expected-error-re {{argument to {{.*}} must be a constant integer}}
 }
+
+/*
+ * Prefetch intrinsics
+ */
+void test_pldx_const_diag(int32_t i) {
+  __pldx(i, 0, 0, 0);  // expected-error-re {{argument to {{.*}} must be a constant integer}}
+}