[AArch64] Regenerate merge-store tests. NFCI.

Prep work for an upcoming patch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364203 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/AArch64/merge-store.ll b/test/CodeGen/AArch64/merge-store.ll
index 5e4e74321704729f235625b881c3ad38b0ca9e4f..cd9564210e9af68dbfb5d68210f56006b5bc02d2 100644 (file)
--- a/test/CodeGen/AArch64/merge-store.ll
+++ b/test/CodeGen/AArch64/merge-store.ll
@@ -1,13 +1,28 @@
-; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s --check-prefix=SPLITTING --check-prefix=CHECK
-; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone -mattr=+slow-misaligned-128store | FileCheck %s --check-prefixes=CHECK,SPLITTING
+; RUN: llc < %s -mtriple=aarch64-eabi -mattr=-slow-misaligned-128store | FileCheck %s --check-prefixes=CHECK,MISALIGNED
 
 @g0 = external global <3 x float>, align 16
 @g1 = external global <3 x float>, align 4
 
-; CHECK: ldr q[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]], :lo12:g0
-; CHECK: str d[[R0]]
-
 define void @blam() {
+; SPLITTING-LABEL: blam:
+; SPLITTING:       // %bb.0:
+; SPLITTING-NEXT:    adrp x8, g1
+; SPLITTING-NEXT:    add x8, x8, :lo12:g1
+; SPLITTING-NEXT:    adrp x9, g0
+; SPLITTING-NEXT:    ldr q0, [x9, :lo12:g0]
+; SPLITTING-NEXT:    str d0, [x8]
+; SPLITTING-NEXT:    ret
+;
+; MISALIGNED-LABEL: blam:
+; MISALIGNED:       // %bb.0:
+; MISALIGNED-NEXT:    adrp x8, g0
+; MISALIGNED-NEXT:    ldr q0, [x8, :lo12:g0]
+; MISALIGNED-NEXT:    adrp x8, g1
+; MISALIGNED-NEXT:    add x8, x8, :lo12:g1
+; MISALIGNED-NEXT:    str d0, [x8]
+; MISALIGNED-NEXT:    ret
   %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0
   %tmp5 = load <3 x float>, <3 x float>* @g0, align 16
   %tmp6 = extractelement <3 x float> %tmp5, i64 0
@@ -27,6 +42,17 @@ define void @blam() {
 ; the fastness of unaligned accesses was not specified correctly.
 
 define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
+; SPLITTING-LABEL: merge_vec_extract_stores:
+; SPLITTING:       // %bb.0:
+; SPLITTING-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; SPLITTING-NEXT:    str d0, [x0, #24]
+; SPLITTING-NEXT:    str d1, [x0, #32]
+; SPLITTING-NEXT:    ret
+;
+; MISALIGNED-LABEL: merge_vec_extract_stores:
+; MISALIGNED:       // %bb.0:
+; MISALIGNED-NEXT:    stur q0, [x0, #24]
+; MISALIGNED-NEXT:    ret
   %idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3
   %idx1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 4
 
@@ -37,16 +63,8 @@ define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
   store <2 x float> %shuffle1, <2 x float>* %idx1, align 8
   ret void
 
-; MISALIGNED-LABEL:    merge_vec_extract_stores
-; MISALIGNED:          stur   q0, [x0, #24]
-; MISALIGNED-NEXT:     ret
 
 ; FIXME: Ideally we would like to use a generic target for this test, but this relies
 ; on suppressing store pairs.
 
-; SPLITTING-LABEL:    merge_vec_extract_stores
-; SPLITTING:          ext   v1.16b, v0.16b, v0.16b, #8
-; SPLITTING-NEXT:     str   d0, [x0, #24]
-; SPLITTING-NEXT:     str   d1, [x0, #32]
-; SPLITTING-NEXT:     ret
 }