[AArch64][GlobalISel] Teach RBS about G_FNEG default mapping.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352340 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index dad4a3c9a7176b9692ae57faa8095fd04d24219b..d68de4ac587eec6e50a831d37bee86f7f0cd96a9 100644 (file)
--- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -392,6 +392,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
   case TargetOpcode::G_FPEXT:
   case TargetOpcode::G_FPTRUNC:
   case TargetOpcode::G_FCEIL:
+  case TargetOpcode::G_FNEG:
     return true;
   }
   return false;

diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index 6545dfd711587a8275c1ff9a88228273ea9e65bd..08fc1998619fb11a473db90e9ab9ee949c472311 100644 (file)
--- a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -59,6 +59,7 @@
   define void @test_fptrunc_s32_s64() { ret void }
 
   define void @test_fconstant_s32() { ret void }
+  define void @test_fneg_s32() { ret void }
 
   define void @test_fcmp_s32() { ret void }
 
@@ -678,6 +679,19 @@ body: |
     %0(s32) = G_FCONSTANT float 1.0
 ...
 
+---
+name:            test_fneg_s32
+legalized:       true
+body: |
+  bb.0:
+  liveins: $s0
+    ; CHECK-LABEL: name: test_fneg_s32
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
+    ; CHECK: [[FNEG:%[0-9]+]]:fpr(s32) = G_FNEG [[COPY]]
+    %0:_(s32) = COPY $s0
+    %1:_(s32) = G_FNEG %0(s32)
+...
+
 ---
 name:            test_fcmp_s32
 legalized:       true