[ARMv8] Add builtins for CRC instructions.

Patch by Bradley Smith!

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@190931 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/clang/Basic/BuiltinsARM.def b/include/clang/Basic/BuiltinsARM.def
index 2fc3a2ea243ed95c7730a53d3d6790fbea0a4ad0..1d8087921e9d4feb67b017f4d12e52e5c72b4128 100644 (file)
--- a/include/clang/Basic/BuiltinsARM.def
+++ b/include/clang/Basic/BuiltinsARM.def
@@ -48,6 +48,16 @@ BUILTIN(__builtin_arm_cdp2, "vUiUiUiUiUiUi", "")
 BUILTIN(__builtin_arm_mcrr, "vUiUiUiUiUi", "")
 BUILTIN(__builtin_arm_mcrr2, "vUiUiUiUiUi", "")
 
+// CRC32
+BUILTIN(__builtin_arm_crc32b, "UiUiUc", "nc")
+BUILTIN(__builtin_arm_crc32cb, "UiUiUc", "nc")
+BUILTIN(__builtin_arm_crc32h, "UiUiUs", "nc")
+BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc")
+BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc")
+BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc")
+
 // NEON
 #define GET_NEON_BUILTINS
 #include "clang/Basic/arm_neon.inc"

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 02baa1fe629f9479a8009113aab41c01b922dec5..56068b7d3644d75b5c016d9d0069b27e6637d7f5 100644 (file)
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -3829,6 +3829,9 @@ public:
     // when Neon instructions are actually available.
     if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
       Builder.defineMacro("__ARM_NEON__");
+
+    if (CPUArch.startswith("8"))
+      Builder.defineMacro("__ARM_FEATURE_CRC32");
   }
   virtual void getTargetBuiltins(const Builtin::Info *&Records,
                                  unsigned &NumRecords) const {

diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp
index e6cfe64471eb48e5c58c94cf79d546283c9955d8..4b4c8f481cb2b141425e87af74cf47a50a3bb25c 100644 (file)
--- a/lib/CodeGen/CGBuiltin.cpp
+++ b/lib/CodeGen/CGBuiltin.cpp
@@ -2153,6 +2153,49 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
     return Builder.CreateCall(F);
   }
 
+  // CRC32
+  Intrinsic::ID CRCIntrinsicID = Intrinsic::not_intrinsic;
+  switch (BuiltinID) {
+  case ARM::BI__builtin_arm_crc32b:
+    CRCIntrinsicID = Intrinsic::arm_crc32b; break;
+  case ARM::BI__builtin_arm_crc32cb:
+    CRCIntrinsicID = Intrinsic::arm_crc32cb; break;
+  case ARM::BI__builtin_arm_crc32h:
+    CRCIntrinsicID = Intrinsic::arm_crc32h; break;
+  case ARM::BI__builtin_arm_crc32ch:
+    CRCIntrinsicID = Intrinsic::arm_crc32ch; break;
+  case ARM::BI__builtin_arm_crc32w:
+  case ARM::BI__builtin_arm_crc32d:
+    CRCIntrinsicID = Intrinsic::arm_crc32w; break;
+  case ARM::BI__builtin_arm_crc32cw:
+  case ARM::BI__builtin_arm_crc32cd:
+    CRCIntrinsicID = Intrinsic::arm_crc32cw; break;
+  }
+
+  if (CRCIntrinsicID != Intrinsic::not_intrinsic) {
+    Value *Arg0 = EmitScalarExpr(E->getArg(0));
+    Value *Arg1 = EmitScalarExpr(E->getArg(1));
+
+    // crc32{c,}d intrinsics are implemnted as two calls to crc32{c,}w
+    // intrinsics, hence we need different codegen for these cases.
+    if (BuiltinID == ARM::BI__builtin_arm_crc32d ||
+        BuiltinID == ARM::BI__builtin_arm_crc32cd) {
+      Value *C1 = llvm::ConstantInt::get(Int64Ty, 32);
+      Value *Arg1a = Builder.CreateTruncOrBitCast(Arg1, Int32Ty);
+      Value *Arg1b = Builder.CreateLShr(Arg1, C1);
+      Arg1b = Builder.CreateTruncOrBitCast(Arg1b, Int32Ty);
+
+      Function *F = CGM.getIntrinsic(CRCIntrinsicID);
+      Value *Res = Builder.CreateCall2(F, Arg0, Arg1a);
+      return Builder.CreateCall2(F, Res, Arg1b);
+    } else {
+      Arg1 = Builder.CreateZExtOrBitCast(Arg1, Int32Ty);
+
+      Function *F = CGM.getIntrinsic(CRCIntrinsicID);
+      return Builder.CreateCall2(F, Arg0, Arg1);
+    }
+  }
+
   SmallVector<Value*, 4> Ops;
   llvm::Value *Align = 0;
   for (unsigned i = 0, e = E->getNumArgs() - 1; i != e; i++) {

diff --git a/test/CodeGen/arm-crc32.c b/test/CodeGen/arm-crc32.c
new file mode 100644 (file)
index 0000000..d49f20e
--- /dev/null
+++ b/test/CodeGen/arm-crc32.c
@@ -0,0 +1,63 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang_cc1 -triple armv8-none-linux-gnueabi \
+// RUN:   -O3 -S -emit-llvm -o - %s | FileCheck %s
+
+int crc32b(int a, char b)
+{
+        return __builtin_arm_crc32b(a,b);
+// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
+// CHECK: call i32 @llvm.arm.crc32b(i32 %a, i32 [[T0]])
+}
+
+int crc32cb(int a, char b)
+{
+        return __builtin_arm_crc32cb(a,b);
+// CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
+// CHECK: call i32 @llvm.arm.crc32cb(i32 %a, i32 [[T0]])
+}
+
+int crc32h(int a, short b)
+{
+        return __builtin_arm_crc32h(a,b);
+// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
+// CHECK: call i32 @llvm.arm.crc32h(i32 %a, i32 [[T0]])
+}
+
+int crc32ch(int a, short b)
+{
+        return __builtin_arm_crc32ch(a,b);
+// CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
+// CHECK: call i32 @llvm.arm.crc32ch(i32 %a, i32 [[T0]])
+}
+
+int crc32w(int a, int b)
+{
+        return __builtin_arm_crc32w(a,b);
+// CHECK: call i32 @llvm.arm.crc32w(i32 %a, i32 %b)
+}
+
+int crc32cw(int a, int b)
+{
+        return __builtin_arm_crc32cw(a,b);
+// CHECK: call i32 @llvm.arm.crc32cw(i32 %a, i32 %b)
+}
+
+int crc32d(int a, long long b)
+{
+        return __builtin_arm_crc32d(a,b);
+// CHECK: [[T0:%[0-9]+]] = trunc i64 %b to i32
+// CHECK: [[T1:%[0-9]+]] = lshr i64 %b, 32
+// CHECK: [[T2:%[0-9]+]] = trunc i64 [[T1]] to i32
+// CHECK: [[T3:%[0-9]+]] = tail call i32 @llvm.arm.crc32w(i32 %a, i32 [[T0]])
+// CHECK: call i32 @llvm.arm.crc32w(i32 [[T3]], i32 [[T2]])
+}
+
+int crc32cd(int a, long long b)
+{
+        return __builtin_arm_crc32cd(a,b);
+// CHECK: [[T0:%[0-9]+]] = trunc i64 %b to i32
+// CHECK: [[T1:%[0-9]+]] = lshr i64 %b, 32
+// CHECK: [[T2:%[0-9]+]] = trunc i64 [[T1]] to i32
+// CHECK: [[T3:%[0-9]+]] = tail call i32 @llvm.arm.crc32cw(i32 %a, i32 [[T0]])
+// CHECK: call i32 @llvm.arm.crc32cw(i32 [[T3]], i32 [[T2]])
+}

diff --git a/test/Preprocessor/arm-target-features.c b/test/Preprocessor/arm-target-features.c
new file mode 100644 (file)
index 0000000..56c893b
--- /dev/null
+++ b/test/Preprocessor/arm-target-features.c
@@ -0,0 +1,11 @@
+// RUN: %clang -target armv8a-none-linux-gnu -x c -E -dM %s -o - | FileCheck %s
+// CHECK: __ARMEL__ 1
+// CHECK: __ARM_ARCH 8
+// CHECK: __ARM_ARCH_8A__ 1
+// CHECK: __ARM_FEATURE_CRC32 1
+
+// RUN: %clang -target armv7a-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-V7 %s
+// CHECK-V7: __ARMEL__ 1
+// CHECK-V7: __ARM_ARCH 7
+// CHECK-V7: __ARM_ARCH_7A__ 1
+// CHECK-NOT-V7: __ARM_FEATURE_CRC32