[ARM GlobalISel] Fix selection of G_SELECT

G_SELECT uses a 1-bit scalar for the condition, and is currently
implemented with a plain CMPri against 0. This means that values such as
0x1110 are interpreted as true, when instead the higher bits should be
treated as undefined and therefore ignored. Replace the CMPri with a
TSTri against 0x1, which performs an implicit AND, yielding the expected
result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357153 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp
index a9f1f6bbc224ee81b2aaeaeebdad8b74c12fc566..d0b63d676da1af63dac17ba97d88fcc08509bee8 100644 (file)
--- a/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -111,7 +111,6 @@ private:
     unsigned MOVCCi;
 
     // Used for G_SELECT
-    unsigned CMPri;
     unsigned MOVCCr;
 
     unsigned TSTri;
@@ -319,7 +318,6 @@ ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) {
   STORE_OPCODE(MOVi, MOVi);
   STORE_OPCODE(MOVCCi, MOVCCi);
 
-  STORE_OPCODE(CMPri, CMPri);
   STORE_OPCODE(MOVCCr, MOVCCr);
 
   STORE_OPCODE(TSTri, TSTri);
@@ -767,13 +765,13 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
   auto InsertBefore = std::next(MIB->getIterator());
   auto &DbgLoc = MIB->getDebugLoc();
 
-  // Compare the condition to 0.
+  // Compare the condition to 1.
   auto CondReg = MIB->getOperand(1).getReg();
   assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
          "Unsupported types for select operation");
-  auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.CMPri))
+  auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
                   .addUse(CondReg)
-                  .addImm(0)
+                  .addImm(1)
                   .add(predOps(ARMCC::AL));
   if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
     return false;

diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index a08466d0cdab9c7a52c73faab46d6556034189ca..01b0893b96e2b968a3a62c42e88aa4f8e88a713c 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -881,7 +881,7 @@ body:             |
     %2(s1) = G_TRUNC %1(s32)
 
     %3(s32) = G_SELECT %2(s1),  %0, %1
-    ; CHECK: CMPri [[VREGY]], 0, 14, $noreg, implicit-def $cpsr
+    ; CHECK: TSTri [[VREGY]], 1, 14, $noreg, implicit-def $cpsr
     ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
 
     $r0 = COPY %3(s32)
@@ -919,7 +919,7 @@ body:             |
     %3(s1) = G_TRUNC %2(s32)
 
     %4(p0) = G_SELECT %3(s1),  %0, %1
-    ; CHECK: CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr
+    ; CHECK: TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
     ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
 
     $r0 = COPY %4(p0)

diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/test/CodeGen/ARM/GlobalISel/arm-isel.ll
index 7162815a7f70a4ecff71fb1eef70047182aef61d..49300cac957437e4f18c006d590fd0e9d912dba0 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-isel.ll
+++ b/test/CodeGen/ARM/GlobalISel/arm-isel.ll
@@ -405,7 +405,7 @@ entry:
 
 define arm_aapcscc i32 @test_select_i32(i32 %a, i32 %b, i1 %cond) {
 ; CHECK-LABEL: test_select_i32
-; CHECK: cmp r2, #0
+; CHECK: tst r2, #1
 ; CHECK: moveq r0, r1
 ; CHECK: bx lr
 entry:
@@ -415,7 +415,7 @@ entry:
 
 define arm_aapcscc i32* @test_select_ptr(i32* %a, i32* %b, i1 %cond) {
 ; CHECK-LABEL: test_select_ptr
-; CHECK: cmp r2, #0
+; CHECK: tst r2, #1
 ; CHECK: moveq r0, r1
 ; CHECK: bx lr
 entry:

diff --git a/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir b/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
index d1a482b5514c50f0d43974f699e3684d17f25db3..290ce548a3be5be8cb939df05c4935100853d871 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
@@ -29,7 +29,7 @@ body:             |
     ; CHECK: [[VREGC:%[0-9]+]]:gprnopc = COPY [[VREGY]]
 
     %3(s32) = G_SELECT %2(s1),  %0, %1
-    ; CHECK: t2CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr
+    ; CHECK: t2TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
     ; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
 
     $r0 = COPY %3(s32)
@@ -68,7 +68,7 @@ body:             |
     ; CHECK: [[VREGC:%[0-9]+]]:gprnopc = COPY [[VREGC32]]
 
     %4(p0) = G_SELECT %3(s1),  %0, %1
-    ; CHECK: t2CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr
+    ; CHECK: t2TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
     ; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
 
     $r0 = COPY %4(p0)