[TableGen] Add EncoderMethod to RegisterOperand

Reviewers: stoklund, grosbach, vpykhtin

Differential Revision: https://reviews.llvm.org/D32493

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303044 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index fc35b4527bc379e6e7ae265a74dd8c35a08b323f..6f44292c47ed0eda7fbaf992064a7e74776a6e2b 100644 (file)
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -680,6 +680,11 @@ class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
   // this type. The method normally will just use an alt-name index to look
   // up the name to print. Default to the generic printOperand().
   string PrintMethod = pm;
+
+  // EncoderMethod - The target method name to call to encode this register
+  // operand.
+  string EncoderMethod = "";
+
   // ParserMatchClass - The "match class" that operands of this type fit
   // in. Match classes are used to define the order in which instructions are
   // match, to ensure that which instructions gets matched is deterministic.

diff --git a/test/TableGen/AsmVariant.td b/test/TableGen/AsmVariant.td
index 6c50241e5ae15aede787632c16b49f431dc0cc0f..cb5d32385d3b36f594e8b621ab158e2a6f36e741 100644 (file)
--- a/test/TableGen/AsmVariant.td
+++ b/test/TableGen/AsmVariant.td
@@ -1,6 +1,6 @@
 // RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
 
-// Check that cpecifying AsmVariant works correctly
+// Check that specifying AsmVariant works correctly
 
 include "llvm/Target/Target.td"
 

diff --git a/test/TableGen/RegisterEncoder.td b/test/TableGen/RegisterEncoder.td
new file mode 100644 (file)
index 0000000..a0472c5
--- /dev/null
+++ b/test/TableGen/RegisterEncoder.td
@@ -0,0 +1,35 @@
+// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
+
+// Check that EncoderMethod for RegisterOperand is working correctly
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo { }
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+}
+
+def Reg : Register<"reg">;
+
+def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
+
+def RegOperand : RegisterOperand<RegClass> {
+  let EncoderMethod = "barEncoder";
+}
+
+def foo : Instruction {
+  let Size = 1;
+
+  let OutOperandList = (outs);
+  let InOperandList = (ins RegOperand:$bar);
+
+  bits<8> bar;
+  bits<8> Inst = bar;
+}
+
+// CHECK: case ::foo: {
+// CHECK:   op = barEncoder
+// CHECK:   Value |= op & UINT64_C(255);
+// CHECK:   break;
+// CHECK: }
\ No newline at end of file

diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index bb2ec2a64e49e04360d2f23cdb3ef84f9bc35319..f4a7609909999d52b81154f3b8fa8baf0655991a 100644 (file)
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -77,6 +77,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
       PrintMethod = Rec->getValueAsString("PrintMethod");
       OperandType = Rec->getValueAsString("OperandType");
       OperandNamespace = Rec->getValueAsString("OperandNamespace");
+      EncoderMethod = Rec->getValueAsString("EncoderMethod");
     } else if (Rec->isSubClassOf("Operand")) {
       PrintMethod = Rec->getValueAsString("PrintMethod");
       OperandType = Rec->getValueAsString("OperandType");