AArch64: don't try to emit an add (shifted reg) for SP.

The "Add/sub (shifted reg)" instructions use the 31 encoding for xzr and wzr
rather than the SP, so we need to use different variants.

Situations where this actually comes up are rare enough (see test-case) that I
think falling back to DAG is fine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305230 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64FastISel.cpp b/lib/Target/AArch64/AArch64FastISel.cpp
index e8fcf1a0e9b71388a25631fce14bda9f08ab4962..7bf2097c17cee1ff22d9fd4ac9468682e84707c0 100644 (file)
--- a/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/lib/Target/AArch64/AArch64FastISel.cpp
@@ -1282,6 +1282,10 @@ unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
                                         bool WantResult) {
   assert(LHSReg && RHSReg && "Invalid register number.");
 
+  if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP ||
+      RHSReg == AArch64::SP || RHSReg == AArch64::WSP)
+    return 0;
+
   if (RetVT != MVT::i32 && RetVT != MVT::i64)
     return 0;
 
@@ -1362,6 +1366,8 @@ unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
                                         uint64_t ShiftImm, bool SetFlags,
                                         bool WantResult) {
   assert(LHSReg && RHSReg && "Invalid register number.");
+  assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP &&
+         RHSReg != AArch64::SP && RHSReg != AArch64::WSP);
 
   if (RetVT != MVT::i32 && RetVT != MVT::i64)
     return 0;
@@ -1403,6 +1409,8 @@ unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
                                         uint64_t ShiftImm, bool SetFlags,
                                         bool WantResult) {
   assert(LHSReg && RHSReg && "Invalid register number.");
+  assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR &&
+         RHSReg != AArch64::XZR && RHSReg != AArch64::WZR);
 
   if (RetVT != MVT::i32 && RetVT != MVT::i64)
     return 0;

diff --git a/test/CodeGen/AArch64/fast-isel-sp-adjust.ll b/test/CodeGen/AArch64/fast-isel-sp-adjust.ll
new file mode 100644 (file)
index 0000000..9201d1b
--- /dev/null
+++ b/test/CodeGen/AArch64/fast-isel-sp-adjust.ll
@@ -0,0 +1,288 @@
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
+; RUN: not llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel-abort=3 %s 2> %t
+; RUN: FileCheck %s --check-prefix=CHECK-ERRORS < %t
+
+; The issue here is that FastISel cannot emit an ADDrr where one of the inputs
+; is SP. This only ever crops up with function calls, and then only if the
+; argument is at an offset > 2^12 * size from SP.
+
+; If FastISel ever starts coping with this and emits an "add xD, sp, xM" it's
+; critical to check the encoding as well as the textual assembly. An ADDXrs with
+; SP as an operand will still print with SP, but will actually mean XZR.
+
+; CHECK-ERRORS: LLVM ERROR: FastISel missed call
+
+; CHECK-LABEL: foo:
+; CHECK-DAG: mov x[[SP:[0-9]+]], sp
+; CHECK-DAG: mov [[TMP:w[0-9]+]], #4104
+; CHECK: mov w[[OFFSET:[0-9]+]], [[TMP]]
+; CHECK: strb w0, [x[[SP]], x[[OFFSET]]]
+
+define void @foo(i8 %in) {
+  call void @bar(i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; All regs gone.
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 32
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 64
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 128
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 256
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 512
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 1024
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 2048
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef,
+                 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 4096
+                 i64 undef, ; sp + 4104 (i.e. not uimm12 or uimm12 << 12).
+                 i8 %in)
+  ret void
+}
+
+declare void @bar(i64, i64, i64, i64,
+                  i64, i64, i64, i64, ; All regs gone.
+                  i64, i64, i64, i64, ; sp + 32
+                  i64, i64, i64, i64, ; sp + 64
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64, ; sp + 128
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64, ; sp + 256
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64, ; sp + 512
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64, ; sp + 1024
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64, ; sp + 2048
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64,
+                  i64, i64, i64, i64, ; sp + 4096
+                  i64,
+                  i8)