]> granicus.if.org Git - llvm/commitdiff
[GlobalISel][X86] For now don't handle not trivial function arguments lowering.
authorIgor Breger <igor.breger@intel.com>
Wed, 5 Jul 2017 11:40:35 +0000 (11:40 +0000)
committerIgor Breger <igor.breger@intel.com>
Wed, 5 Jul 2017 11:40:35 +0000 (11:40 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307142 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86CallLowering.cpp

index bb549dc048840738a361d7e5ae5578a3f191e91e..99aeec67c326648a261b9ed5ebb383952bd2f479 100644 (file)
@@ -195,8 +195,18 @@ bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   SmallVector<ArgInfo, 8> SplitArgs;
   unsigned Idx = 0;
   for (auto &Arg : F.args()) {
+
+    // TODO: handle not simple cases.
+    if (Arg.hasAttribute(Attribute::ByVal) ||
+        Arg.hasAttribute(Attribute::InReg) ||
+        Arg.hasAttribute(Attribute::StructRet) ||
+        Arg.hasAttribute(Attribute::SwiftSelf) ||
+        Arg.hasAttribute(Attribute::SwiftError) ||
+        Arg.hasAttribute(Attribute::Nest))
+      return false;
+
     ArgInfo OrigArg(VRegs[Idx], Arg.getType());
-    setArgFlags(OrigArg, Idx + 1, DL, F);
+    setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
     if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
                            [&](ArrayRef<unsigned> Regs) {
                              MIRBuilder.buildMerge(VRegs[Idx], Regs);