[InstSimplify] add tests for PR27689; regenerate checks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273128 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Transforms/InstSimplify/AndOrXor.ll b/test/Transforms/InstSimplify/AndOrXor.ll
index 11f2524109cbe1653cd96d4d7064a5651337ee59..a97844a7be8eede792899c1fef20251f02d6a90f 100644 (file)
--- a/test/Transforms/InstSimplify/AndOrXor.ll
+++ b/test/Transforms/InstSimplify/AndOrXor.ll
@@ -1,9 +1,9 @@
-; NOTE: Assertions have been autogenerated by update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i64 @pow2(i32 %x) {
 ; CHECK-LABEL: @pow2(
-; CHECK:         [[NEGX:%.*]] = sub i32 0, %x
+; CHECK-NEXT:    [[NEGX:%.*]] = sub i32 0, %x
 ; CHECK-NEXT:    [[X2:%.*]] = and i32 %x, [[NEGX]]
 ; CHECK-NEXT:    [[E:%.*]] = zext i32 [[X2]] to i64
 ; CHECK-NEXT:    ret i64 [[E]]
@@ -18,7 +18,7 @@ define i64 @pow2(i32 %x) {
 
 define i64 @pow2b(i32 %x) {
 ; CHECK-LABEL: @pow2b(
-; CHECK:         [[SH:%.*]] = shl i32 2, %x
+; CHECK-NEXT:    [[SH:%.*]] = shl i32 2, %x
 ; CHECK-NEXT:    [[E:%.*]] = zext i32 [[SH]] to i64
 ; CHECK-NEXT:    ret i64 [[E]]
 ;
@@ -31,7 +31,7 @@ define i64 @pow2b(i32 %x) {
 
 define i32 @sub_neg_nuw(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sub_neg_nuw(
-; CHECK:         ret i32 %x
+; CHECK-NEXT:    ret i32 %x
 ;
   %neg = sub nuw i32 0, %y
   %sub = sub i32 %x, %neg
@@ -40,7 +40,7 @@ define i32 @sub_neg_nuw(i32 %x, i32 %y) {
 
 define i1 @and_of_icmps0(i32 %b) {
 ; CHECK-LABEL: @and_of_icmps0(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %1 = add i32 %b, 2
   %2 = icmp ult i32 %1, 4
@@ -51,7 +51,7 @@ define i1 @and_of_icmps0(i32 %b) {
 
 define i1 @and_of_icmps1(i32 %b) {
 ; CHECK-LABEL: @and_of_icmps1(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %1 = add nsw i32 %b, 2
   %2 = icmp slt i32 %1, 4
@@ -62,7 +62,7 @@ define i1 @and_of_icmps1(i32 %b) {
 
 define i1 @and_of_icmps2(i32 %b) {
 ; CHECK-LABEL: @and_of_icmps2(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %1 = add i32 %b, 2
   %2 = icmp ule i32 %1, 3
@@ -73,7 +73,7 @@ define i1 @and_of_icmps2(i32 %b) {
 
 define i1 @and_of_icmps3(i32 %b) {
 ; CHECK-LABEL: @and_of_icmps3(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %1 = add nsw i32 %b, 2
   %2 = icmp sle i32 %1, 3
@@ -84,7 +84,7 @@ define i1 @and_of_icmps3(i32 %b) {
 
 define i1 @and_of_icmps4(i32 %b) {
 ; CHECK-LABEL: @and_of_icmps4(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %1 = add nuw i32 %b, 2
   %2 = icmp ult i32 %1, 4
@@ -95,7 +95,7 @@ define i1 @and_of_icmps4(i32 %b) {
 
 define i1 @and_of_icmps5(i32 %b) {
 ; CHECK-LABEL: @and_of_icmps5(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %1 = add nuw i32 %b, 2
   %2 = icmp ule i32 %1, 3
@@ -106,7 +106,7 @@ define i1 @and_of_icmps5(i32 %b) {
 
 define i1 @or_of_icmps0(i32 %b) {
 ; CHECK-LABEL: @or_of_icmps0(
-; CHECK:         ret i1 true
+; CHECK-NEXT:    ret i1 true
 ;
   %1 = add i32 %b, 2
   %2 = icmp uge i32 %1, 4
@@ -117,7 +117,7 @@ define i1 @or_of_icmps0(i32 %b) {
 
 define i1 @or_of_icmps1(i32 %b) {
 ; CHECK-LABEL: @or_of_icmps1(
-; CHECK:         ret i1 true
+; CHECK-NEXT:    ret i1 true
 ;
   %1 = add nsw i32 %b, 2
   %2 = icmp sge i32 %1, 4
@@ -128,7 +128,7 @@ define i1 @or_of_icmps1(i32 %b) {
 
 define i1 @or_of_icmps2(i32 %b) {
 ; CHECK-LABEL: @or_of_icmps2(
-; CHECK:         ret i1 true
+; CHECK-NEXT:    ret i1 true
 ;
   %1 = add i32 %b, 2
   %2 = icmp ugt i32 %1, 3
@@ -139,7 +139,7 @@ define i1 @or_of_icmps2(i32 %b) {
 
 define i1 @or_of_icmps3(i32 %b) {
 ; CHECK-LABEL: @or_of_icmps3(
-; CHECK:         ret i1 true
+; CHECK-NEXT:    ret i1 true
 ;
   %1 = add nsw i32 %b, 2
   %2 = icmp sgt i32 %1, 3
@@ -150,7 +150,7 @@ define i1 @or_of_icmps3(i32 %b) {
 
 define i1 @or_of_icmps4(i32 %b) {
 ; CHECK-LABEL: @or_of_icmps4(
-; CHECK:         ret i1 true
+; CHECK-NEXT:    ret i1 true
 ;
   %1 = add nuw i32 %b, 2
   %2 = icmp uge i32 %1, 4
@@ -161,7 +161,7 @@ define i1 @or_of_icmps4(i32 %b) {
 
 define i1 @or_of_icmps5(i32 %b) {
 ; CHECK-LABEL: @or_of_icmps5(
-; CHECK:         ret i1 true
+; CHECK-NEXT:    ret i1 true
 ;
   %1 = add nuw i32 %b, 2
   %2 = icmp ugt i32 %1, 3
@@ -172,7 +172,7 @@ define i1 @or_of_icmps5(i32 %b) {
 
 define i32 @neg_nuw(i32 %x) {
 ; CHECK-LABEL: @neg_nuw(
-; CHECK:         ret i32 0
+; CHECK-NEXT:    ret i32 0
 ;
   %neg = sub nuw i32 0, %x
   ret i32 %neg
@@ -180,7 +180,7 @@ define i32 @neg_nuw(i32 %x) {
 
 define i1 @and_icmp1(i32 %x, i32 %y) {
 ; CHECK-LABEL: @and_icmp1(
-; CHECK:         [[TMP1:%.*]] = icmp ult i32 %x, %y
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 %x, %y
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %1 = icmp ult i32 %x, %y
@@ -191,7 +191,7 @@ define i1 @and_icmp1(i32 %x, i32 %y) {
 
 define i1 @and_icmp2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @and_icmp2(
-; CHECK:         ret i1 false
+; CHECK-NEXT:    ret i1 false
 ;
   %1 = icmp ult i32 %x, %y
   %2 = icmp eq i32 %y, 0
@@ -201,7 +201,7 @@ define i1 @and_icmp2(i32 %x, i32 %y) {
 
 define i1 @or_icmp1(i32 %x, i32 %y) {
 ; CHECK-LABEL: @or_icmp1(
-; CHECK:         [[TMP1:%.*]] = icmp ne i32 %y, 0
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i32 %y, 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %1 = icmp ult i32 %x, %y
@@ -212,7 +212,7 @@ define i1 @or_icmp1(i32 %x, i32 %y) {
 
 define i1 @or_icmp2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @or_icmp2(
-; CHECK:         ret i1 true
+; CHECK-NEXT:    ret i1 true
 ;
   %1 = icmp uge i32 %x, %y
   %2 = icmp ne i32 %y, 0
@@ -222,7 +222,7 @@ define i1 @or_icmp2(i32 %x, i32 %y) {
 
 define i1 @or_icmp3(i32 %x, i32 %y) {
 ; CHECK-LABEL: @or_icmp3(
-; CHECK:         [[TMP1:%.*]] = icmp uge i32 %x, %y
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp uge i32 %x, %y
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
   %1 = icmp uge i32 %x, %y
@@ -231,3 +231,37 @@ define i1 @or_icmp3(i32 %x, i32 %y) {
   ret i1 %3
 }
 
+define i32 @and_of_zexted_icmps(i32 %i) {
+; CHECK-LABEL: @and_of_zexted_icmps(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 %i, 0
+; CHECK-NEXT:    [[CONV:%.*]] = zext i1 [[CMP]] to i32
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ugt i32 %i, 4
+; CHECK-NEXT:    [[CONV2:%.*]] = zext i1 [[CMP1]] to i32
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[CONV]], [[CONV2]]
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %cmp = icmp eq i32 %i, 0
+  %conv = zext i1 %cmp to i32
+  %cmp1 = icmp ugt i32 %i, 4
+  %conv2 = zext i1 %cmp1 to i32
+  %and = and i32 %conv, %conv2
+  ret i32 %and
+}
+
+define <4 x i32> @and_of_zexted_icmps_vec(<4 x i32> %i) {
+; CHECK-LABEL: @and_of_zexted_icmps_vec(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> %i, zeroinitializer
+; CHECK-NEXT:    [[CONV:%.*]] = zext <4 x i1> [[CMP]] to <4 x i32>
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt <4 x i32> %i, zeroinitializer
+; CHECK-NEXT:    [[CONV2:%.*]] = zext <4 x i1> [[CMP1]] to <4 x i32>
+; CHECK-NEXT:    [[AND:%.*]] = and <4 x i32> [[CONV]], [[CONV2]]
+; CHECK-NEXT:    ret <4 x i32> [[AND]]
+;
+  %cmp = icmp eq <4 x i32> %i, zeroinitializer
+  %conv = zext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp slt <4 x i32> %i, zeroinitializer
+  %conv2 = zext <4 x i1> %cmp1 to <4 x i32>
+  %and = and <4 x i32> %conv, %conv2
+  ret <4 x i32> %and
+}
+