[mips][msa] Remove range checks for non-immediate sld.[bhwd] instructions

Removes immediate range checks for these instructions, since they have GPR
rt as their input operand.

Patch by Stefan Maksimovic.

Differential Revision: https://reviews.llvm.org/D30693

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@297485 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Sema/SemaChecking.cpp b/lib/Sema/SemaChecking.cpp
index eef8f557744cbe7935130fb14df6ac9f5cd4d8be..57d765de688f79dd4a4a5d187676a9e1d517f976 100644 (file)
--- a/lib/Sema/SemaChecking.cpp
+++ b/lib/Sema/SemaChecking.cpp
@@ -1619,28 +1619,24 @@ bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
   case Mips::BI__builtin_msa_copy_u_b:
   case Mips::BI__builtin_msa_insve_b:
   case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break;
-  case Mips::BI__builtin_msa_sld_b:
   case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break;
   // These intrinsics take an unsigned 3 bit immediate.
   case Mips::BI__builtin_msa_copy_s_h:
   case Mips::BI__builtin_msa_copy_u_h:
   case Mips::BI__builtin_msa_insve_h:
   case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break;
-  case Mips::BI__builtin_msa_sld_h:
   case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break;
   // These intrinsics take an unsigned 2 bit immediate.
   case Mips::BI__builtin_msa_copy_s_w:
   case Mips::BI__builtin_msa_copy_u_w:
   case Mips::BI__builtin_msa_insve_w:
   case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break;
-  case Mips::BI__builtin_msa_sld_w:
   case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break;
   // These intrinsics take an unsigned 1 bit immediate.
   case Mips::BI__builtin_msa_copy_s_d:
   case Mips::BI__builtin_msa_copy_u_d:
   case Mips::BI__builtin_msa_insve_d:
   case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break;
-  case Mips::BI__builtin_msa_sld_d:
   case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
   // Memory offsets and immediate loads.
   // These intrinsics take a signed 10 bit immediate.

diff --git a/test/CodeGen/builtins-mips-msa-error.c b/test/CodeGen/builtins-mips-msa-error.c
index fcdf6f0c48c84fa16e444d04ba8b99448d657aa5..7aba8ff9b0f8b3d1d6790ce2ba9192c97ff9b393 100644 (file)
--- a/test/CodeGen/builtins-mips-msa-error.c
+++ b/test/CodeGen/builtins-mips-msa-error.c
@@ -162,11 +162,6 @@ void test(void) {
   v8i16_r = __msa_shf_h(v8i16_a, 256);               // CHECK: warning: argument should be a value from 0 to 255}}
   v4i32_r = __msa_shf_w(v4i32_a, 256);               // CHECK: warning: argument should be a value from 0 to 255}}
 
-  v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16);      // expected-error {{argument should be a value from 0 to 15}}
-  v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8);       // expected-error {{argument should be a value from 0 to 7}}
-  v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4);       // expected-error {{argument should be a value from 0 to 3}}
-  v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2);       // expected-error {{argument should be a value from 0 to 1}}
-
   v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 16);      // expected-error {{argument should be a value from 0 to 15}}
   v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 8);       // expected-error {{argument should be a value from 0 to 7}}
   v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 4);       // expected-error {{argument should be a value from 0 to 3}}
@@ -358,11 +353,6 @@ void test(void) {
   v8i16_r = __msa_shf_h(v8i16_a, -1);                // CHECK: warning: argument should be a value from 0 to 255}}
   v4i32_r = __msa_shf_w(v4i32_a, -1);                // CHECK: warning: argument should be a value from 0 to 255}}
 
-  v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, -17);      // expected-error {{argument should be a value from 0 to 15}}
-  v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, -8);       // expected-error {{argument should be a value from 0 to 7}}
-  v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, -4);       // expected-error {{argument should be a value from 0 to 3}}
-  v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, -2);       // expected-error {{argument should be a value from 0 to 1}}
-
   v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, -17);     // expected-error {{argument should be a value from 0 to 15}}
   v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, -8);      // expected-error {{argument should be a value from 0 to 7}}
   v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, -4);      // expected-error {{argument should be a value from 0 to 3}}

diff --git a/test/CodeGen/builtins-mips-msa.c b/test/CodeGen/builtins-mips-msa.c
index 125679545601f37f80b7fdd3b980f679b5c7f74d..2e46bfd9957cee70ecf6b8de25c673aa0e7a7728 100644 (file)
--- a/test/CodeGen/builtins-mips-msa.c
+++ b/test/CodeGen/builtins-mips-msa.c
@@ -699,6 +699,11 @@ void test(void) {
   v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 3); // CHECK: call <4  x i32> @llvm.mips.sld.w(
   v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 1); // CHECK: call <2  x i64> @llvm.mips.sld.d(
 
+  v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 16); // CHECK: call <16 x i8>  @llvm.mips.sld.b(
+  v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 8); // CHECK: call <8  x i16> @llvm.mips.sld.h(
+  v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 4); // CHECK: call <4  x i32> @llvm.mips.sld.w(
+  v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 2); // CHECK: call <2  x i64> @llvm.mips.sld.d(
+
   v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 7); // CHECK: call <16 x i8>  @llvm.mips.sldi.b(
   v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 3); // CHECK: call <8  x i16> @llvm.mips.sldi.h(
   v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 2); // CHECK: call <4  x i32> @llvm.mips.sldi.w(