Normalize line endings. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320389 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrExtension.td b/lib/Target/X86/X86InstrExtension.td
index bb391fd9c8174d0a82ed044218227495bcd8a3ec..2a8ab0069b1eb33b3717fbbc8a4676089a8e2540 100644 (file)
--- a/lib/Target/X86/X86InstrExtension.td
+++ b/lib/Target/X86/X86InstrExtension.td
@@ -9,36 +9,36 @@
 //
 // This file describes the sign and zero extension operations.
 //
-//===----------------------------------------------------------------------===//\r
-\r
-let hasSideEffects = 0 in {\r
-  let Defs = [AX], Uses = [AL] in // AX = signext(AL)\r
-  def CBW : I<0x98, RawFrm, (outs), (ins),\r
-              "{cbtw|cbw}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;\r
-  let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)\r
-  def CWDE : I<0x98, RawFrm, (outs), (ins),\r
-              "{cwtl|cwde}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;\r
-\r
-  let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)\r
-  def CWD : I<0x99, RawFrm, (outs), (ins),\r
-              "{cwtd|cwd}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;\r
-  let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)\r
-  def CDQ : I<0x99, RawFrm, (outs), (ins),\r
-              "{cltd|cdq}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;\r
-\r
-\r
-  let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)\r
-  def CDQE : RI<0x98, RawFrm, (outs), (ins),\r
-               "{cltq|cdqe}", [], IIC_CBW>, Sched<[WriteALU]>;\r
-\r
-  let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)\r
-  def CQO  : RI<0x99, RawFrm, (outs), (ins),\r
-                "{cqto|cqo}", [], IIC_CBW>, Sched<[WriteALU]>;\r
-}\r
-\r
-// Sign/Zero extenders\r
-let hasSideEffects = 0 in {\r
-def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),\r
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0 in {
+  let Defs = [AX], Uses = [AL] in // AX = signext(AL)
+  def CBW : I<0x98, RawFrm, (outs), (ins),
+              "{cbtw|cbw}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+  let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
+  def CWDE : I<0x98, RawFrm, (outs), (ins),
+              "{cwtl|cwde}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
+
+  let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
+  def CWD : I<0x99, RawFrm, (outs), (ins),
+              "{cwtd|cwd}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+  let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
+  def CDQ : I<0x99, RawFrm, (outs), (ins),
+              "{cltd|cdq}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
+
+
+  let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
+  def CDQE : RI<0x98, RawFrm, (outs), (ins),
+               "{cltq|cdqe}", [], IIC_CBW>, Sched<[WriteALU]>;
+
+  let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
+  def CQO  : RI<0x99, RawFrm, (outs), (ins),
+                "{cqto|cqo}", [], IIC_CBW>, Sched<[WriteALU]>;
+}
+
+// Sign/Zero extenders
+let hasSideEffects = 0 in {
+def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
                    "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
                    TB, OpSize16, Sched<[WriteALU]>;
 let mayLoad = 1 in