#include "ARMRegisterBankInfo.h"
#include "ARMInstrInfo.h" // For the register classes
+#include "ARMSubtarget.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
return InstructionMapping{};
}
+#ifndef NDEBUG
+ for (unsigned i = 0; i < NumOperands; i++) {
+ for (const auto &Mapping : OperandsMapping[i]) {
+ assert(
+ (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
+ MF.getSubtarget<ARMSubtarget>().hasVFP2()) &&
+ "Trying to use floating point register bank on target without vfp");
+ }
+ }
+#endif
+
return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,
NumOperands};
}
define void @test_add_s8() { ret void }
define void @test_add_s1() { ret void }
- define void @test_loads() { ret void }
+ define void @test_loads() #0 { ret void }
- define void @test_fadd_s32() { ret void }
- define void @test_fadd_s64() { ret void }
+ define void @test_fadd_s32() #0 { ret void }
+ define void @test_fadd_s64() #0 { ret void }
- define void @test_soft_fp_s64() { ret void }
+ define void @test_soft_fp_s64() #0 { ret void }
+
+ attributes #0 = { "target-features"="+vfp2"}
...
---
name: test_add_s32