]> granicus.if.org Git - llvm/commitdiff
[GISEL]: Move getConstantVReg to Utils
authorAditya Nandakumar <aditya_nandakumar@apple.com>
Wed, 19 Apr 2017 20:48:50 +0000 (20:48 +0000)
committerAditya Nandakumar <aditya_nandakumar@apple.com>
Wed, 19 Apr 2017 20:48:50 +0000 (20:48 +0000)
NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300751 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/GlobalISel/InstructionSelector.h
include/llvm/CodeGen/GlobalISel/Utils.h
lib/CodeGen/GlobalISel/InstructionSelector.cpp
lib/CodeGen/GlobalISel/Utils.cpp
lib/Target/AArch64/AArch64InstructionSelector.cpp

index d8096aeb215ada2ad247d1130abe98c301a0c2fe..911e8756070b2fc9da48d2f6db34a63e520aa660 100644 (file)
@@ -62,9 +62,6 @@ protected:
                                         const TargetRegisterInfo &TRI,
                                         const RegisterBankInfo &RBI) const;
 
-  Optional<int64_t> getConstantVRegVal(unsigned VReg,
-                                       const MachineRegisterInfo &MRI) const;
-
   bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
                          const MachineRegisterInfo &MRI) const;
 
index 52bf965a3cb3f953e4a27783ce388e59f208b083..92bc9736141a180af8de0fc4f9db1bbf6f826bc6 100644 (file)
@@ -60,5 +60,8 @@ void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
                         const char *PassName, StringRef Msg,
                         const MachineInstr &MI);
 
+Optional<int64_t> getConstantVRegVal(unsigned VReg,
+                                     const MachineRegisterInfo &MRI);
+
 } // End namespace llvm.
 #endif
index fb9d01ef8542a3efd4646914111ec0f88bec4b0f..942680b6fff3407dad38423546e9c4e7d0a693c8 100644 (file)
@@ -68,23 +68,6 @@ bool InstructionSelector::constrainSelectedInstRegOperands(
   return true;
 }
 
-Optional<int64_t>
-InstructionSelector::getConstantVRegVal(unsigned VReg,
-                                        const MachineRegisterInfo &MRI) const {
-  MachineInstr *MI = MRI.getVRegDef(VReg);
-  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
-    return None;
-
-  if (MI->getOperand(1).isImm())
-    return MI->getOperand(1).getImm();
-
-  if (MI->getOperand(1).isCImm() &&
-      MI->getOperand(1).getCImm()->getBitWidth() <= 64)
-    return MI->getOperand(1).getCImm()->getSExtValue();
-
-  return None;
-}
-
 bool InstructionSelector::isOperandImmEqual(
     const MachineOperand &MO, int64_t Value,
     const MachineRegisterInfo &MRI) const {
index 606a59680a3d4a618caedf55077da371be44df55..3c93f8123b0d14afb4a0bd5567c4f71c00adac11 100644 (file)
@@ -18,6 +18,7 @@
 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/Constants.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
@@ -93,3 +94,19 @@ void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
   R << Msg << ": " << ore::MNV("Inst", MI);
   reportGISelFailure(MF, TPC, MORE, R);
 }
+
+Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
+                                           const MachineRegisterInfo &MRI) {
+  MachineInstr *MI = MRI.getVRegDef(VReg);
+  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
+    return None;
+
+  if (MI->getOperand(1).isImm())
+    return MI->getOperand(1).getImm();
+
+  if (MI->getOperand(1).isCImm() &&
+      MI->getOperand(1).getCImm()->getBitWidth() <= 64)
+    return MI->getOperand(1).getCImm()->getSExtValue();
+
+  return None;
+}
index 878dac6bff1e31002e992421d5e8bee215c8a153..5e01b6cd2b46f68e2a268c6c853a59b4857043a3 100644 (file)
@@ -20,6 +20,7 @@
 #include "AArch64TargetMachine.h"
 #include "MCTargetDesc/AArch64AddressingModes.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"