[Mips][Codegen] Fix fast-isel mixing of FGR64 and AFGR64 registers

Fast-isel was picking AFGR64 register class for processing call
arguments when +fp64 options was used. We simply check is option +fp64
is used and pick appropriate register.

Patch by Mirko Brkusanin.

Differential Revision: https://reviews.llvm.org/D65886

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368433 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp
index 123d3cc242f0ba42b8c13ace04eae3d2477102b0..702c2b01358aa247fb0417c80d934e27a768b52f 100644 (file)
--- a/lib/Target/Mips/MipsFastISel.cpp
+++ b/lib/Target/Mips/MipsFastISel.cpp
@@ -1162,14 +1162,20 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
       if (ArgVT == MVT::f32) {
         VA.convertToReg(Mips::F12);
       } else if (ArgVT == MVT::f64) {
-        VA.convertToReg(Mips::D6);
+        if (Subtarget->isFP64bit())
+          VA.convertToReg(Mips::D6_64);
+        else
+          VA.convertToReg(Mips::D6);
       }
     } else if (i == 1) {
       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
         if (ArgVT == MVT::f32) {
           VA.convertToReg(Mips::F14);
         } else if (ArgVT == MVT::f64) {
-          VA.convertToReg(Mips::D7);
+          if (Subtarget->isFP64bit())
+            VA.convertToReg(Mips::D7_64);
+          else
+            VA.convertToReg(Mips::D7);
         }
       }
     }

diff --git a/test/CodeGen/Mips/copy-fp64.ll b/test/CodeGen/Mips/copy-fp64.ll
new file mode 100644 (file)
index 0000000..439c788
--- /dev/null
+++ b/test/CodeGen/Mips/copy-fp64.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+
+; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic -mattr=+fp64 \
+; RUN:   -stop-before=prologepilog %s -o - | FileCheck %s
+
+declare double @bar(double)
+
+define  double @foo(double %self) {
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0.start:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $d12_64, $t9, $v0
+  ; CHECK:   renamable $at = ADDu killed $v0, killed $t9
+  ; CHECK:   ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+  ; CHECK:   $d6_64 = COPY killed renamable $d12_64
+  ; CHECK:   renamable $t9 = LW killed renamable $at, target-flags(mips-got) @bar
+  ; CHECK:   dead $ra = JALR killed $t9, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, implicit-def dead $ra, implicit killed $d6_64, implicit-def $d0_64
+  ; CHECK:   ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+  ; CHECK:   SDC164 killed $d0_64, %stack.0, 0 :: (store 8 into %stack.0)
+  ; CHECK: bb.1.bb1:
+  ; CHECK:   $d0_64 = LDC164 %stack.0, 0 :: (load 8 from %stack.0)
+  ; CHECK:   RetRA implicit killed $d0_64
+start:
+  %0 = call double @bar(double %self)
+  br label %bb1
+
+bb1:
+  ret double %0
+}