Don't assume instruction names in the output.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@191957 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/aarch64-neon-shifts.c b/test/CodeGen/aarch64-neon-shifts.c
index 9b939e6f32b68dd181eed03b518b9b8824560504..4777f18aae7f37ccde7fc0f1c36c26b8ed9ae5f7 100644 (file)
--- a/test/CodeGen/aarch64-neon-shifts.c
+++ b/test/CodeGen/aarch64-neon-shifts.c
@@ -6,13 +6,13 @@
 
 uint8x8_t test_shift_vshr(uint8x8_t a) {
   // CHECK-LABEL: test_shift_vshr
-  // CHECK: %vshr_n = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  // CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
   return vshr_n_u8(a, 5);
 }
 
 int8x8_t test_shift_vshr_smax(int8x8_t a) {
   // CHECK-LABEL: test_shift_vshr_smax
-  // CHECK: %vshr_n = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  // CHECK: %{{.*}} = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   return vshr_n_s8(a, 8);
 }
 
@@ -24,15 +24,15 @@ uint8x8_t test_shift_vshr_umax(uint8x8_t a) {
 
 uint8x8_t test_shift_vsra(uint8x8_t a, uint8x8_t b) {
   // CHECK-LABEL: test_shift_vsra
-  // CHECK: %vsra_n = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
-  // CHECK: %0 = add <8 x i8> %vsra_n, %a
+  // CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  // CHECK: %{{.*}} = add <8 x i8> %[[SHR]], %a
   return vsra_n_u8(a, b, 5);
 }
 
 int8x8_t test_shift_vsra_smax(int8x8_t a, int8x8_t b) {
   // CHECK-LABEL: test_shift_vsra_smax
-  // CHECK: %vsra_n = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
-  // CHECK: %0 = add <8 x i8> %vsra_n, %a
+  // CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  // CHECK: %{{.*}} = add <8 x i8> %[[SHR]], %a
   return vsra_n_s8(a, b, 8);
 }
 

diff --git a/test/CodeGen/arm-neon-shifts.c b/test/CodeGen/arm-neon-shifts.c
index a89ddf5e5c884a5e977e104410dd932960cc42e5..7acfb894e97685084aeb3637f446ebf9098f4647 100644 (file)
--- a/test/CodeGen/arm-neon-shifts.c
+++ b/test/CodeGen/arm-neon-shifts.c
@@ -8,13 +8,13 @@
 
 uint8x8_t test_shift_vshr(uint8x8_t a) {
   // CHECK-LABEL: test_shift_vshr
-  // CHECK: %vshr_n = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  // CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
   return vshr_n_u8(a, 5);
 }
 
 int8x8_t test_shift_vshr_smax(int8x8_t a) {
   // CHECK-LABEL: test_shift_vshr_smax
-  // CHECK: %vshr_n = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  // CHECK: %{{.*}} = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   return vshr_n_s8(a, 8);
 }
 
@@ -26,15 +26,15 @@ uint8x8_t test_shift_vshr_umax(uint8x8_t a) {
 
 uint8x8_t test_shift_vsra(uint8x8_t a, uint8x8_t b) {
   // CHECK-LABEL: test_shift_vsra
-  // CHECK: %vsra_n = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
-  // CHECK: %0 = add <8 x i8> %vsra_n, %a
+  // CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
+  // CHECK: %{{.*}} = add <8 x i8> %[[SHR]], %a
   return vsra_n_u8(a, b, 5);
 }
 
 int8x8_t test_shift_vsra_smax(int8x8_t a, int8x8_t b) {
   // CHECK-LABEL: test_shift_vsra_smax
-  // CHECK: %vsra_n = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
-  // CHECK: %0 = add <8 x i8> %vsra_n, %a
+  // CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
+  // CHECK: %{{.*}} = add <8 x i8> %[[SHR]], %a
   return vsra_n_s8(a, b, 8);
 }