]> granicus.if.org Git - llvm/commitdiff
[AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences.
authorQuentin Colombet <qcolombet@apple.com>
Fri, 1 May 2015 20:57:11 +0000 (20:57 +0000)
committerQuentin Colombet <qcolombet@apple.com>
Fri, 1 May 2015 20:57:11 +0000 (20:57 +0000)
rdar://problem/20748715

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236346 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AArch64/AArch64FastISel.cpp
test/CodeGen/AArch64/arm64-fast-isel.ll

index 837a31f303fb08061091aef6d8c71b9fa111d556..c70b17c8a32c41e3af137c70a1e141f32a68fe3e 100644 (file)
@@ -3598,7 +3598,10 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
                     AArch64_AM::ASR, 31, /*WantResult=*/false);
       } else {
         assert(VT == MVT::i64 && "Unexpected value type.");
-        MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
+        // LHSReg and RHSReg cannot be killed by this Mul, since they are
+        // reused in the next instruction.
+        MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg,
+                            /*IsKill=*/false);
         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
                                         RHSReg, RHSIsKill);
         emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
@@ -3627,7 +3630,10 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
                                             AArch64::sub_32);
       } else {
         assert(VT == MVT::i64 && "Unexpected value type.");
-        MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
+        // LHSReg and RHSReg cannot be killed by this Mul, since they are
+        // reused in the next instruction.
+        MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg,
+                            /*IsKill=*/false);
         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
                                         RHSReg, RHSIsKill);
         emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
index a1d51a54cd466c520cb50d26577a77ac1c1a0259..6663c9ac577ed71a9043557bf6d2fd24929b1907 100644 (file)
@@ -101,3 +101,16 @@ entry:
   store i32 %cond91, i32* %addr, align 4
   ret void
 }
+
+define i64 @mul_umul(i64 %arg) {
+; CHECK-LABEL: mul_umul:
+; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
+; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
+entry:
+  %sub.ptr.div = sdiv exact i64 %arg, 8
+  %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
+  %tmp1 = extractvalue { i64, i1 } %tmp, 0
+  ret i64 %tmp1
+}
+
+declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)