case HexagonISD::INSERT: return "HexagonISD::INSERT";
case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
case HexagonISD::JT: return "HexagonISD::JT";
- case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
// S2_vtruneh
def: Pat<(v2i16 (trunc V2I32:$Rs)),
- (LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>;
+ (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
// --(4) Logical ---------------------------------------------------------
SDTCisSubVecOfVec<1, 0>]>;
def SDTHexagonVPACK: SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisVec<1>]>;
-def HexagonPACKHL: SDNode<"HexagonISD::PACKHL", SDTHexagonI64I32I32>;
def HexagonCOMBINE: SDNode<"HexagonISD::COMBINE", SDTHexagonI64I32I32>;
def HexagonVCOMBINE: SDNode<"HexagonISD::VCOMBINE", SDTHexagonVCOMBINE>;
def HexagonVPACKE: SDNode<"HexagonISD::VPACKE", SDTHexagonVPACK>;
def HexagonVPACKO: SDNode<"HexagonISD::VPACKO", SDTHexagonVPACK>;
-def: OpR_RR_pat<S2_packhl, pf2<HexagonPACKHL>, i64, I32>;
-
def: Pat<(HexagonCOMBINE I32:$Rs, I32:$Rt), (Combinew $Rs, $Rt)>;
// The complexity of the combines involving immediates should be greater
; Extracted from test/CodeGen/Generic/vector-casts.ll: used to loop indefinitely.
; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: packhl
+; CHECK: combine
define void @a(<2 x double>* %p, <2 x i8>* %q) {
%t = load <2 x double>, <2 x double>* %p