Although all the registers are actually 32-bits, I think we have to assume the
high 32-bits could be RES0 (the ARM ARM is unclear). If so, reading as a 32-bit
register can require extra zero extension operations.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@266212
91177308-0d34-0410-b5e6-
96231b3b80d8
if (BuiltinID == AArch64::BI__builtin_arm_rsr64 ||
BuiltinID == AArch64::BI__builtin_arm_wsr64)
- return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, false);
+ return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true);
if (BuiltinID == AArch64::BI__builtin_arm_rsr ||
BuiltinID == AArch64::BI__builtin_arm_rsrp ||
}
void wsr64_1(unsigned long v) {
- __builtin_arm_wsr64("sysreg", v); //expected-error {{invalid special register for builtin}}
+ __builtin_arm_wsr64("sysreg", v);
}
unsigned rsr_1() {
}
unsigned long rsr64_1() {
- return __builtin_arm_rsr64("sysreg"); //expected-error {{invalid special register for builtin}}
+ return __builtin_arm_rsr64("sysreg");
}
void wsr_2(unsigned v) {