[DAGCombine] (A+C1)-C2 -> A+(C1-C2) constant-fold

Summary:
Direct sibling of D62662, the root cause of the endless combine loop in D62257

https://rise4fun.com/Alive/d3W

Reviewers: RKSimon, craig.topper, spatel, t.p.northover

Reviewed By: t.p.northover

Subscribers: t.p.northover, javed.absar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62664

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362133 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index c04dbd276cfe7c821051a36f8138528f54a808ce..da205841a2208b881752c750eca3828bbcbab05f 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2863,6 +2863,16 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
   if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
     return N0.getOperand(0);
 
+  // fold (A+C1)-C2 -> A+(C1-C2)
+  if (N0.getOpcode() == ISD::ADD &&
+      isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
+      isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
+    SDValue NewC = DAG.FoldConstantArithmetic(
+        ISD::SUB, DL, VT, N0.getOperand(1).getNode(), N1.getNode());
+    assert(NewC && "Constant folding failed");
+    return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
+  }
+
   // fold C2-(A+C1) -> (C2-C1)-A
   if (N1.getOpcode() == ISD::ADD) {
     SDValue N11 = N1.getOperand(1);

diff --git a/test/CodeGen/AArch64/addsub-constant-folding.ll b/test/CodeGen/AArch64/addsub-constant-folding.ll
index a1bf779e1dbfd2ae49e9671be763e0c64482854a..8afa4ded1e04e75ff0b381f147777eb76d7ae5c7 100644 (file)
--- a/test/CodeGen/AArch64/addsub-constant-folding.ll
+++ b/test/CodeGen/AArch64/addsub-constant-folding.ll
@@ -56,10 +56,8 @@ define <4 x i32> @add_const_add_const_nonsplat(<4 x i32> %arg) {
 define <4 x i32> @add_const_sub_const(<4 x i32> %arg) {
 ; CHECK-LABEL: add_const_sub_const:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    movi v1.4s, #8
+; CHECK-NEXT:    movi v1.4s, #6
 ; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    movi v1.4s, #2
-; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
   %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
   %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
@@ -74,13 +72,13 @@ define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) {
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    .cfi_offset w30, -16
 ; CHECK-NEXT:    movi v1.4s, #8
-; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
+; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    bl use
 ; CHECK-NEXT:    ldr q1, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT:    movi v0.4s, #2
-; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    movi v0.4s, #6
+; CHECK-NEXT:    add v0.4s, v1.4s, v0.4s
 ; CHECK-NEXT:    add sp, sp, #32 // =32
 ; CHECK-NEXT:    ret
   %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
@@ -94,10 +92,7 @@ define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI5_0
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
-; CHECK-NEXT:    adrp x8, .LCPI5_1
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_1]
 ; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    sub v0.4s, v0.4s, v2.4s
 ; CHECK-NEXT:    ret
   %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
   %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>

diff --git a/test/CodeGen/X86/addsub-constant-folding.ll b/test/CodeGen/X86/addsub-constant-folding.ll
index c3cbe5ed4b43e038ac5175458f906bde7c159b1d..0053bc2b611d357be1732929012efcbaff35d96f 100644 (file)
--- a/test/CodeGen/X86/addsub-constant-folding.ll
+++ b/test/CodeGen/X86/addsub-constant-folding.ll
@@ -78,13 +78,11 @@ define <4 x i32> @add_const_sub_const(<4 x i32> %arg) {
 ; X86-LABEL: add_const_sub_const:
 ; X86:       # %bb.0:
 ; X86-NEXT:    paddd {{\.LCPI.*}}, %xmm0
-; X86-NEXT:    psubd {{\.LCPI.*}}, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: add_const_sub_const:
 ; X64:       # %bb.0:
 ; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
-; X64-NEXT:    psubd {{.*}}(%rip), %xmm0
 ; X64-NEXT:    retq
   %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
   %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
@@ -96,11 +94,13 @@ define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) {
 ; X86:       # %bb.0:
 ; X86-NEXT:    subl $28, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 32
-; X86-NEXT:    paddd {{\.LCPI.*}}, %xmm0
+; X86-NEXT:    movdqa %xmm0, %xmm1
 ; X86-NEXT:    movdqu %xmm0, (%esp) # 16-byte Spill
+; X86-NEXT:    movdqa {{.*#+}} xmm0 = [8,8,8,8]
+; X86-NEXT:    paddd %xmm1, %xmm0
 ; X86-NEXT:    calll use
 ; X86-NEXT:    movdqu (%esp), %xmm0 # 16-byte Reload
-; X86-NEXT:    psubd {{\.LCPI.*}}, %xmm0
+; X86-NEXT:    paddd {{\.LCPI.*}}, %xmm0
 ; X86-NEXT:    addl $28, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
@@ -109,11 +109,13 @@ define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) {
 ; X64:       # %bb.0:
 ; X64-NEXT:    subq $24, %rsp
 ; X64-NEXT:    .cfi_def_cfa_offset 32
-; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
+; X64-NEXT:    movdqa %xmm0, %xmm1
 ; X64-NEXT:    movdqa %xmm0, (%rsp) # 16-byte Spill
+; X64-NEXT:    movdqa {{.*#+}} xmm0 = [8,8,8,8]
+; X64-NEXT:    paddd %xmm1, %xmm0
 ; X64-NEXT:    callq use
 ; X64-NEXT:    movdqa (%rsp), %xmm0 # 16-byte Reload
-; X64-NEXT:    psubd {{.*}}(%rip), %xmm0
+; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
 ; X64-NEXT:    addq $24, %rsp
 ; X64-NEXT:    .cfi_def_cfa_offset 8
 ; X64-NEXT:    retq
@@ -127,13 +129,11 @@ define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) {
 ; X86-LABEL: add_const_sub_const_nonsplat:
 ; X86:       # %bb.0:
 ; X86-NEXT:    paddd {{\.LCPI.*}}, %xmm0
-; X86-NEXT:    psubd {{\.LCPI.*}}, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: add_const_sub_const_nonsplat:
 ; X64:       # %bb.0:
 ; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
-; X64-NEXT:    psubd {{.*}}(%rip), %xmm0
 ; X64-NEXT:    retq
   %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
   %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>