Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
#include "soc/io_mux_reg.h"
#include "soc/efuse_reg.h"
#include "soc/rtc_cntl_reg.h"
-#include "soc/timers_reg.h"
+#include "soc/timer_group_reg.h"
#include "sdkconfig.h"
Cache_Flush(0);
Cache_Flush(1);
mmu_init(0);
- REG_SET_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
+ REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
mmu_init(1);
- REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
+ REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
/* (above steps probably unnecessary for most serial bootloader
usage, all that's absolutely needed is that we unmask DROM0
cache on the following two lines - normal ROM boot exits with
The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
necessary to work around a hardware bug.
*/
- REG_CLR_BIT(PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
- REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
+ REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
+ REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
bootloader_main();
}
log_notice( "compile time %s\n", __TIME__ );
/* close watch dog here */
- REG_CLR_BIT( RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
- REG_CLR_BIT( WDTCONFIG0(0), TIMERS_WDT_FLASHBOOT_MOD_EN );
+ REG_CLR_BIT( RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
+ REG_CLR_BIT( TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN );
SPIUnlock();
/*register first sector in drom0 page 0 */
boot_cache_redirect( 0, 0x5000 );
log_debug( "rc=%d", rc );
rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
log_debug( "rc=%d", rc );
- REG_CLR_BIT( PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
- REG_CLR_BIT( APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
+ REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
+ REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
Cache_Read_Enable( 0 );
Cache_Read_Enable( 1 );
bool flash_encrypt(bootloader_state_t *bs)
{
uint32_t bin_len = 0;
- uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0, EFUSE_FLASH_CRYPT_CNT);
+ uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_FLASH_CRYPT_CNT);
uint8_t count = bitcount(flash_crypt_cnt);
int i = 0;
log_debug("flash crypt cnt %x, count %d\n", flash_crypt_cnt, count);
log_error("encrypt ota binfo error");
return false;
}
- REG_SET_FIELD(EFUSE_BLK0_WDATA0, EFUSE_FLASH_CRYPT_CNT, 0x04);
- REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
- REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */
- while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */
+ REG_SET_FIELD(EFUSE_BLK0_WDATA0_REG, EFUSE_FLASH_CRYPT_CNT, 0x04);
+ REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
+ REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */
+ while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */
log_warn("burn flash_crypt_cnt\n");
- REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */
- REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */
- while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */
+ REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */
+ REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */
+ while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */
return true;
} else {
log_info("flash already encrypted.\n");
*/
bool secure_boot(void){
uint32_t bin_len = 0;
- if (REG_READ(EFUSE_BLK0_RDATA6) & EFUSE_RD_ABS_DONE_0)
+ if (REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_RD_ABS_DONE_0)
{
log_info("already secure boot !\n");
return true;
}
}
- REG_SET_BIT(EFUSE_BLK0_WDATA6, EFUSE_RD_ABS_DONE_0);
- REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
- REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */
- while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */
+ REG_SET_BIT(EFUSE_BLK0_WDATA6_REG, EFUSE_RD_ABS_DONE_0);
+ REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
+ REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */
+ while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */
log_warn("burn abstract_done_0\n");
- REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */
- REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */
- while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */
- log_debug("read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6));
+ REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */
+ REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */
+ while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */
+ log_debug("read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6_REG));
return true;
}
#ifndef CONFIG_FREERTOS_UNICORE
ets_printf("Starting app cpu, entry point is %p\n", call_user_start_cpu1);
- SET_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
- CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL);
- SET_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
- CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
+ SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
+ CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
+ SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
+ CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1);
while (!app_cpu_started) {
ets_delay_us(100);
}
#else
- CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
+ CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
#endif
ets_printf("Pro cpu start user code\n");
user_start_cpu0();
#include "esp_attr.h"
-#include "soc/spi_register.h"
+#include "soc/spi_reg.h"
#ifdef __cplusplus
extern "C" {
#include "soc.h"
-#define PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000)
-#define DPORT_PRO_BOOT_REMAP (BIT(0))
-#define DPORT_PRO_BOOT_REMAP_S 0
-
-#define APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004)
-#define DPORT_APP_BOOT_REMAP (BIT(0))
-#define DPORT_APP_BOOT_REMAP_S 0
-
-#define DPORT_ACCESS_CHECK (DR_REG_DPORT_BASE + 0x008)
-#define DPORT_DPORT_ACCESS_CHECK_APP (BIT(8))
-#define DPORT_DPORT_ACCESS_CHECK_APP_S 8
-#define DPORT_DPORT_ACCESS_CHECK_PRO (BIT(0))
-#define DPORT_DPORT_ACCESS_CHECK_PRO_S 0
-
-#define PRO_DPORT_APB_MASK0 (DR_REG_DPORT_BASE + 0x00C)
-#define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF
-#define DPORT_PRODPORT_APB_MASK0_S 0
-
-#define PRO_DPORT_APB_MASK1 (DR_REG_DPORT_BASE + 0x010)
-#define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF
-#define DPORT_PRODPORT_APB_MASK1_S 0
-
-#define APP_DPORT_APB_MASK0 (DR_REG_DPORT_BASE + 0x014)
-#define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF
-#define DPORT_APPDPORT_APB_MASK0_S 0
-
-#define APP_DPORT_APB_MASK1 (DR_REG_DPORT_BASE + 0x018)
-#define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF
-#define DPORT_APPDPORT_APB_MASK1_S 0
-
-#define PERI_CLK_EN (DR_REG_DPORT_BASE + 0x01C)
-#define DPORT_PERI_CLK_EN 0xFFFFFFFF
-#define DPORT_PERI_CLK_EN_S 0
-
-#define PERI_RST_EN (DR_REG_DPORT_BASE + 0x020)
-#define DPORT_PERI_RST_EN 0xFFFFFFFF
-#define DPORT_PERI_RST_EN_S 0
-
-#define WIFI_BB_CFG (DR_REG_DPORT_BASE + 0x024)
-#define DPORT_WIFI_BB_CFG 0xFFFFFFFF
-#define DPORT_WIFI_BB_CFG_S 0
-
-#define WIFI_BB_CFG_2 (DR_REG_DPORT_BASE + 0x028)
-#define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF
-#define DPORT_WIFI_BB_CFG_2_S 0
-
-#define APPCPU_CTRL_REG_A (DR_REG_DPORT_BASE + 0x02C)
-#define DPORT_APPCPU_RESETTING (BIT(0))
-#define DPORT_APPCPU_RESETTING_S 0
-
-#define APPCPU_CTRL_REG_B (DR_REG_DPORT_BASE + 0x030)
-#define DPORT_APPCPU_CLKGATE_EN (BIT(0))
-#define DPORT_APPCPU_CLKGATE_EN_S 0
-
-#define APPCPU_CTRL_REG_C (DR_REG_DPORT_BASE + 0x034)
-#define DPORT_APPCPU_RUNSTALL (BIT(0))
-#define DPORT_APPCPU_RUNSTALL_S 0
-
-#define APPCPU_CTRL_REG_D (DR_REG_DPORT_BASE + 0x038)
-#define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF
-#define DPORT_APPCPU_BOOT_ADDR_S 0
-
-#define CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C)
-#define DPORT_FAST_CLK_RTC_SEL (BIT(3))
-#define DPORT_FAST_CLK_RTC_SEL_S 3
-#define DPORT_LOWSPEED_CLK_SEL (BIT(2))
-#define DPORT_LOWSPEED_CLK_SEL_S 2
-#define DPORT_CPUPERIOD_SEL 0x00000003
-#define DPORT_CPUPERIOD_SEL_S 0
-
-#define PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040)
-#define DPORT_PRO_DRAM_HL (BIT(16))
-#define DPORT_PRO_DRAM_HL_S 16
-#define DPORT_SLAVE_REQ (BIT(15))
-#define DPORT_SLAVE_REQ_S 15
-#define DPORT_AHB_SPI_REQ (BIT(14))
-#define DPORT_AHB_SPI_REQ_S 14
-#define DPORT_PRO_SLAVE_REQ (BIT(13))
-#define DPORT_PRO_SLAVE_REQ_S 13
-#define DPORT_PRO_AHB_SPI_REQ (BIT(12))
-#define DPORT_PRO_AHB_SPI_REQ_S 12
-#define DPORT_PRO_DRAM_SPLIT (BIT(11))
-#define DPORT_PRO_DRAM_SPLIT_S 11
-#define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10))
-#define DPORT_PRO_SINGLE_IRAM_ENA_S 10
-#define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9))
-#define DPORT_PRO_CACHE_LOCK_3_EN_S 9
-#define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8))
-#define DPORT_PRO_CACHE_LOCK_2_EN_S 8
-#define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7))
-#define DPORT_PRO_CACHE_LOCK_1_EN_S 7
-#define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6))
-#define DPORT_PRO_CACHE_LOCK_0_EN_S 6
-#define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5))
-#define DPORT_PRO_CACHE_FLUSH_DONE_S 5
-#define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4))
-#define DPORT_PRO_CACHE_FLUSH_ENA_S 4
-#define DPORT_PRO_CACHE_ENABLE (BIT(3))
-#define DPORT_PRO_CACHE_ENABLE_S 3
-#define DPORT_PRO_CACHE_MODE (BIT(2))
-#define DPORT_PRO_CACHE_MODE_S 2
-
-#define PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044)
-#define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13))
-#define DPORT_PRO_CACHE_MMU_IA_CLR_S 13
-#define DPORT_PRO_CMMU_PD (BIT(12))
-#define DPORT_PRO_CMMU_PD_S 12
-#define DPORT_PRO_CMMU_FORCE_ON (BIT(11))
-#define DPORT_PRO_CMMU_FORCE_ON_S 11
-#define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003
-#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9
-#define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007
-#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6
-#define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5))
-#define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5
-#define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4))
-#define DPORT_PRO_CACHE_MASK_DROM0_S 4
-#define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3))
-#define DPORT_PRO_CACHE_MASK_DRAM1_S 3
-#define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2))
-#define DPORT_PRO_CACHE_MASK_IROM0_S 2
-#define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1))
-#define DPORT_PRO_CACHE_MASK_IRAM1_S 1
-#define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0))
-#define DPORT_PRO_CACHE_MASK_IRAM0_S 0
-
-#define PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048)
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0
-
-#define PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C)
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0
-
-#define PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050)
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0
-
-#define PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054)
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0
-
-#define APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058)
-#define DPORT_APP_DRAM_HL (BIT(14))
-#define DPORT_APP_DRAM_HL_S 14
-#define DPORT_APP_SLAVE_REQ (BIT(13))
-#define DPORT_APP_SLAVE_REQ_S 13
-#define DPORT_APP_AHB_SPI_REQ (BIT(12))
-#define DPORT_APP_AHB_SPI_REQ_S 12
-#define DPORT_APP_DRAM_SPLIT (BIT(11))
-#define DPORT_APP_DRAM_SPLIT_S 11
-#define DPORT_APP_SINGLE_IRAM_ENA (BIT(10))
-#define DPORT_APP_SINGLE_IRAM_ENA_S 10
-#define DPORT_APP_CACHE_LOCK_3_EN (BIT(9))
-#define DPORT_APP_CACHE_LOCK_3_EN_S 9
-#define DPORT_APP_CACHE_LOCK_2_EN (BIT(8))
-#define DPORT_APP_CACHE_LOCK_2_EN_S 8
-#define DPORT_APP_CACHE_LOCK_1_EN (BIT(7))
-#define DPORT_APP_CACHE_LOCK_1_EN_S 7
-#define DPORT_APP_CACHE_LOCK_0_EN (BIT(6))
-#define DPORT_APP_CACHE_LOCK_0_EN_S 6
-#define DPORT_APP_CACHE_FLUSH_DONE (BIT(5))
-#define DPORT_APP_CACHE_FLUSH_DONE_S 5
-#define DPORT_APP_CACHE_FLUSH_ENA (BIT(4))
-#define DPORT_APP_CACHE_FLUSH_ENA_S 4
-#define DPORT_APP_CACHE_ENABLE (BIT(3))
-#define DPORT_APP_CACHE_ENABLE_S 3
-#define DPORT_APP_CACHE_MODE (BIT(2))
-#define DPORT_APP_CACHE_MODE_S 2
-
-#define APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C)
-#define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13))
-#define DPORT_APP_CACHE_MMU_IA_CLR_S 13
-#define DPORT_APP_CMMU_PD (BIT(12))
-#define DPORT_APP_CMMU_PD_S 12
-#define DPORT_APP_CMMU_FORCE_ON (BIT(11))
-#define DPORT_APP_CMMU_FORCE_ON_S 11
-#define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003
-#define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9
-#define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007
-#define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6
-#define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5))
-#define DPORT_APP_CACHE_MASK_OPSDRAM_S 5
-#define DPORT_APP_CACHE_MASK_DROM0 (BIT(4))
-#define DPORT_APP_CACHE_MASK_DROM0_S 4
-#define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3))
-#define DPORT_APP_CACHE_MASK_DRAM1_S 3
-#define DPORT_APP_CACHE_MASK_IROM0 (BIT(2))
-#define DPORT_APP_CACHE_MASK_IROM0_S 2
-#define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1))
-#define DPORT_APP_CACHE_MASK_IRAM1_S 1
-#define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0))
-#define DPORT_APP_CACHE_MASK_IRAM0_S 0
-
-#define APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060)
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14
-#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF
-#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0
-
-#define APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064)
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14
-#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF
-#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0
-
-#define APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068)
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14
-#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF
-#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0
-
-#define APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C)
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14
-#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF
-#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0
-
-#define TRACEMEM_MUX_MODE (DR_REG_DPORT_BASE + 0x070)
-#define DPORT_TRACEMEM_MUX_MODE 0x00000003
-#define DPORT_TRACEMEM_MUX_MODE_S 0
-
-#define PRO_TRACEMEM_ENA (DR_REG_DPORT_BASE + 0x074)
-#define DPORT_PRO_TRACEMEM_ENA (BIT(0))
-#define DPORT_PRO_TRACEMEM_ENA_S 0
-
-#define APP_TRACEMEM_ENA (DR_REG_DPORT_BASE + 0x078)
-#define DPORT_APP_TRACEMEM_ENA (BIT(0))
-#define DPORT_APP_TRACEMEM_ENA_S 0
-
-#define CACHE_MUX_MODE (DR_REG_DPORT_BASE + 0x07C)
-#define DPORT_CACHE_MUX_MODE 0x00000003
-#define DPORT_CACHE_MUX_MODE_S 0
-
-#define IMMU_PAGE_MODE (DR_REG_DPORT_BASE + 0x080)
-#define DPORT_IMMU_PAGE_MODE 0x00000003
-#define DPORT_IMMU_PAGE_MODE_S 1
-#define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0))
-#define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0
-
-#define DMMU_PAGE_MODE (DR_REG_DPORT_BASE + 0x084)
-#define DPORT_DMMU_PAGE_MODE 0x00000003
-#define DPORT_DMMU_PAGE_MODE_S 1
-#define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0))
-#define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0
-
-#define ROM_MPU_ENA (DR_REG_DPORT_BASE + 0x088)
-#define DPORT_APP_ROM_MPU_ENA (BIT(2))
-#define DPORT_APP_ROM_MPU_ENA_S 2
-#define DPORT_PRO_ROM_MPU_ENA (BIT(1))
-#define DPORT_PRO_ROM_MPU_ENA_S 1
-#define DPORT_SHARE_ROM_MPU_ENA (BIT(0))
-#define DPORT_SHARE_ROM_MPU_ENA_S 0
-
-#define MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C)
-#define DPORT_LSLP_MEM_PD_MASK (BIT(0))
-#define DPORT_LSLP_MEM_PD_MASK_S 0
-
-#define ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090)
-#define DPORT_SHARE_ROM_PD 0x0000003F
-#define DPORT_SHARE_ROM_PD_S 2
-#define DPORT_APP_ROM_PD (BIT(1))
-#define DPORT_APP_ROM_PD_S 1
-#define DPORT_PRO_ROM_PD (BIT(0))
-#define DPORT_PRO_ROM_PD_S 0
-
-#define ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094)
-#define DPORT_SHARE_ROM_FO 0x0000003F
-#define DPORT_SHARE_ROM_FO_S 2
-#define DPORT_APP_ROM_FO (BIT(1))
-#define DPORT_APP_ROM_FO_S 1
-#define DPORT_PRO_ROM_FO (BIT(0))
-#define DPORT_PRO_ROM_FO_S 0
-
-#define SRAM_PD_CTRL_REG_0 (DR_REG_DPORT_BASE + 0x098)
-#define DPORT_SRAM_PD_0 0xFFFFFFFF
-#define DPORT_SRAM_PD_0_S 0
-
-#define SRAM_PD_CTRL_REG_1 (DR_REG_DPORT_BASE + 0x09C)
-#define DPORT_SRAM_PD_1 (BIT(0))
-#define DPORT_SRAM_PD_1_S 0
-
-#define SRAM_FO_CTRL_REG_0 (DR_REG_DPORT_BASE + 0x0A0)
-#define DPORT_SRAM_FO_0 0xFFFFFFFF
-#define DPORT_SRAM_FO_0_S 0
-
-#define SRAM_FO_CTRL_REG_1 (DR_REG_DPORT_BASE + 0x0A4)
-#define DPORT_SRAM_FO_1 (BIT(0))
-#define DPORT_SRAM_FO_1_S 0
-
-#define IRAM_DRAM_AHB_SEL (DR_REG_DPORT_BASE + 0x0A8)
-#define DPORT_MAC_DUMP_MODE 0x00000003
-#define DPORT_MAC_DUMP_MODE_S 5
-#define DPORT_MASK_AHB (BIT(4))
-#define DPORT_MASK_AHB_S 4
-#define DPORT_MASK_APP_DRAM (BIT(3))
-#define DPORT_MASK_APP_DRAM_S 3
-#define DPORT_MASK_PRO_DRAM (BIT(2))
-#define DPORT_MASK_PRO_DRAM_S 2
-#define DPORT_MASK_APP_IRAM (BIT(1))
-#define DPORT_MASK_APP_IRAM_S 1
-#define DPORT_MASK_PRO_IRAM (BIT(0))
-#define DPORT_MASK_PRO_IRAM_S 0
-
-#define TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC)
-#define DPORT_APP_CACHE_TAG_PD (BIT(9))
-#define DPORT_APP_CACHE_TAG_PD_S 9
-#define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8))
-#define DPORT_APP_CACHE_TAG_FORCE_ON_S 8
-#define DPORT_PRO_CACHE_TAG_PD (BIT(1))
-#define DPORT_PRO_CACHE_TAG_PD_S 1
-#define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0))
-#define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0
-
-#define AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0)
-#define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007
-#define DPORT_AHB_LITE_SDHOST_PID_REG_S 11
-#define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10))
-#define DPORT_AHB_LITE_MASK_APPDPORT_S 10
-#define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9))
-#define DPORT_AHB_LITE_MASK_PRODPORT_S 9
-#define DPORT_AHB_LITE_MASK_SDIO (BIT(8))
-#define DPORT_AHB_LITE_MASK_SDIO_S 8
-#define DPORT_AHB_LITE_MASK_APP (BIT(4))
-#define DPORT_AHB_LITE_MASK_APP_S 4
-#define DPORT_AHB_LITE_MASK_PRO (BIT(0))
-#define DPORT_AHB_LITE_MASK_PRO_S 0
-
-#define AHB_MPU_TABLE_0 (DR_REG_DPORT_BASE + 0x0B4)
-#define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF
-#define DPORT_AHB_ACCESS_GRANT_0_S 0
-
-#define AHB_MPU_TABLE_1 (DR_REG_DPORT_BASE + 0x0B8)
-#define DPORT_AHB_ACCESS_GRANT_1 0x000001FF
-#define DPORT_AHB_ACCESS_GRANT_1_S 0
-
-#define HOST_INF_SEL (DR_REG_DPORT_BASE + 0x0BC)
-#define DPORT_LINK_DEVICE_SEL 0x000000FF
-#define DPORT_LINK_DEVICE_SEL_S 8
-#define DPORT_PERI_IO_SWAP 0x000000FF
-#define DPORT_PERI_IO_SWAP_S 0
-
-#define PERIP_CLK_EN (DR_REG_DPORT_BASE + 0x0C0)
-#define DPORT_PERIP_CLK_EN 0xFFFFFFFF
-#define DPORT_PERIP_CLK_EN_S 0
-
-#define PERIP_RST_EN (DR_REG_DPORT_BASE + 0x0C4)
-#define DPORT_PERIP_RST 0xFFFFFFFF
-#define DPORT_PERIP_RST_S 0
-
-#define SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8)
-#define DPORT_SPI_DECRYPT_ENABLE (BIT(12))
-#define DPORT_SPI_DECRYPT_ENABLE_S 12
-#define DPORT_SPI_ENCRYPT_ENABLE (BIT(8))
-#define DPORT_SPI_ENCRYPT_ENABLE_S 8
-#define DPORT_SLAVE_SPI_MASK_APP (BIT(4))
-#define DPORT_SLAVE_SPI_MASK_APP_S 4
-#define DPORT_SLAVE_SPI_MASK_PRO (BIT(0))
-#define DPORT_SLAVE_SPI_MASK_PRO_S 0
-
-#define WIFI_CLK_EN (DR_REG_DPORT_BASE + 0x0CC)
-#define DPORT_WIFI_CLK_EN 0xFFFFFFFF
-#define DPORT_WIFI_CLK_EN_S 0
-
-#define WIFI_RST_EN (DR_REG_DPORT_BASE + 0x0D0)
-#define DPORT_SDIO_RST (BIT(5))
-#define DPORT_MAC_RST (BIT(2))
-#define DPORT_WIFI_RST 0xFFFFFFFF
-#define DPORT_WIFI_RST_S 0
-
-#define BT_LPCK_DIV_INT (DR_REG_DPORT_BASE + 0x0D4)
-#define DPORT_BTEXTWAKEUP_REQ (BIT(12))
-#define DPORT_BTEXTWAKEUP_REQ_S 12
-#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF
-#define DPORT_BT_LPCK_DIV_NUM_S 0
-
-#define BT_LPCK_DIV_FRAC (DR_REG_DPORT_BASE + 0x0D8)
-#define DPORT_LPCLK_SEL_XTAL32K (BIT(27))
-#define DPORT_LPCLK_SEL_XTAL32K_S 27
-#define DPORT_LPCLK_SEL_XTAL (BIT(26))
-#define DPORT_LPCLK_SEL_XTAL_S 26
-#define DPORT_LPCLK_SEL_8M (BIT(25))
-#define DPORT_LPCLK_SEL_8M_S 25
-#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24))
-#define DPORT_LPCLK_SEL_RTC_SLOW_S 24
-#define DPORT_BT_LPCK_DIV_A 0x00000FFF
-#define DPORT_BT_LPCK_DIV_A_S 12
-#define DPORT_BT_LPCK_DIV_B 0x00000FFF
-#define DPORT_BT_LPCK_DIV_B_S 0
-
-#define CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC)
-#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_0_S 0
-
-#define CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0)
-#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_1_S 0
-
-#define CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4)
-#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_2_S 0
-
-#define CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8)
-#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_3_S 0
-
-#define PRO_INTR_STATUS_REG_0 (DR_REG_DPORT_BASE + 0x0EC)
-#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_0_S 0
-
-#define PRO_INTR_STATUS_REG_1 (DR_REG_DPORT_BASE + 0x0F0)
-#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_1_S 0
-
-#define PRO_INTR_STATUS_REG_2 (DR_REG_DPORT_BASE + 0x0F4)
-#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_2_S 0
-
-#define APP_INTR_STATUS_REG_0 (DR_REG_DPORT_BASE + 0x0F8)
-#define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_0_S 0
-
-#define APP_INTR_STATUS_REG_1 (DR_REG_DPORT_BASE + 0x0FC)
-#define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_1_S 0
-
-#define APP_INTR_STATUS_REG_2 (DR_REG_DPORT_BASE + 0x100)
-#define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_2_S 0
-
-#define PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104)
-#define DPORT_PRO_MAC_INTR_MAP 0x0000001F
-#define DPORT_PRO_MAC_INTR_MAP_S 0
-
-#define PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108)
-#define DPORT_PRO_MAC_NMI_MAP 0x0000001F
-#define DPORT_PRO_MAC_NMI_MAP_S 0
-
-#define PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C)
-#define DPORT_PRO_BB_INT_MAP 0x0000001F
-#define DPORT_PRO_BB_INT_MAP_S 0
-
-#define PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110)
-#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F
-#define DPORT_PRO_BT_MAC_INT_MAP_S 0
-
-#define PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114)
-#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F
-#define DPORT_PRO_BT_BB_INT_MAP_S 0
-
-#define PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118)
-#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F
-#define DPORT_PRO_BT_BB_NMI_MAP_S 0
-
-#define PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C)
-#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F
-#define DPORT_PRO_RWBT_IRQ_MAP_S 0
-
-#define PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120)
-#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F
-#define DPORT_PRO_RWBLE_IRQ_MAP_S 0
-
-#define PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124)
-#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F
-#define DPORT_PRO_RWBT_NMI_MAP_S 0
-
-#define PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128)
-#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F
-#define DPORT_PRO_RWBLE_NMI_MAP_S 0
-
-#define PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C)
-#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F
-#define DPORT_PRO_SLC0_INTR_MAP_S 0
-
-#define PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130)
-#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F
-#define DPORT_PRO_SLC1_INTR_MAP_S 0
-
-#define PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134)
-#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F
-#define DPORT_PRO_UHCI0_INTR_MAP_S 0
-
-#define PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138)
-#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F
-#define DPORT_PRO_UHCI1_INTR_MAP_S 0
-
-#define PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C)
-#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F
-#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0
-
-#define PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140)
-#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F
-#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0
-
-#define PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144)
-#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F
-#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0
-
-#define PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148)
-#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F
-#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0
-
-#define PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C)
-#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F
-#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0
-
-#define PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150)
-#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F
-#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0
-
-#define PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154)
-#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F
-#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0
-
-#define PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158)
-#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F
-#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0
-
-#define PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C)
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0
-
-#define PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160)
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
-
-#define PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164)
-#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0
-
-#define PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168)
-#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0
-
-#define PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C)
-#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0
-
-#define PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170)
-#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0
-
-#define PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174)
-#define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F
-#define DPORT_PRO_SPI_INTR_0_MAP_S 0
-
-#define PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178)
-#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F
-#define DPORT_PRO_SPI_INTR_1_MAP_S 0
-
-#define PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C)
-#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F
-#define DPORT_PRO_SPI_INTR_2_MAP_S 0
-
-#define PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180)
-#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F
-#define DPORT_PRO_SPI_INTR_3_MAP_S 0
-
-#define PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184)
-#define DPORT_PRO_I2S0_INT_MAP 0x0000001F
-#define DPORT_PRO_I2S0_INT_MAP_S 0
-
-#define PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188)
-#define DPORT_PRO_I2S1_INT_MAP 0x0000001F
-#define DPORT_PRO_I2S1_INT_MAP_S 0
-
-#define PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C)
-#define DPORT_PRO_UART_INTR_MAP 0x0000001F
-#define DPORT_PRO_UART_INTR_MAP_S 0
-
-#define PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190)
-#define DPORT_PRO_UART1_INTR_MAP 0x0000001F
-#define DPORT_PRO_UART1_INTR_MAP_S 0
-
-#define PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194)
-#define DPORT_PRO_UART2_INTR_MAP 0x0000001F
-#define DPORT_PRO_UART2_INTR_MAP_S 0
-
-#define PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198)
-#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F
-#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0
-
-#define PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C)
-#define DPORT_PRO_EMAC_INT_MAP 0x0000001F
-#define DPORT_PRO_EMAC_INT_MAP_S 0
-
-#define PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0)
-#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F
-#define DPORT_PRO_PWM0_INTR_MAP_S 0
-
-#define PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4)
-#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F
-#define DPORT_PRO_PWM1_INTR_MAP_S 0
-
-#define PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8)
-#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F
-#define DPORT_PRO_PWM2_INTR_MAP_S 0
-
-#define PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC)
-#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F
-#define DPORT_PRO_PWM3_INTR_MAP_S 0
-
-#define PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0)
-#define DPORT_PRO_LEDC_INT_MAP 0x0000001F
-#define DPORT_PRO_LEDC_INT_MAP_S 0
-
-#define PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4)
-#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F
-#define DPORT_PRO_EFUSE_INT_MAP_S 0
-
-#define PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8)
-#define DPORT_PRO_CAN_INT_MAP 0x0000001F
-#define DPORT_PRO_CAN_INT_MAP_S 0
-
-#define PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC)
-#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F
-#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0
-
-#define PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0)
-#define DPORT_PRO_RMT_INTR_MAP 0x0000001F
-#define DPORT_PRO_RMT_INTR_MAP_S 0
-
-#define PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4)
-#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F
-#define DPORT_PRO_PCNT_INTR_MAP_S 0
-
-#define PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8)
-#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F
-#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0
-
-#define PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC)
-#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F
-#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0
-
-#define PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0)
-#define DPORT_PRO_RSA_INTR_MAP 0x0000001F
-#define DPORT_PRO_RSA_INTR_MAP_S 0
-
-#define PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4)
-#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F
-#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0
-
-#define PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8)
-#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F
-#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0
-
-#define PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC)
-#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F
-#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0
-
-#define PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0)
-#define DPORT_PRO_WDG_INT_MAP 0x0000001F
-#define DPORT_PRO_WDG_INT_MAP_S 0
-
-#define PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4)
-#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F
-#define DPORT_PRO_TIMER_INT1_MAP_S 0
-
-#define PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8)
-#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F
-#define DPORT_PRO_TIMER_INT2_MAP_S 0
-
-#define PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC)
-#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F
-#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0
-
-#define PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0)
-#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F
-#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0
-
-#define PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4)
-#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F
-#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0
-
-#define PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8)
-#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F
-#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0
-
-#define PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC)
-#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F
-#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0
-
-#define PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200)
-#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F
-#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0
-
-#define PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204)
-#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F
-#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0
-
-#define PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208)
-#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F
-#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0
-
-#define PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C)
-#define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F
-#define DPORT_PRO_MMU_IA_INT_MAP_S 0
-
-#define PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210)
-#define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F
-#define DPORT_PRO_MPU_IA_INT_MAP_S 0
-
-#define PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214)
-#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F
-#define DPORT_PRO_CACHE_IA_INT_MAP_S 0
-
-#define APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218)
-#define DPORT_APP_MAC_INTR_MAP 0x0000001F
-#define DPORT_APP_MAC_INTR_MAP_S 0
-
-#define APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C)
-#define DPORT_APP_MAC_NMI_MAP 0x0000001F
-#define DPORT_APP_MAC_NMI_MAP_S 0
-
-#define APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220)
-#define DPORT_APP_BB_INT_MAP 0x0000001F
-#define DPORT_APP_BB_INT_MAP_S 0
-
-#define APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224)
-#define DPORT_APP_BT_MAC_INT_MAP 0x0000001F
-#define DPORT_APP_BT_MAC_INT_MAP_S 0
-
-#define APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228)
-#define DPORT_APP_BT_BB_INT_MAP 0x0000001F
-#define DPORT_APP_BT_BB_INT_MAP_S 0
-
-#define APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C)
-#define DPORT_APP_BT_BB_NMI_MAP 0x0000001F
-#define DPORT_APP_BT_BB_NMI_MAP_S 0
-
-#define APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230)
-#define DPORT_APP_RWBT_IRQ_MAP 0x0000001F
-#define DPORT_APP_RWBT_IRQ_MAP_S 0
-
-#define APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234)
-#define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F
-#define DPORT_APP_RWBLE_IRQ_MAP_S 0
-
-#define APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238)
-#define DPORT_APP_RWBT_NMI_MAP 0x0000001F
-#define DPORT_APP_RWBT_NMI_MAP_S 0
-
-#define APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C)
-#define DPORT_APP_RWBLE_NMI_MAP 0x0000001F
-#define DPORT_APP_RWBLE_NMI_MAP_S 0
-
-#define APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240)
-#define DPORT_APP_SLC0_INTR_MAP 0x0000001F
-#define DPORT_APP_SLC0_INTR_MAP_S 0
-
-#define APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244)
-#define DPORT_APP_SLC1_INTR_MAP 0x0000001F
-#define DPORT_APP_SLC1_INTR_MAP_S 0
-
-#define APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248)
-#define DPORT_APP_UHCI0_INTR_MAP 0x0000001F
-#define DPORT_APP_UHCI0_INTR_MAP_S 0
-
-#define APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C)
-#define DPORT_APP_UHCI1_INTR_MAP 0x0000001F
-#define DPORT_APP_UHCI1_INTR_MAP_S 0
-
-#define APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250)
-#define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F
-#define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0
-
-#define APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254)
-#define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F
-#define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0
-
-#define APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258)
-#define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F
-#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0
-
-#define APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C)
-#define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F
-#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0
-
-#define APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260)
-#define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F
-#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0
-
-#define APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264)
-#define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F
-#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0
-
-#define APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268)
-#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F
-#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0
-
-#define APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C)
-#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F
-#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0
-
-#define APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270)
-#define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F
-#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0
-
-#define APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274)
-#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F
-#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0
-
-#define APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278)
-#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
-#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0
-
-#define APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C)
-#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
-#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0
-
-#define APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280)
-#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
-#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0
-
-#define APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284)
-#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
-#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0
-
-#define APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288)
-#define DPORT_APP_SPI_INTR_0_MAP 0x0000001F
-#define DPORT_APP_SPI_INTR_0_MAP_S 0
-
-#define APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C)
-#define DPORT_APP_SPI_INTR_1_MAP 0x0000001F
-#define DPORT_APP_SPI_INTR_1_MAP_S 0
-
-#define APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290)
-#define DPORT_APP_SPI_INTR_2_MAP 0x0000001F
-#define DPORT_APP_SPI_INTR_2_MAP_S 0
-
-#define APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294)
-#define DPORT_APP_SPI_INTR_3_MAP 0x0000001F
-#define DPORT_APP_SPI_INTR_3_MAP_S 0
-
-#define APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298)
-#define DPORT_APP_I2S0_INT_MAP 0x0000001F
-#define DPORT_APP_I2S0_INT_MAP_S 0
-
-#define APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C)
-#define DPORT_APP_I2S1_INT_MAP 0x0000001F
-#define DPORT_APP_I2S1_INT_MAP_S 0
-
-#define APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0)
-#define DPORT_APP_UART_INTR_MAP 0x0000001F
-#define DPORT_APP_UART_INTR_MAP_S 0
-
-#define APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4)
-#define DPORT_APP_UART1_INTR_MAP 0x0000001F
-#define DPORT_APP_UART1_INTR_MAP_S 0
-
-#define APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8)
-#define DPORT_APP_UART2_INTR_MAP 0x0000001F
-#define DPORT_APP_UART2_INTR_MAP_S 0
-
-#define APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC)
-#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F
-#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0
-
-#define APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0)
-#define DPORT_APP_EMAC_INT_MAP 0x0000001F
-#define DPORT_APP_EMAC_INT_MAP_S 0
-
-#define APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4)
-#define DPORT_APP_PWM0_INTR_MAP 0x0000001F
-#define DPORT_APP_PWM0_INTR_MAP_S 0
-
-#define APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8)
-#define DPORT_APP_PWM1_INTR_MAP 0x0000001F
-#define DPORT_APP_PWM1_INTR_MAP_S 0
-
-#define APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC)
-#define DPORT_APP_PWM2_INTR_MAP 0x0000001F
-#define DPORT_APP_PWM2_INTR_MAP_S 0
-
-#define APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0)
-#define DPORT_APP_PWM3_INTR_MAP 0x0000001F
-#define DPORT_APP_PWM3_INTR_MAP_S 0
-
-#define APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4)
-#define DPORT_APP_LEDC_INT_MAP 0x0000001F
-#define DPORT_APP_LEDC_INT_MAP_S 0
-
-#define APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8)
-#define DPORT_APP_EFUSE_INT_MAP 0x0000001F
-#define DPORT_APP_EFUSE_INT_MAP_S 0
-
-#define APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC)
-#define DPORT_APP_CAN_INT_MAP 0x0000001F
-#define DPORT_APP_CAN_INT_MAP_S 0
-
-#define APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0)
-#define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F
-#define DPORT_APP_RTC_CORE_INTR_MAP_S 0
-
-#define APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4)
-#define DPORT_APP_RMT_INTR_MAP 0x0000001F
-#define DPORT_APP_RMT_INTR_MAP_S 0
-
-#define APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8)
-#define DPORT_APP_PCNT_INTR_MAP 0x0000001F
-#define DPORT_APP_PCNT_INTR_MAP_S 0
-
-#define APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC)
-#define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F
-#define DPORT_APP_I2C_EXT0_INTR_MAP_S 0
-
-#define APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0)
-#define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F
-#define DPORT_APP_I2C_EXT1_INTR_MAP_S 0
-
-#define APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4)
-#define DPORT_APP_RSA_INTR_MAP 0x0000001F
-#define DPORT_APP_RSA_INTR_MAP_S 0
-
-#define APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8)
-#define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F
-#define DPORT_APP_SPI1_DMA_INT_MAP_S 0
-
-#define APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC)
-#define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F
-#define DPORT_APP_SPI2_DMA_INT_MAP_S 0
-
-#define APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0)
-#define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F
-#define DPORT_APP_SPI3_DMA_INT_MAP_S 0
-
-#define APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4)
-#define DPORT_APP_WDG_INT_MAP 0x0000001F
-#define DPORT_APP_WDG_INT_MAP_S 0
-
-#define APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8)
-#define DPORT_APP_TIMER_INT1_MAP 0x0000001F
-#define DPORT_APP_TIMER_INT1_MAP_S 0
-
-#define APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC)
-#define DPORT_APP_TIMER_INT2_MAP 0x0000001F
-#define DPORT_APP_TIMER_INT2_MAP_S 0
-
-#define APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300)
-#define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F
-#define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0
-
-#define APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304)
-#define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F
-#define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0
-
-#define APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308)
-#define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F
-#define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0
-
-#define APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C)
-#define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F
-#define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0
-
-#define APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310)
-#define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F
-#define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0
-
-#define APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314)
-#define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F
-#define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0
-
-#define APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318)
-#define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F
-#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0
-
-#define APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C)
-#define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F
-#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0
-
-#define APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320)
-#define DPORT_APP_MMU_IA_INT_MAP 0x0000001F
-#define DPORT_APP_MMU_IA_INT_MAP_S 0
-
-#define APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324)
-#define DPORT_APP_MPU_IA_INT_MAP 0x0000001F
-#define DPORT_APP_MPU_IA_INT_MAP_S 0
-
-#define APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328)
-#define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F
-#define DPORT_APP_CACHE_IA_INT_MAP_S 0
-
-#define AHBLITE_MPU_TABLE_UART (DR_REG_DPORT_BASE + 0x32C)
-#define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_UART_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_SPI1 (DR_REG_DPORT_BASE + 0x330)
-#define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_SPI0 (DR_REG_DPORT_BASE + 0x334)
-#define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_GPIO (DR_REG_DPORT_BASE + 0x338)
-#define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_FE2 (DR_REG_DPORT_BASE + 0x33C)
-#define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_FE (DR_REG_DPORT_BASE + 0x340)
-#define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_FE_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_TIMER (DR_REG_DPORT_BASE + 0x344)
-#define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_RTC (DR_REG_DPORT_BASE + 0x348)
-#define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_IO_MUX (DR_REG_DPORT_BASE + 0x34C)
-#define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_WDG (DR_REG_DPORT_BASE + 0x350)
-#define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_HINF (DR_REG_DPORT_BASE + 0x354)
-#define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_UHCI1 (DR_REG_DPORT_BASE + 0x358)
-#define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_MISC (DR_REG_DPORT_BASE + 0x35C)
-#define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_I2C (DR_REG_DPORT_BASE + 0x360)
-#define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_I2S0 (DR_REG_DPORT_BASE + 0x364)
-#define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_UART1 (DR_REG_DPORT_BASE + 0x368)
-#define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_BT (DR_REG_DPORT_BASE + 0x36C)
-#define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_BT_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_BT_BUFFER (DR_REG_DPORT_BASE + 0x370)
-#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_I2C_EXT0 (DR_REG_DPORT_BASE + 0x374)
-#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_UHCI0 (DR_REG_DPORT_BASE + 0x378)
-#define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_SLCHOST (DR_REG_DPORT_BASE + 0x37C)
-#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_RMT (DR_REG_DPORT_BASE + 0x380)
-#define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_PCNT (DR_REG_DPORT_BASE + 0x384)
-#define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_SLC (DR_REG_DPORT_BASE + 0x388)
-#define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_LEDC (DR_REG_DPORT_BASE + 0x38C)
-#define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_EFUSE (DR_REG_DPORT_BASE + 0x390)
-#define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_SPI_ENCRYPT (DR_REG_DPORT_BASE + 0x394)
-#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_BB (DR_REG_DPORT_BASE + 0x398)
-#define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_BB_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_PWM0 (DR_REG_DPORT_BASE + 0x39C)
-#define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_TIMERGROUP (DR_REG_DPORT_BASE + 0x3A0)
-#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_TIMERGROUP1 (DR_REG_DPORT_BASE + 0x3A4)
-#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_SPI2 (DR_REG_DPORT_BASE + 0x3A8)
-#define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_SPI3 (DR_REG_DPORT_BASE + 0x3AC)
-#define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_APB_CTRL (DR_REG_DPORT_BASE + 0x3B0)
-#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_I2C_EXT1 (DR_REG_DPORT_BASE + 0x3B4)
-#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_SDIO_HOST (DR_REG_DPORT_BASE + 0x3B8)
-#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_EMAC (DR_REG_DPORT_BASE + 0x3BC)
-#define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_CAN (DR_REG_DPORT_BASE + 0x3C0)
-#define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_PWM1 (DR_REG_DPORT_BASE + 0x3C4)
-#define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_I2S1 (DR_REG_DPORT_BASE + 0x3C8)
-#define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_UART2 (DR_REG_DPORT_BASE + 0x3CC)
-#define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_PWM2 (DR_REG_DPORT_BASE + 0x3D0)
-#define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_PWM3 (DR_REG_DPORT_BASE + 0x3D4)
-#define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_RWBT (DR_REG_DPORT_BASE + 0x3D8)
-#define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_BTMAC (DR_REG_DPORT_BASE + 0x3DC)
-#define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_WIFIMAC (DR_REG_DPORT_BASE + 0x3E0)
-#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0
-
-#define AHBLITE_MPU_TABLE_PWR (DR_REG_DPORT_BASE + 0x3E4)
-#define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F
-#define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0
-
-#define MEM_ACCESS_DBUG0 (DR_REG_DPORT_BASE + 0x3E8)
-#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F
-#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26
-#define DPORT_INTERNAL_SRAM_IA 0x00000FFF
-#define DPORT_INTERNAL_SRAM_IA_S 14
-#define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F
-#define DPORT_INTERNAL_SRAM_MMU_AD_S 10
-#define DPORT_SHARE_ROM_IA 0x0000000F
-#define DPORT_SHARE_ROM_IA_S 6
-#define DPORT_SHARE_ROM_MPU_AD 0x00000003
-#define DPORT_SHARE_ROM_MPU_AD_S 4
-#define DPORT_APP_ROM_IA (BIT(3))
-#define DPORT_APP_ROM_IA_S 3
-#define DPORT_APP_ROM_MPU_AD (BIT(2))
-#define DPORT_APP_ROM_MPU_AD_S 2
-#define DPORT_PRO_ROM_IA (BIT(1))
-#define DPORT_PRO_ROM_IA_S 1
-#define DPORT_PRO_ROM_MPU_AD (BIT(0))
-#define DPORT_PRO_ROM_MPU_AD_S 0
-
-#define MEM_ACCESS_DBUG1 (DR_REG_DPORT_BASE + 0x3EC)
-#define DPORT_AHBLITE_IA (BIT(10))
-#define DPORT_AHBLITE_IA_S 10
-#define DPORT_AHBLITE_ACCESS_DENY (BIT(9))
-#define DPORT_AHBLITE_ACCESS_DENY_S 9
-#define DPORT_AHB_ACCESS_DENY (BIT(8))
-#define DPORT_AHB_ACCESS_DENY_S 8
-#define DPORT_DPORT_PIDGEN_IA 0x00000003
-#define DPORT_DPORT_PIDGEN_IA_S 6
-#define DPORT_DPORT_ARB_IA 0x00000003
-#define DPORT_DPORT_ARB_IA_S 4
-#define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F
-#define DPORT_INTERNAL_SRAM_MMU_MISS_S 0
-
-#define PRO_DCACHE_DBUG_REG0 (DR_REG_DPORT_BASE + 0x3F0)
-#define DPORT_PRO_RX_END (BIT(23))
-#define DPORT_PRO_RX_END_S 23
-#define DPORT_PRO_SLAVE_WDATA_V (BIT(22))
-#define DPORT_PRO_SLAVE_WDATA_V_S 22
-#define DPORT_PRO_SLAVE_WR (BIT(21))
-#define DPORT_PRO_SLAVE_WR_S 21
-#define DPORT_PRO_TX_END (BIT(20))
-#define DPORT_PRO_TX_END_S 20
-#define DPORT_PRO_WR_BAK_TO_READ (BIT(19))
-#define DPORT_PRO_WR_BAK_TO_READ_S 19
-#define DPORT_PRO_CACHE_STATE 0x00000FFF
-#define DPORT_PRO_CACHE_STATE_S 7
-#define DPORT_PRO_CACHE_IA 0x0000003F
-#define DPORT_PRO_CACHE_IA_S 1
-#define DPORT_PRO_CACHE_MMU_IA (BIT(0))
-#define DPORT_PRO_CACHE_MMU_IA_S 0
-
-#define PRO_DCACHE_DBUG_REG1 (DR_REG_DPORT_BASE + 0x3F4)
-#define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF
-#define DPORT_PRO_CTAG_RAM_RDATA_S 0
-
-#define PRO_DCACHE_DBUG_REG2 (DR_REG_DPORT_BASE + 0x3F8)
-#define DPORT_PRO_CACHE_VADDR 0x07FFFFFF
-#define DPORT_PRO_CACHE_VADDR_S 0
-
-#define PRO_DCACHE_DBUG_REG3 (DR_REG_DPORT_BASE + 0x3FC)
-#define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15))
-#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9
-#define DPORT_PRO_MMU_RDATA 0x000001FF
-#define DPORT_PRO_MMU_RDATA_S 0
-
-#define PRO_DCACHE_DBUG_REG4 (DR_REG_DPORT_BASE + 0x400)
-#define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF
-#define DPORT_PRO_DRAM1ADDR0_IA_S 0
-
-#define PRO_DCACHE_DBUG_REG5 (DR_REG_DPORT_BASE + 0x404)
-#define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF
-#define DPORT_PRO_DROM0ADDR0_IA_S 0
-
-#define PRO_DCACHE_DBUG_REG6 (DR_REG_DPORT_BASE + 0x408)
-#define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF
-#define DPORT_PRO_IRAM0ADDR_IA_S 0
-
-#define PRO_DCACHE_DBUG_REG7 (DR_REG_DPORT_BASE + 0x40C)
-#define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF
-#define DPORT_PRO_IRAM1ADDR_IA_S 0
-
-#define PRO_DCACHE_DBUG_REG8 (DR_REG_DPORT_BASE + 0x410)
-#define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF
-#define DPORT_PRO_IROM0ADDR_IA_S 0
-
-#define PRO_DCACHE_DBUG_REG9 (DR_REG_DPORT_BASE + 0x414)
-#define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF
-#define DPORT_PRO_OPSDRAMADDR_IA_S 0
-
-#define APP_DCACHE_DBUG_REG0 (DR_REG_DPORT_BASE + 0x418)
-#define DPORT_APP_RX_END (BIT(23))
-#define DPORT_APP_RX_END_S 23
-#define DPORT_APP_SLAVE_WDATA_V (BIT(22))
-#define DPORT_APP_SLAVE_WDATA_V_S 22
-#define DPORT_APP_SLAVE_WR (BIT(21))
-#define DPORT_APP_SLAVE_WR_S 21
-#define DPORT_APP_TX_END (BIT(20))
-#define DPORT_APP_TX_END_S 20
-#define DPORT_APP_WR_BAK_TO_READ (BIT(19))
-#define DPORT_APP_WR_BAK_TO_READ_S 19
-#define DPORT_APP_CACHE_STATE 0x00000FFF
-#define DPORT_APP_CACHE_STATE_S 7
-#define DPORT_APP_CACHE_IA 0x0000003F
-#define DPORT_APP_CACHE_IA_S 1
-#define DPORT_APP_CACHE_MMU_IA (BIT(0))
-#define DPORT_APP_CACHE_MMU_IA_S 0
-
-#define APP_DCACHE_DBUG_REG1 (DR_REG_DPORT_BASE + 0x41C)
-#define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF
-#define DPORT_APP_CTAG_RAM_RDATA_S 0
-
-#define APP_DCACHE_DBUG_REG2 (DR_REG_DPORT_BASE + 0x420)
-#define DPORT_APP_CACHE_VADDR 0x07FFFFFF
-#define DPORT_APP_CACHE_VADDR_S 0
-
-#define APP_DCACHE_DBUG_REG3 (DR_REG_DPORT_BASE + 0x424)
-#define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15))
-#define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15
-#define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9
-#define DPORT_APP_MMU_RDATA 0x000001FF
-#define DPORT_APP_MMU_RDATA_S 0
-
-#define APP_DCACHE_DBUG_REG4 (DR_REG_DPORT_BASE + 0x428)
-#define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF
-#define DPORT_APP_DRAM1ADDR0_IA_S 0
-
-#define APP_DCACHE_DBUG_REG5 (DR_REG_DPORT_BASE + 0x42C)
-#define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF
-#define DPORT_APP_DROM0ADDR0_IA_S 0
-
-#define APP_DCACHE_DBUG_REG6 (DR_REG_DPORT_BASE + 0x430)
-#define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF
-#define DPORT_APP_IRAM0ADDR_IA_S 0
-
-#define APP_DCACHE_DBUG_REG7 (DR_REG_DPORT_BASE + 0x434)
-#define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF
-#define DPORT_APP_IRAM1ADDR_IA_S 0
-
-#define APP_DCACHE_DBUG_REG8 (DR_REG_DPORT_BASE + 0x438)
-#define DPORT_APP_IROM0ADDR_IA 0x000FFFFF
-#define DPORT_APP_IROM0ADDR_IA_S 0
-
-#define APP_DCACHE_DBUG_REG9 (DR_REG_DPORT_BASE + 0x43C)
-#define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF
-#define DPORT_APP_OPSDRAMADDR_IA_S 0
-
-#define PRO_CPU_RECORD_CTRL (DR_REG_DPORT_BASE + 0x440)
-#define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8))
-#define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8
-#define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4))
-#define DPORT_PRO_CPU_RECORD_DISABLE_S 4
-#define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0))
-#define DPORT_PRO_CPU_RECORD_ENABLE_S 0
-
-#define PRO_CPU_RECORD_STATUS (DR_REG_DPORT_BASE + 0x444)
-#define DPORT_PRO_CPU_RECORDING (BIT(0))
-#define DPORT_PRO_CPU_RECORDING_S 0
-
-#define PRO_CPU_RECORD_PID (DR_REG_DPORT_BASE + 0x448)
-#define DPORT_RECORD_PRO_PID 0x00000007
-#define DPORT_RECORD_PRO_PID_S 0
-
-#define PRO_CPU_RECORD_PDEBUGINST (DR_REG_DPORT_BASE + 0x44C)
-#define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGINST_S 0
-
-#define PRO_CPU_RECORD_PDEBUGSTATUS (DR_REG_DPORT_BASE + 0x450)
-#define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF
-#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0
-
-#define PRO_CPU_RECORD_PDEBUGDATA (DR_REG_DPORT_BASE + 0x454)
-#define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGDATA_S 0
-
-#define PRO_CPU_RECORD_PDEBUGPC (DR_REG_DPORT_BASE + 0x458)
-#define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGPC_S 0
-
-#define PRO_CPU_RECORD_PDEBUGLS0STAT (DR_REG_DPORT_BASE + 0x45C)
-#define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0
-
-#define PRO_CPU_RECORD_PDEBUGLS0ADDR (DR_REG_DPORT_BASE + 0x460)
-#define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0
-
-#define PRO_CPU_RECORD_PDEBUGLS0DATA (DR_REG_DPORT_BASE + 0x464)
-#define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0
-
-#define APP_CPU_RECORD_CTRL (DR_REG_DPORT_BASE + 0x468)
-#define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8))
-#define DPORT_APP_CPU_PDEBUG_ENABLE_S 8
-#define DPORT_APP_CPU_RECORD_DISABLE (BIT(4))
-#define DPORT_APP_CPU_RECORD_DISABLE_S 4
-#define DPORT_APP_CPU_RECORD_ENABLE (BIT(0))
-#define DPORT_APP_CPU_RECORD_ENABLE_S 0
-
-#define APP_CPU_RECORD_STATUS (DR_REG_DPORT_BASE + 0x46C)
-#define DPORT_APP_CPU_RECORDING (BIT(0))
-#define DPORT_APP_CPU_RECORDING_S 0
-
-#define APP_CPU_RECORD_PID (DR_REG_DPORT_BASE + 0x470)
-#define DPORT_RECORD_APP_PID 0x00000007
-#define DPORT_RECORD_APP_PID_S 0
-
-#define APP_CPU_RECORD_PDEBUGINST (DR_REG_DPORT_BASE + 0x474)
-#define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGINST_S 0
-
-#define APP_CPU_RECORD_PDEBUGSTATUS (DR_REG_DPORT_BASE + 0x478)
-#define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF
-#define DPORT_RECORD_APP_PDEBUGSTATUS_S 0
-
-#define APP_CPU_RECORD_PDEBUGDATA (DR_REG_DPORT_BASE + 0x47C)
-#define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGDATA_S 0
-
-#define APP_CPU_RECORD_PDEBUGPC (DR_REG_DPORT_BASE + 0x480)
-#define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGPC_S 0
-
-#define APP_CPU_RECORD_PDEBUGLS0STAT (DR_REG_DPORT_BASE + 0x484)
-#define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0
-
-#define APP_CPU_RECORD_PDEBUGLS0ADDR (DR_REG_DPORT_BASE + 0x488)
-#define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0
-
-#define APP_CPU_RECORD_PDEBUGLS0DATA (DR_REG_DPORT_BASE + 0x48C)
-#define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0
-
-#define RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490)
-#define DPORT_RSA_PD (BIT(0))
-#define DPORT_RSA_PD_S 0
-
-#define ROM_MPU_TABLE0 (DR_REG_DPORT_BASE + 0x494)
-#define DPORT_ROM_MPU_TABLE0 0x00000003
-#define DPORT_ROM_MPU_TABLE0_S 0
-
-#define ROM_MPU_TABLE1 (DR_REG_DPORT_BASE + 0x498)
-#define DPORT_ROM_MPU_TABLE1 0x00000003
-#define DPORT_ROM_MPU_TABLE1_S 0
-
-#define ROM_MPU_TABLE2 (DR_REG_DPORT_BASE + 0x49C)
-#define DPORT_ROM_MPU_TABLE2 0x00000003
-#define DPORT_ROM_MPU_TABLE2_S 0
-
-#define ROM_MPU_TABLE3 (DR_REG_DPORT_BASE + 0x4A0)
-#define DPORT_ROM_MPU_TABLE3 0x00000003
-#define DPORT_ROM_MPU_TABLE3_S 0
-
-#define SHROM_MPU_TABLE0 (DR_REG_DPORT_BASE + 0x4A4)
-#define DPORT_SHROM_MPU_TABLE0 0x00000003
-#define DPORT_SHROM_MPU_TABLE0_S 0
-
-#define SHROM_MPU_TABLE1 (DR_REG_DPORT_BASE + 0x4A8)
-#define DPORT_SHROM_MPU_TABLE1 0x00000003
-#define DPORT_SHROM_MPU_TABLE1_S 0
-
-#define SHROM_MPU_TABLE2 (DR_REG_DPORT_BASE + 0x4AC)
-#define DPORT_SHROM_MPU_TABLE2 0x00000003
-#define DPORT_SHROM_MPU_TABLE2_S 0
-
-#define SHROM_MPU_TABLE3 (DR_REG_DPORT_BASE + 0x4B0)
-#define DPORT_SHROM_MPU_TABLE3 0x00000003
-#define DPORT_SHROM_MPU_TABLE3_S 0
-
-#define SHROM_MPU_TABLE4 (DR_REG_DPORT_BASE + 0x4B4)
-#define DPORT_SHROM_MPU_TABLE4 0x00000003
-#define DPORT_SHROM_MPU_TABLE4_S 0
-
-#define SHROM_MPU_TABLE5 (DR_REG_DPORT_BASE + 0x4B8)
-#define DPORT_SHROM_MPU_TABLE5 0x00000003
-#define DPORT_SHROM_MPU_TABLE5_S 0
-
-#define SHROM_MPU_TABLE6 (DR_REG_DPORT_BASE + 0x4BC)
-#define DPORT_SHROM_MPU_TABLE6 0x00000003
-#define DPORT_SHROM_MPU_TABLE6_S 0
-
-#define SHROM_MPU_TABLE7 (DR_REG_DPORT_BASE + 0x4C0)
-#define DPORT_SHROM_MPU_TABLE7 0x00000003
-#define DPORT_SHROM_MPU_TABLE7_S 0
-
-#define SHROM_MPU_TABLE8 (DR_REG_DPORT_BASE + 0x4C4)
-#define DPORT_SHROM_MPU_TABLE8 0x00000003
-#define DPORT_SHROM_MPU_TABLE8_S 0
-
-#define SHROM_MPU_TABLE9 (DR_REG_DPORT_BASE + 0x4C8)
-#define DPORT_SHROM_MPU_TABLE9 0x00000003
-#define DPORT_SHROM_MPU_TABLE9_S 0
-
-#define SHROM_MPU_TABLE10 (DR_REG_DPORT_BASE + 0x4CC)
-#define DPORT_SHROM_MPU_TABLE10 0x00000003
-#define DPORT_SHROM_MPU_TABLE10_S 0
-
-#define SHROM_MPU_TABLE11 (DR_REG_DPORT_BASE + 0x4D0)
-#define DPORT_SHROM_MPU_TABLE11 0x00000003
-#define DPORT_SHROM_MPU_TABLE11_S 0
-
-#define SHROM_MPU_TABLE12 (DR_REG_DPORT_BASE + 0x4D4)
-#define DPORT_SHROM_MPU_TABLE12 0x00000003
-#define DPORT_SHROM_MPU_TABLE12_S 0
-
-#define SHROM_MPU_TABLE13 (DR_REG_DPORT_BASE + 0x4D8)
-#define DPORT_SHROM_MPU_TABLE13 0x00000003
-#define DPORT_SHROM_MPU_TABLE13_S 0
-
-#define SHROM_MPU_TABLE14 (DR_REG_DPORT_BASE + 0x4DC)
-#define DPORT_SHROM_MPU_TABLE14 0x00000003
-#define DPORT_SHROM_MPU_TABLE14_S 0
-
-#define SHROM_MPU_TABLE15 (DR_REG_DPORT_BASE + 0x4E0)
-#define DPORT_SHROM_MPU_TABLE15 0x00000003
-#define DPORT_SHROM_MPU_TABLE15_S 0
-
-#define SHROM_MPU_TABLE16 (DR_REG_DPORT_BASE + 0x4E4)
-#define DPORT_SHROM_MPU_TABLE16 0x00000003
-#define DPORT_SHROM_MPU_TABLE16_S 0
-
-#define SHROM_MPU_TABLE17 (DR_REG_DPORT_BASE + 0x4E8)
-#define DPORT_SHROM_MPU_TABLE17 0x00000003
-#define DPORT_SHROM_MPU_TABLE17_S 0
-
-#define SHROM_MPU_TABLE18 (DR_REG_DPORT_BASE + 0x4EC)
-#define DPORT_SHROM_MPU_TABLE18 0x00000003
-#define DPORT_SHROM_MPU_TABLE18_S 0
-
-#define SHROM_MPU_TABLE19 (DR_REG_DPORT_BASE + 0x4F0)
-#define DPORT_SHROM_MPU_TABLE19 0x00000003
-#define DPORT_SHROM_MPU_TABLE19_S 0
-
-#define SHROM_MPU_TABLE20 (DR_REG_DPORT_BASE + 0x4F4)
-#define DPORT_SHROM_MPU_TABLE20 0x00000003
-#define DPORT_SHROM_MPU_TABLE20_S 0
-
-#define SHROM_MPU_TABLE21 (DR_REG_DPORT_BASE + 0x4F8)
-#define DPORT_SHROM_MPU_TABLE21 0x00000003
-#define DPORT_SHROM_MPU_TABLE21_S 0
-
-#define SHROM_MPU_TABLE22 (DR_REG_DPORT_BASE + 0x4FC)
-#define DPORT_SHROM_MPU_TABLE22 0x00000003
-#define DPORT_SHROM_MPU_TABLE22_S 0
-
-#define SHROM_MPU_TABLE23 (DR_REG_DPORT_BASE + 0x500)
-#define DPORT_SHROM_MPU_TABLE23 0x00000003
-#define DPORT_SHROM_MPU_TABLE23_S 0
-
-#define IMMU_TABLE0 (DR_REG_DPORT_BASE + 0x504)
-#define DPORT_IMMU_TABLE0 0x0000007F
-#define DPORT_IMMU_TABLE0_S 0
-
-#define IMMU_TABLE1 (DR_REG_DPORT_BASE + 0x508)
-#define DPORT_IMMU_TABLE1 0x0000007F
-#define DPORT_IMMU_TABLE1_S 0
-
-#define IMMU_TABLE2 (DR_REG_DPORT_BASE + 0x50C)
-#define DPORT_IMMU_TABLE2 0x0000007F
-#define DPORT_IMMU_TABLE2_S 0
-
-#define IMMU_TABLE3 (DR_REG_DPORT_BASE + 0x510)
-#define DPORT_IMMU_TABLE3 0x0000007F
-#define DPORT_IMMU_TABLE3_S 0
-
-#define IMMU_TABLE4 (DR_REG_DPORT_BASE + 0x514)
-#define DPORT_IMMU_TABLE4 0x0000007F
-#define DPORT_IMMU_TABLE4_S 0
-
-#define IMMU_TABLE5 (DR_REG_DPORT_BASE + 0x518)
-#define DPORT_IMMU_TABLE5 0x0000007F
-#define DPORT_IMMU_TABLE5_S 0
-
-#define IMMU_TABLE6 (DR_REG_DPORT_BASE + 0x51C)
-#define DPORT_IMMU_TABLE6 0x0000007F
-#define DPORT_IMMU_TABLE6_S 0
-
-#define IMMU_TABLE7 (DR_REG_DPORT_BASE + 0x520)
-#define DPORT_IMMU_TABLE7 0x0000007F
-#define DPORT_IMMU_TABLE7_S 0
+#define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000)
+/* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_BOOT_REMAP (BIT(0))
+#define DPORT_PRO_BOOT_REMAP_M (BIT(0))
+#define DPORT_PRO_BOOT_REMAP_V 0x1
+#define DPORT_PRO_BOOT_REMAP_S 0
+
+#define DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004)
+/* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_BOOT_REMAP (BIT(0))
+#define DPORT_APP_BOOT_REMAP_M (BIT(0))
+#define DPORT_APP_BOOT_REMAP_V 0x1
+#define DPORT_APP_BOOT_REMAP_S 0
+
+#define DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008)
+/* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ACCESS_CHECK_APP (BIT(8))
+#define DPORT_ACCESS_CHECK_APP_M (BIT(8))
+#define DPORT_ACCESS_CHECK_APP_V 0x1
+#define DPORT_ACCESS_CHECK_APP_S 8
+/* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ACCESS_CHECK_PRO (BIT(0))
+#define DPORT_ACCESS_CHECK_PRO_M (BIT(0))
+#define DPORT_ACCESS_CHECK_PRO_V 0x1
+#define DPORT_ACCESS_CHECK_PRO_S 0
+
+#define DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C)
+/* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF
+#define DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S))
+#define DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF
+#define DPORT_PRODPORT_APB_MASK0_S 0
+
+#define DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010)
+/* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF
+#define DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S))
+#define DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF
+#define DPORT_PRODPORT_APB_MASK1_S 0
+
+#define DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014)
+/* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF
+#define DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S))
+#define DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF
+#define DPORT_APPDPORT_APB_MASK0_S 0
+
+#define DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018)
+/* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF
+#define DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S))
+#define DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF
+#define DPORT_APPDPORT_APB_MASK1_S 0
+
+#define DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C)
+/* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PERI_CLK_EN 0xFFFFFFFF
+#define DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S))
+#define DPORT_PERI_CLK_EN_V 0xFFFFFFFF
+#define DPORT_PERI_CLK_EN_S 0
+
+#define DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020)
+/* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PERI_RST_EN 0xFFFFFFFF
+#define DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S))
+#define DPORT_PERI_RST_EN_V 0xFFFFFFFF
+#define DPORT_PERI_RST_EN_S 0
+
+#define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024)
+/* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_WIFI_BB_CFG 0xFFFFFFFF
+#define DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S))
+#define DPORT_WIFI_BB_CFG_V 0xFFFFFFFF
+#define DPORT_WIFI_BB_CFG_S 0
+
+#define DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028)
+/* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF
+#define DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S))
+#define DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF
+#define DPORT_WIFI_BB_CFG_2_S 0
+
+#define DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C)
+/* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APPCPU_RESETTING (BIT(0))
+#define DPORT_APPCPU_RESETTING_M (BIT(0))
+#define DPORT_APPCPU_RESETTING_V 0x1
+#define DPORT_APPCPU_RESETTING_S 0
+
+#define DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030)
+/* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APPCPU_CLKGATE_EN (BIT(0))
+#define DPORT_APPCPU_CLKGATE_EN_M (BIT(0))
+#define DPORT_APPCPU_CLKGATE_EN_V 0x1
+#define DPORT_APPCPU_CLKGATE_EN_S 0
+
+#define DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034)
+/* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APPCPU_RUNSTALL (BIT(0))
+#define DPORT_APPCPU_RUNSTALL_M (BIT(0))
+#define DPORT_APPCPU_RUNSTALL_V 0x1
+#define DPORT_APPCPU_RUNSTALL_S 0
+
+#define DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038)
+/* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF
+#define DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S))
+#define DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF
+#define DPORT_APPCPU_BOOT_ADDR_S 0
+
+#define DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C)
+/* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_FAST_CLK_RTC_SEL (BIT(3))
+#define DPORT_FAST_CLK_RTC_SEL_M (BIT(3))
+#define DPORT_FAST_CLK_RTC_SEL_V 0x1
+#define DPORT_FAST_CLK_RTC_SEL_S 3
+/* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LOWSPEED_CLK_SEL (BIT(2))
+#define DPORT_LOWSPEED_CLK_SEL_M (BIT(2))
+#define DPORT_LOWSPEED_CLK_SEL_V 0x1
+#define DPORT_LOWSPEED_CLK_SEL_S 2
+/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_CPUPERIOD_SEL 0x00000003
+#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
+#define DPORT_CPUPERIOD_SEL_V 0x3
+#define DPORT_CPUPERIOD_SEL_S 0
+
+#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040)
+/* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DRAM_HL (BIT(16))
+#define DPORT_PRO_DRAM_HL_M (BIT(16))
+#define DPORT_PRO_DRAM_HL_V 0x1
+#define DPORT_PRO_DRAM_HL_S 16
+/* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SLAVE_REQ (BIT(15))
+#define DPORT_SLAVE_REQ_M (BIT(15))
+#define DPORT_SLAVE_REQ_V 0x1
+#define DPORT_SLAVE_REQ_S 15
+/* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHB_SPI_REQ (BIT(14))
+#define DPORT_AHB_SPI_REQ_M (BIT(14))
+#define DPORT_AHB_SPI_REQ_V 0x1
+#define DPORT_AHB_SPI_REQ_S 14
+/* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_SLAVE_REQ (BIT(13))
+#define DPORT_PRO_SLAVE_REQ_M (BIT(13))
+#define DPORT_PRO_SLAVE_REQ_V 0x1
+#define DPORT_PRO_SLAVE_REQ_S 13
+/* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_AHB_SPI_REQ (BIT(12))
+#define DPORT_PRO_AHB_SPI_REQ_M (BIT(12))
+#define DPORT_PRO_AHB_SPI_REQ_V 0x1
+#define DPORT_PRO_AHB_SPI_REQ_S 12
+/* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DRAM_SPLIT (BIT(11))
+#define DPORT_PRO_DRAM_SPLIT_M (BIT(11))
+#define DPORT_PRO_DRAM_SPLIT_V 0x1
+#define DPORT_PRO_DRAM_SPLIT_S 11
+/* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10))
+#define DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10))
+#define DPORT_PRO_SINGLE_IRAM_ENA_V 0x1
+#define DPORT_PRO_SINGLE_IRAM_ENA_S 10
+/* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9))
+#define DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9))
+#define DPORT_PRO_CACHE_LOCK_3_EN_V 0x1
+#define DPORT_PRO_CACHE_LOCK_3_EN_S 9
+/* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8))
+#define DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8))
+#define DPORT_PRO_CACHE_LOCK_2_EN_V 0x1
+#define DPORT_PRO_CACHE_LOCK_2_EN_S 8
+/* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7))
+#define DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7))
+#define DPORT_PRO_CACHE_LOCK_1_EN_V 0x1
+#define DPORT_PRO_CACHE_LOCK_1_EN_S 7
+/* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6))
+#define DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6))
+#define DPORT_PRO_CACHE_LOCK_0_EN_V 0x1
+#define DPORT_PRO_CACHE_LOCK_0_EN_S 6
+/* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5))
+#define DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5))
+#define DPORT_PRO_CACHE_FLUSH_DONE_V 0x1
+#define DPORT_PRO_CACHE_FLUSH_DONE_S 5
+/* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4))
+#define DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4))
+#define DPORT_PRO_CACHE_FLUSH_ENA_V 0x1
+#define DPORT_PRO_CACHE_FLUSH_ENA_S 4
+/* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_ENABLE (BIT(3))
+#define DPORT_PRO_CACHE_ENABLE_M (BIT(3))
+#define DPORT_PRO_CACHE_ENABLE_V 0x1
+#define DPORT_PRO_CACHE_ENABLE_S 3
+/* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MODE (BIT(2))
+#define DPORT_PRO_CACHE_MODE_M (BIT(2))
+#define DPORT_PRO_CACHE_MODE_V 0x1
+#define DPORT_PRO_CACHE_MODE_S 2
+
+#define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044)
+/* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13))
+#define DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13))
+#define DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1
+#define DPORT_PRO_CACHE_MMU_IA_CLR_S 13
+/* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CMMU_PD (BIT(12))
+#define DPORT_PRO_CMMU_PD_M (BIT(12))
+#define DPORT_PRO_CMMU_PD_V 0x1
+#define DPORT_PRO_CMMU_PD_S 12
+/* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CMMU_FORCE_ON (BIT(11))
+#define DPORT_PRO_CMMU_FORCE_ON_M (BIT(11))
+#define DPORT_PRO_CMMU_FORCE_ON_V 0x1
+#define DPORT_PRO_CMMU_FORCE_ON_S 11
+/* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003
+#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S))
+#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3
+#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9
+/* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */
+/*description: */
+#define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007
+#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S))
+#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7
+#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6
+/* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5))
+#define DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5))
+#define DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1
+#define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5
+/* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4))
+#define DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4))
+#define DPORT_PRO_CACHE_MASK_DROM0_V 0x1
+#define DPORT_PRO_CACHE_MASK_DROM0_S 4
+/* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3))
+#define DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3))
+#define DPORT_PRO_CACHE_MASK_DRAM1_V 0x1
+#define DPORT_PRO_CACHE_MASK_DRAM1_S 3
+/* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2))
+#define DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2))
+#define DPORT_PRO_CACHE_MASK_IROM0_V 0x1
+#define DPORT_PRO_CACHE_MASK_IROM0_S 2
+/* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1))
+#define DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1))
+#define DPORT_PRO_CACHE_MASK_IRAM1_V 0x1
+#define DPORT_PRO_CACHE_MASK_IRAM1_S 1
+/* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0))
+#define DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0))
+#define DPORT_PRO_CACHE_MASK_IRAM0_V 0x1
+#define DPORT_PRO_CACHE_MASK_IRAM0_S 0
+
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048)
+/* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S))
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18
+/* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S))
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14
+/* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S))
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0
+
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C)
+/* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S))
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18
+/* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S))
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14
+/* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S))
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0
+
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050)
+/* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S))
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18
+/* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S))
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14
+/* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S))
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0
+
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054)
+/* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S))
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18
+/* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S))
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14
+/* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S))
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0
+
+#define DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058)
+/* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_DRAM_HL (BIT(14))
+#define DPORT_APP_DRAM_HL_M (BIT(14))
+#define DPORT_APP_DRAM_HL_V 0x1
+#define DPORT_APP_DRAM_HL_S 14
+/* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_SLAVE_REQ (BIT(13))
+#define DPORT_APP_SLAVE_REQ_M (BIT(13))
+#define DPORT_APP_SLAVE_REQ_V 0x1
+#define DPORT_APP_SLAVE_REQ_S 13
+/* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_AHB_SPI_REQ (BIT(12))
+#define DPORT_APP_AHB_SPI_REQ_M (BIT(12))
+#define DPORT_APP_AHB_SPI_REQ_V 0x1
+#define DPORT_APP_AHB_SPI_REQ_S 12
+/* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_DRAM_SPLIT (BIT(11))
+#define DPORT_APP_DRAM_SPLIT_M (BIT(11))
+#define DPORT_APP_DRAM_SPLIT_V 0x1
+#define DPORT_APP_DRAM_SPLIT_S 11
+/* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_SINGLE_IRAM_ENA (BIT(10))
+#define DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10))
+#define DPORT_APP_SINGLE_IRAM_ENA_V 0x1
+#define DPORT_APP_SINGLE_IRAM_ENA_S 10
+/* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_3_EN (BIT(9))
+#define DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9))
+#define DPORT_APP_CACHE_LOCK_3_EN_V 0x1
+#define DPORT_APP_CACHE_LOCK_3_EN_S 9
+/* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_2_EN (BIT(8))
+#define DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8))
+#define DPORT_APP_CACHE_LOCK_2_EN_V 0x1
+#define DPORT_APP_CACHE_LOCK_2_EN_S 8
+/* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_1_EN (BIT(7))
+#define DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7))
+#define DPORT_APP_CACHE_LOCK_1_EN_V 0x1
+#define DPORT_APP_CACHE_LOCK_1_EN_S 7
+/* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_0_EN (BIT(6))
+#define DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6))
+#define DPORT_APP_CACHE_LOCK_0_EN_V 0x1
+#define DPORT_APP_CACHE_LOCK_0_EN_S 6
+/* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_FLUSH_DONE (BIT(5))
+#define DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5))
+#define DPORT_APP_CACHE_FLUSH_DONE_V 0x1
+#define DPORT_APP_CACHE_FLUSH_DONE_S 5
+/* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CACHE_FLUSH_ENA (BIT(4))
+#define DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4))
+#define DPORT_APP_CACHE_FLUSH_ENA_V 0x1
+#define DPORT_APP_CACHE_FLUSH_ENA_S 4
+/* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_ENABLE (BIT(3))
+#define DPORT_APP_CACHE_ENABLE_M (BIT(3))
+#define DPORT_APP_CACHE_ENABLE_V 0x1
+#define DPORT_APP_CACHE_ENABLE_S 3
+/* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_MODE (BIT(2))
+#define DPORT_APP_CACHE_MODE_M (BIT(2))
+#define DPORT_APP_CACHE_MODE_V 0x1
+#define DPORT_APP_CACHE_MODE_S 2
+
+#define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C)
+/* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13))
+#define DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13))
+#define DPORT_APP_CACHE_MMU_IA_CLR_V 0x1
+#define DPORT_APP_CACHE_MMU_IA_CLR_S 13
+/* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CMMU_PD (BIT(12))
+#define DPORT_APP_CMMU_PD_M (BIT(12))
+#define DPORT_APP_CMMU_PD_V 0x1
+#define DPORT_APP_CMMU_PD_S 12
+/* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CMMU_FORCE_ON (BIT(11))
+#define DPORT_APP_CMMU_FORCE_ON_M (BIT(11))
+#define DPORT_APP_CMMU_FORCE_ON_V 0x1
+#define DPORT_APP_CMMU_FORCE_ON_S 11
+/* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003
+#define DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S))
+#define DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3
+#define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9
+/* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */
+/*description: */
+#define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007
+#define DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S))
+#define DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7
+#define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6
+/* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5))
+#define DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5))
+#define DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1
+#define DPORT_APP_CACHE_MASK_OPSDRAM_S 5
+/* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CACHE_MASK_DROM0 (BIT(4))
+#define DPORT_APP_CACHE_MASK_DROM0_M (BIT(4))
+#define DPORT_APP_CACHE_MASK_DROM0_V 0x1
+#define DPORT_APP_CACHE_MASK_DROM0_S 4
+/* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3))
+#define DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3))
+#define DPORT_APP_CACHE_MASK_DRAM1_V 0x1
+#define DPORT_APP_CACHE_MASK_DRAM1_S 3
+/* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CACHE_MASK_IROM0 (BIT(2))
+#define DPORT_APP_CACHE_MASK_IROM0_M (BIT(2))
+#define DPORT_APP_CACHE_MASK_IROM0_V 0x1
+#define DPORT_APP_CACHE_MASK_IROM0_S 2
+/* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1))
+#define DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1))
+#define DPORT_APP_CACHE_MASK_IRAM1_V 0x1
+#define DPORT_APP_CACHE_MASK_IRAM1_S 1
+/* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0))
+#define DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0))
+#define DPORT_APP_CACHE_MASK_IRAM0_V 0x1
+#define DPORT_APP_CACHE_MASK_IRAM0_S 0
+
+#define DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060)
+/* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S))
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18
+/* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S))
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14
+/* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF
+#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S))
+#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF
+#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0
+
+#define DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064)
+/* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S))
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18
+/* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S))
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14
+/* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF
+#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S))
+#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF
+#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0
+
+#define DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068)
+/* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S))
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18
+/* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S))
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14
+/* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF
+#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S))
+#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF
+#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0
+
+#define DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C)
+/* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S))
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18
+/* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S))
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14
+/* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF
+#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S))
+#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF
+#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0
+
+#define DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070)
+/* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_TRACEMEM_MUX_MODE 0x00000003
+#define DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S))
+#define DPORT_TRACEMEM_MUX_MODE_V 0x3
+#define DPORT_TRACEMEM_MUX_MODE_S 0
+
+#define DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074)
+/* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_TRACEMEM_ENA (BIT(0))
+#define DPORT_PRO_TRACEMEM_ENA_M (BIT(0))
+#define DPORT_PRO_TRACEMEM_ENA_V 0x1
+#define DPORT_PRO_TRACEMEM_ENA_S 0
+
+#define DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078)
+/* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_TRACEMEM_ENA (BIT(0))
+#define DPORT_APP_TRACEMEM_ENA_M (BIT(0))
+#define DPORT_APP_TRACEMEM_ENA_V 0x1
+#define DPORT_APP_TRACEMEM_ENA_S 0
+
+#define DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C)
+/* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_CACHE_MUX_MODE 0x00000003
+#define DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S))
+#define DPORT_CACHE_MUX_MODE_V 0x3
+#define DPORT_CACHE_MUX_MODE_S 0
+
+#define DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080)
+/* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_IMMU_PAGE_MODE 0x00000003
+#define DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S))
+#define DPORT_IMMU_PAGE_MODE_V 0x3
+#define DPORT_IMMU_PAGE_MODE_S 1
+/* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0))
+#define DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0))
+#define DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1
+#define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0
+
+#define DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084)
+/* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_DMMU_PAGE_MODE 0x00000003
+#define DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S))
+#define DPORT_DMMU_PAGE_MODE_V 0x3
+#define DPORT_DMMU_PAGE_MODE_S 1
+/* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0))
+#define DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0))
+#define DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1
+#define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0
+
+#define DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088)
+/* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_ROM_MPU_ENA (BIT(2))
+#define DPORT_APP_ROM_MPU_ENA_M (BIT(2))
+#define DPORT_APP_ROM_MPU_ENA_V 0x1
+#define DPORT_APP_ROM_MPU_ENA_S 2
+/* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ROM_MPU_ENA (BIT(1))
+#define DPORT_PRO_ROM_MPU_ENA_M (BIT(1))
+#define DPORT_PRO_ROM_MPU_ENA_V 0x1
+#define DPORT_PRO_ROM_MPU_ENA_S 1
+/* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SHARE_ROM_MPU_ENA (BIT(0))
+#define DPORT_SHARE_ROM_MPU_ENA_M (BIT(0))
+#define DPORT_SHARE_ROM_MPU_ENA_V 0x1
+#define DPORT_SHARE_ROM_MPU_ENA_S 0
+
+#define DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C)
+/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_LSLP_MEM_PD_MASK (BIT(0))
+#define DPORT_LSLP_MEM_PD_MASK_M (BIT(0))
+#define DPORT_LSLP_MEM_PD_MASK_V 0x1
+#define DPORT_LSLP_MEM_PD_MASK_S 0
+
+#define DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090)
+/* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */
+/*description: */
+#define DPORT_SHARE_ROM_PD 0x0000003F
+#define DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S))
+#define DPORT_SHARE_ROM_PD_V 0x3F
+#define DPORT_SHARE_ROM_PD_S 2
+/* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define DPORT_APP_ROM_PD (BIT(1))
+#define DPORT_APP_ROM_PD_M (BIT(1))
+#define DPORT_APP_ROM_PD_V 0x1
+#define DPORT_APP_ROM_PD_S 1
+/* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define DPORT_PRO_ROM_PD (BIT(0))
+#define DPORT_PRO_ROM_PD_M (BIT(0))
+#define DPORT_PRO_ROM_PD_V 0x1
+#define DPORT_PRO_ROM_PD_S 0
+
+#define DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094)
+/* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */
+/*description: */
+#define DPORT_SHARE_ROM_FO 0x0000003F
+#define DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S))
+#define DPORT_SHARE_ROM_FO_V 0x3F
+#define DPORT_SHARE_ROM_FO_S 2
+/* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: */
+#define DPORT_APP_ROM_FO (BIT(1))
+#define DPORT_APP_ROM_FO_M (BIT(1))
+#define DPORT_APP_ROM_FO_V 0x1
+#define DPORT_APP_ROM_FO_S 1
+/* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: */
+#define DPORT_PRO_ROM_FO (BIT(0))
+#define DPORT_PRO_ROM_FO_M (BIT(0))
+#define DPORT_PRO_ROM_FO_V 0x1
+#define DPORT_PRO_ROM_FO_S 0
+
+#define DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098)
+/* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_SRAM_PD_0 0xFFFFFFFF
+#define DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S))
+#define DPORT_SRAM_PD_0_V 0xFFFFFFFF
+#define DPORT_SRAM_PD_0_S 0
+
+#define DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C)
+/* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define DPORT_SRAM_PD_1 (BIT(0))
+#define DPORT_SRAM_PD_1_M (BIT(0))
+#define DPORT_SRAM_PD_1_V 0x1
+#define DPORT_SRAM_PD_1_S 0
+
+#define DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0)
+/* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define DPORT_SRAM_FO_0 0xFFFFFFFF
+#define DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S))
+#define DPORT_SRAM_FO_0_V 0xFFFFFFFF
+#define DPORT_SRAM_FO_0_S 0
+
+#define DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4)
+/* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: */
+#define DPORT_SRAM_FO_1 (BIT(0))
+#define DPORT_SRAM_FO_1_M (BIT(0))
+#define DPORT_SRAM_FO_1_V 0x1
+#define DPORT_SRAM_FO_1_S 0
+
+#define DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8)
+/* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */
+/*description: */
+#define DPORT_MAC_DUMP_MODE 0x00000003
+#define DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S))
+#define DPORT_MAC_DUMP_MODE_V 0x3
+#define DPORT_MAC_DUMP_MODE_S 5
+/* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_MASK_AHB (BIT(4))
+#define DPORT_MASK_AHB_M (BIT(4))
+#define DPORT_MASK_AHB_V 0x1
+#define DPORT_MASK_AHB_S 4
+/* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_MASK_APP_DRAM (BIT(3))
+#define DPORT_MASK_APP_DRAM_M (BIT(3))
+#define DPORT_MASK_APP_DRAM_V 0x1
+#define DPORT_MASK_APP_DRAM_S 3
+/* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_MASK_PRO_DRAM (BIT(2))
+#define DPORT_MASK_PRO_DRAM_M (BIT(2))
+#define DPORT_MASK_PRO_DRAM_V 0x1
+#define DPORT_MASK_PRO_DRAM_S 2
+/* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_MASK_APP_IRAM (BIT(1))
+#define DPORT_MASK_APP_IRAM_M (BIT(1))
+#define DPORT_MASK_APP_IRAM_V 0x1
+#define DPORT_MASK_APP_IRAM_S 1
+/* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_MASK_PRO_IRAM (BIT(0))
+#define DPORT_MASK_PRO_IRAM_M (BIT(0))
+#define DPORT_MASK_PRO_IRAM_V 0x1
+#define DPORT_MASK_PRO_IRAM_S 0
+
+#define DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC)
+/* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_TAG_PD (BIT(9))
+#define DPORT_APP_CACHE_TAG_PD_M (BIT(9))
+#define DPORT_APP_CACHE_TAG_PD_V 0x1
+#define DPORT_APP_CACHE_TAG_PD_S 9
+/* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8))
+#define DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8))
+#define DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1
+#define DPORT_APP_CACHE_TAG_FORCE_ON_S 8
+/* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_TAG_PD (BIT(1))
+#define DPORT_PRO_CACHE_TAG_PD_M (BIT(1))
+#define DPORT_PRO_CACHE_TAG_PD_V 0x1
+#define DPORT_PRO_CACHE_TAG_PD_S 1
+/* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0))
+#define DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0))
+#define DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1
+#define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0
+
+#define DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0)
+/* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */
+/*description: */
+#define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007
+#define DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S))
+#define DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7
+#define DPORT_AHB_LITE_SDHOST_PID_REG_S 11
+/* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10))
+#define DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10))
+#define DPORT_AHB_LITE_MASK_APPDPORT_V 0x1
+#define DPORT_AHB_LITE_MASK_APPDPORT_S 10
+/* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9))
+#define DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9))
+#define DPORT_AHB_LITE_MASK_PRODPORT_V 0x1
+#define DPORT_AHB_LITE_MASK_PRODPORT_S 9
+/* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHB_LITE_MASK_SDIO (BIT(8))
+#define DPORT_AHB_LITE_MASK_SDIO_M (BIT(8))
+#define DPORT_AHB_LITE_MASK_SDIO_V 0x1
+#define DPORT_AHB_LITE_MASK_SDIO_S 8
+/* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHB_LITE_MASK_APP (BIT(4))
+#define DPORT_AHB_LITE_MASK_APP_M (BIT(4))
+#define DPORT_AHB_LITE_MASK_APP_V 0x1
+#define DPORT_AHB_LITE_MASK_APP_S 4
+/* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHB_LITE_MASK_PRO (BIT(0))
+#define DPORT_AHB_LITE_MASK_PRO_M (BIT(0))
+#define DPORT_AHB_LITE_MASK_PRO_V 0x1
+#define DPORT_AHB_LITE_MASK_PRO_S 0
+
+#define DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4)
+/* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF
+#define DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S))
+#define DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF
+#define DPORT_AHB_ACCESS_GRANT_0_S 0
+
+#define DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8)
+/* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */
+/*description: */
+#define DPORT_AHB_ACCESS_GRANT_1 0x000001FF
+#define DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S))
+#define DPORT_AHB_ACCESS_GRANT_1_V 0x1FF
+#define DPORT_AHB_ACCESS_GRANT_1_S 0
+
+#define DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC)
+/* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define DPORT_LINK_DEVICE_SEL 0x000000FF
+#define DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S))
+#define DPORT_LINK_DEVICE_SEL_V 0xFF
+#define DPORT_LINK_DEVICE_SEL_S 8
+/* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define DPORT_PERI_IO_SWAP 0x000000FF
+#define DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S))
+#define DPORT_PERI_IO_SWAP_V 0xFF
+#define DPORT_PERI_IO_SWAP_S 0
+
+#define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0)
+/* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */
+/*description: */
+#define DPORT_PERIP_CLK_EN 0xFFFFFFFF
+#define DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S))
+#define DPORT_PERIP_CLK_EN_V 0xFFFFFFFF
+#define DPORT_PERIP_CLK_EN_S 0
+
+#define DPORT_PWM3_CLK_EN (BIT(26))
+#define DPORT_PWM2_CLK_EN (BIT(25))
+#define DPORT_UART_MEM_CLK_EN (BIT(24))
+#define DPORT_UART2_CLK_EN (BIT(23))
+#define DPORT_SPI_DMA_CLK_EN (BIT(22))
+#define DPORT_I2S1_CLK_EN (BIT(21))
+#define DPORT_PWM1_CLK_EN (BIT(20))
+#define DPORT_CAN_CLK_EN (BIT(19))
+#define DPORT_I2C_EXT1_CLK_EN (BIT(18))
+#define DPORT_PWM0_CLK_EN (BIT(17))
+#define DPORT_SPI_CLK_EN (BIT(16))
+#define DPORT_TIMERGROUP1_CLK_EN (BIT(15))
+#define DPORT_EFUSE_CLK_EN (BIT(14))
+#define DPORT_TIMERGROUP_CLK_EN (BIT(13))
+#define DPORT_UHCI1_CLK_EN (BIT(12))
+#define DPORT_LEDC_CLK_EN (BIT(11))
+#define DPORT_PCNT_CLK_EN (BIT(10))
+#define DPORT_RMT_CLK_EN (BIT(9))
+#define DPORT_UHCI0_CLK_EN (BIT(8))
+#define DPORT_I2C_EXT0_CLK_EN (BIT(7))
+#define DPORT_SPI_CLK_EN_2 (BIT(6))
+#define DPORT_UART1_CLK_EN (BIT(5))
+#define DPORT_I2S0_CLK_EN (BIT(4))
+#define DPORT_WDG_CLK_EN (BIT(3))
+#define DPORT_UART_CLK_EN (BIT(2))
+#define DPORT_SPI_CLK_EN_1 (BIT(1))
+#define DPORT_TIMERS_CLK_EN (BIT(0))
+#define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4)
+/* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PERIP_RST 0xFFFFFFFF
+#define DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S))
+#define DPORT_PERIP_RST_V 0xFFFFFFFF
+#define DPORT_PERIP_RST_S 0
+#define DPORT_PWM3_RST (BIT(26))
+#define DPORT_PWM2_RST (BIT(25))
+#define DPORT_UART_MEM_RST (BIT(24))
+#define DPORT_UART2_RST (BIT(23))
+#define DPORT_SPI_DMA_RST (BIT(22))
+#define DPORT_I2S1_RST (BIT(21))
+#define DPORT_PWM1_RST (BIT(20))
+#define DPORT_CAN_RST (BIT(19))
+#define DPORT_I2C_EXT1_RST (BIT(18))
+#define DPORT_PWM0_RST (BIT(17))
+#define DPORT_SPI_RST (BIT(16))
+#define DPORT_TIMERGROUP1_RST (BIT(15))
+#define DPORT_EFUSE_RST (BIT(14))
+#define DPORT_TIMERGROUP_RST (BIT(13))
+#define DPORT_UHCI1_RST (BIT(12))
+#define DPORT_LEDC_RST (BIT(11))
+#define DPORT_PCNT_RST (BIT(10))
+#define DPORT_RMT_RST (BIT(9))
+#define DPORT_UHCI0_RST (BIT(8))
+#define DPORT_I2C_EXT0_RST (BIT(7))
+#define DPORT_SPI_RST_2 (BIT(6))
+#define DPORT_UART1_RST (BIT(5))
+#define DPORT_I2S0_RST (BIT(4))
+#define DPORT_WDG_RST (BIT(3))
+#define DPORT_UART_RST (BIT(2))
+#define DPORT_SPI_RST_1 (BIT(1))
+#define DPORT_TIMERS_RST (BIT(0))
+#define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8)
+/* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI_DECRYPT_ENABLE (BIT(12))
+#define DPORT_SPI_DECRYPT_ENABLE_M (BIT(12))
+#define DPORT_SPI_DECRYPT_ENABLE_V 0x1
+#define DPORT_SPI_DECRYPT_ENABLE_S 12
+/* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI_ENCRYPT_ENABLE (BIT(8))
+#define DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8))
+#define DPORT_SPI_ENCRYPT_ENABLE_V 0x1
+#define DPORT_SPI_ENCRYPT_ENABLE_S 8
+/* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SLAVE_SPI_MASK_APP (BIT(4))
+#define DPORT_SLAVE_SPI_MASK_APP_M (BIT(4))
+#define DPORT_SLAVE_SPI_MASK_APP_V 0x1
+#define DPORT_SLAVE_SPI_MASK_APP_S 4
+/* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SLAVE_SPI_MASK_PRO (BIT(0))
+#define DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0))
+#define DPORT_SLAVE_SPI_MASK_PRO_V 0x1
+#define DPORT_SLAVE_SPI_MASK_PRO_S 0
+
+#define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC)
+/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define DPORT_WIFI_CLK_EN 0xFFFFFFFF
+#define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S))
+#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF
+#define DPORT_WIFI_CLK_EN_S 0
+
+#define DPORT_WIFI_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0)
+/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_WIFI_RST 0xFFFFFFFF
+#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S))
+#define DPORT_WIFI_RST_V 0xFFFFFFFF
+#define DPORT_WIFI_RST_S 0
+
+#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4)
+/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_BTEXTWAKEUP_REQ (BIT(12))
+#define DPORT_BTEXTWAKEUP_REQ_M (BIT(12))
+#define DPORT_BTEXTWAKEUP_REQ_V 0x1
+#define DPORT_BTEXTWAKEUP_REQ_S 12
+/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
+/*description: */
+#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF
+#define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S))
+#define DPORT_BT_LPCK_DIV_NUM_V 0xFFF
+#define DPORT_BT_LPCK_DIV_NUM_S 0
+
+#define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8)
+/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LPCLK_SEL_XTAL32K (BIT(27))
+#define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27))
+#define DPORT_LPCLK_SEL_XTAL32K_V 0x1
+#define DPORT_LPCLK_SEL_XTAL32K_S 27
+/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LPCLK_SEL_XTAL (BIT(26))
+#define DPORT_LPCLK_SEL_XTAL_M (BIT(26))
+#define DPORT_LPCLK_SEL_XTAL_V 0x1
+#define DPORT_LPCLK_SEL_XTAL_S 26
+/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_LPCLK_SEL_8M (BIT(25))
+#define DPORT_LPCLK_SEL_8M_M (BIT(25))
+#define DPORT_LPCLK_SEL_8M_V 0x1
+#define DPORT_LPCLK_SEL_8M_S 25
+/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24))
+#define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24))
+#define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1
+#define DPORT_LPCLK_SEL_RTC_SLOW_S 24
+/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
+/*description: */
+#define DPORT_BT_LPCK_DIV_A 0x00000FFF
+#define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S))
+#define DPORT_BT_LPCK_DIV_A_V 0xFFF
+#define DPORT_BT_LPCK_DIV_A_S 12
+/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
+/*description: */
+#define DPORT_BT_LPCK_DIV_B 0x00000FFF
+#define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S))
+#define DPORT_BT_LPCK_DIV_B_V 0xFFF
+#define DPORT_BT_LPCK_DIV_B_S 0
+
+#define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC)
+/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_0_V 0x1
+#define DPORT_CPU_INTR_FROM_CPU_0_S 0
+
+#define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0)
+/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1
+#define DPORT_CPU_INTR_FROM_CPU_1_S 0
+
+#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4)
+/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1
+#define DPORT_CPU_INTR_FROM_CPU_2_S 0
+
+#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8)
+/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_3_V 0x1
+#define DPORT_CPU_INTR_FROM_CPU_3_S 0
+
+#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC)
+/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S))
+#define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_0_S 0
+
+#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0)
+/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S))
+#define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_1_S 0
+
+#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4)
+/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S))
+#define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_2_S 0
+
+#define DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8)
+/* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S))
+#define DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_0_S 0
+
+#define DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC)
+/* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S))
+#define DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_1_S 0
+
+#define DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100)
+/* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S))
+#define DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_2_S 0
+
+#define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104)
+/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_MAC_INTR_MAP 0x0000001F
+#define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S))
+#define DPORT_PRO_MAC_INTR_MAP_V 0x1F
+#define DPORT_PRO_MAC_INTR_MAP_S 0
+
+#define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108)
+/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_MAC_NMI_MAP 0x0000001F
+#define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S))
+#define DPORT_PRO_MAC_NMI_MAP_V 0x1F
+#define DPORT_PRO_MAC_NMI_MAP_S 0
+
+#define DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C)
+/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_BB_INT_MAP 0x0000001F
+#define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S))
+#define DPORT_PRO_BB_INT_MAP_V 0x1F
+#define DPORT_PRO_BB_INT_MAP_S 0
+
+#define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110)
+/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F
+#define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S))
+#define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F
+#define DPORT_PRO_BT_MAC_INT_MAP_S 0
+
+#define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114)
+/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F
+#define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S))
+#define DPORT_PRO_BT_BB_INT_MAP_V 0x1F
+#define DPORT_PRO_BT_BB_INT_MAP_S 0
+
+#define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118)
+/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F
+#define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S))
+#define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F
+#define DPORT_PRO_BT_BB_NMI_MAP_S 0
+
+#define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C)
+/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F
+#define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S))
+#define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F
+#define DPORT_PRO_RWBT_IRQ_MAP_S 0
+
+#define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120)
+/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F
+#define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S))
+#define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F
+#define DPORT_PRO_RWBLE_IRQ_MAP_S 0
+
+#define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124)
+/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F
+#define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S))
+#define DPORT_PRO_RWBT_NMI_MAP_V 0x1F
+#define DPORT_PRO_RWBT_NMI_MAP_S 0
+
+#define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128)
+/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F
+#define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S))
+#define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F
+#define DPORT_PRO_RWBLE_NMI_MAP_S 0
+
+#define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C)
+/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F
+#define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S))
+#define DPORT_PRO_SLC0_INTR_MAP_V 0x1F
+#define DPORT_PRO_SLC0_INTR_MAP_S 0
+
+#define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130)
+/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F
+#define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S))
+#define DPORT_PRO_SLC1_INTR_MAP_V 0x1F
+#define DPORT_PRO_SLC1_INTR_MAP_S 0
+
+#define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134)
+/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F
+#define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S))
+#define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F
+#define DPORT_PRO_UHCI0_INTR_MAP_S 0
+
+#define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138)
+/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F
+#define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S))
+#define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F
+#define DPORT_PRO_UHCI1_INTR_MAP_S 0
+
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C)
+/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0
+
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140)
+/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0
+
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144)
+/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0
+
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148)
+/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0
+
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C)
+/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0
+
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150)
+/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0
+
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154)
+/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0
+
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158)
+/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0
+
+#define DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C)
+/* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S))
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0
+
+#define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160)
+/* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S))
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
+
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164)
+/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S))
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0
+
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168)
+/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S))
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0
+
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C)
+/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S))
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0
+
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170)
+/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S))
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0
+
+#define DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174)
+/* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F
+#define DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S))
+#define DPORT_PRO_SPI_INTR_0_MAP_V 0x1F
+#define DPORT_PRO_SPI_INTR_0_MAP_S 0
+
+#define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178)
+/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F
+#define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S))
+#define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F
+#define DPORT_PRO_SPI_INTR_1_MAP_S 0
+
+#define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C)
+/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F
+#define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S))
+#define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F
+#define DPORT_PRO_SPI_INTR_2_MAP_S 0
+
+#define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180)
+/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F
+#define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S))
+#define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F
+#define DPORT_PRO_SPI_INTR_3_MAP_S 0
+
+#define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184)
+/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_I2S0_INT_MAP 0x0000001F
+#define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S))
+#define DPORT_PRO_I2S0_INT_MAP_V 0x1F
+#define DPORT_PRO_I2S0_INT_MAP_S 0
+
+#define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188)
+/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_I2S1_INT_MAP 0x0000001F
+#define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S))
+#define DPORT_PRO_I2S1_INT_MAP_V 0x1F
+#define DPORT_PRO_I2S1_INT_MAP_S 0
+
+#define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C)
+/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UART_INTR_MAP 0x0000001F
+#define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S))
+#define DPORT_PRO_UART_INTR_MAP_V 0x1F
+#define DPORT_PRO_UART_INTR_MAP_S 0
+
+#define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190)
+/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UART1_INTR_MAP 0x0000001F
+#define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S))
+#define DPORT_PRO_UART1_INTR_MAP_V 0x1F
+#define DPORT_PRO_UART1_INTR_MAP_S 0
+
+#define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194)
+/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UART2_INTR_MAP 0x0000001F
+#define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S))
+#define DPORT_PRO_UART2_INTR_MAP_V 0x1F
+#define DPORT_PRO_UART2_INTR_MAP_S 0
+
+#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198)
+/* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F
+#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S))
+#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F
+#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0
+
+#define DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C)
+/* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_EMAC_INT_MAP 0x0000001F
+#define DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S))
+#define DPORT_PRO_EMAC_INT_MAP_V 0x1F
+#define DPORT_PRO_EMAC_INT_MAP_S 0
+
+#define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0)
+/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F
+#define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S))
+#define DPORT_PRO_PWM0_INTR_MAP_V 0x1F
+#define DPORT_PRO_PWM0_INTR_MAP_S 0
+
+#define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4)
+/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F
+#define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S))
+#define DPORT_PRO_PWM1_INTR_MAP_V 0x1F
+#define DPORT_PRO_PWM1_INTR_MAP_S 0
+
+#define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8)
+/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F
+#define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S))
+#define DPORT_PRO_PWM2_INTR_MAP_V 0x1F
+#define DPORT_PRO_PWM2_INTR_MAP_S 0
+
+#define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC)
+/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F
+#define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S))
+#define DPORT_PRO_PWM3_INTR_MAP_V 0x1F
+#define DPORT_PRO_PWM3_INTR_MAP_S 0
+
+#define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0)
+/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_LEDC_INT_MAP 0x0000001F
+#define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S))
+#define DPORT_PRO_LEDC_INT_MAP_V 0x1F
+#define DPORT_PRO_LEDC_INT_MAP_S 0
+
+#define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4)
+/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F
+#define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S))
+#define DPORT_PRO_EFUSE_INT_MAP_V 0x1F
+#define DPORT_PRO_EFUSE_INT_MAP_S 0
+
+#define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8)
+/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CAN_INT_MAP 0x0000001F
+#define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S))
+#define DPORT_PRO_CAN_INT_MAP_V 0x1F
+#define DPORT_PRO_CAN_INT_MAP_S 0
+
+#define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC)
+/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F
+#define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S))
+#define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F
+#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0
+
+#define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0)
+/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RMT_INTR_MAP 0x0000001F
+#define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S))
+#define DPORT_PRO_RMT_INTR_MAP_V 0x1F
+#define DPORT_PRO_RMT_INTR_MAP_S 0
+
+#define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4)
+/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F
+#define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S))
+#define DPORT_PRO_PCNT_INTR_MAP_V 0x1F
+#define DPORT_PRO_PCNT_INTR_MAP_S 0
+
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8)
+/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S))
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0
+
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC)
+/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S))
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0
+
+#define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0)
+/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RSA_INTR_MAP 0x0000001F
+#define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S))
+#define DPORT_PRO_RSA_INTR_MAP_V 0x1F
+#define DPORT_PRO_RSA_INTR_MAP_S 0
+
+#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4)
+/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F
+#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S))
+#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F
+#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0
+
+#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8)
+/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F
+#define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S))
+#define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F
+#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0
+
+#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC)
+/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F
+#define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S))
+#define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F
+#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0
+
+#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0)
+/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_WDG_INT_MAP 0x0000001F
+#define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S))
+#define DPORT_PRO_WDG_INT_MAP_V 0x1F
+#define DPORT_PRO_WDG_INT_MAP_S 0
+
+#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4)
+/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F
+#define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S))
+#define DPORT_PRO_TIMER_INT1_MAP_V 0x1F
+#define DPORT_PRO_TIMER_INT1_MAP_S 0
+
+#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8)
+/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F
+#define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S))
+#define DPORT_PRO_TIMER_INT2_MAP_V 0x1F
+#define DPORT_PRO_TIMER_INT2_MAP_S 0
+
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC)
+/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0
+
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0)
+/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0
+
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4)
+/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0
+
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8)
+/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0
+
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC)
+/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0
+
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200)
+/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0
+
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204)
+/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0
+
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208)
+/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0
+
+#define DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C)
+/* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F
+#define DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S))
+#define DPORT_PRO_MMU_IA_INT_MAP_V 0x1F
+#define DPORT_PRO_MMU_IA_INT_MAP_S 0
+
+#define DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210)
+/* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F
+#define DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S))
+#define DPORT_PRO_MPU_IA_INT_MAP_V 0x1F
+#define DPORT_PRO_MPU_IA_INT_MAP_S 0
+
+#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214)
+/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F
+#define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S))
+#define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F
+#define DPORT_PRO_CACHE_IA_INT_MAP_S 0
+
+#define DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218)
+/* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_MAC_INTR_MAP 0x0000001F
+#define DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S))
+#define DPORT_APP_MAC_INTR_MAP_V 0x1F
+#define DPORT_APP_MAC_INTR_MAP_S 0
+
+#define DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C)
+/* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_MAC_NMI_MAP 0x0000001F
+#define DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S))
+#define DPORT_APP_MAC_NMI_MAP_V 0x1F
+#define DPORT_APP_MAC_NMI_MAP_S 0
+
+#define DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220)
+/* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_BB_INT_MAP 0x0000001F
+#define DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S))
+#define DPORT_APP_BB_INT_MAP_V 0x1F
+#define DPORT_APP_BB_INT_MAP_S 0
+
+#define DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224)
+/* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_BT_MAC_INT_MAP 0x0000001F
+#define DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S))
+#define DPORT_APP_BT_MAC_INT_MAP_V 0x1F
+#define DPORT_APP_BT_MAC_INT_MAP_S 0
+
+#define DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228)
+/* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_BT_BB_INT_MAP 0x0000001F
+#define DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S))
+#define DPORT_APP_BT_BB_INT_MAP_V 0x1F
+#define DPORT_APP_BT_BB_INT_MAP_S 0
+
+#define DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C)
+/* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_BT_BB_NMI_MAP 0x0000001F
+#define DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S))
+#define DPORT_APP_BT_BB_NMI_MAP_V 0x1F
+#define DPORT_APP_BT_BB_NMI_MAP_S 0
+
+#define DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230)
+/* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_RWBT_IRQ_MAP 0x0000001F
+#define DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S))
+#define DPORT_APP_RWBT_IRQ_MAP_V 0x1F
+#define DPORT_APP_RWBT_IRQ_MAP_S 0
+
+#define DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234)
+/* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F
+#define DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S))
+#define DPORT_APP_RWBLE_IRQ_MAP_V 0x1F
+#define DPORT_APP_RWBLE_IRQ_MAP_S 0
+
+#define DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238)
+/* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_RWBT_NMI_MAP 0x0000001F
+#define DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S))
+#define DPORT_APP_RWBT_NMI_MAP_V 0x1F
+#define DPORT_APP_RWBT_NMI_MAP_S 0
+
+#define DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C)
+/* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_RWBLE_NMI_MAP 0x0000001F
+#define DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S))
+#define DPORT_APP_RWBLE_NMI_MAP_V 0x1F
+#define DPORT_APP_RWBLE_NMI_MAP_S 0
+
+#define DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240)
+/* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SLC0_INTR_MAP 0x0000001F
+#define DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S))
+#define DPORT_APP_SLC0_INTR_MAP_V 0x1F
+#define DPORT_APP_SLC0_INTR_MAP_S 0
+
+#define DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244)
+/* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SLC1_INTR_MAP 0x0000001F
+#define DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S))
+#define DPORT_APP_SLC1_INTR_MAP_V 0x1F
+#define DPORT_APP_SLC1_INTR_MAP_S 0
+
+#define DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248)
+/* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_UHCI0_INTR_MAP 0x0000001F
+#define DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S))
+#define DPORT_APP_UHCI0_INTR_MAP_V 0x1F
+#define DPORT_APP_UHCI0_INTR_MAP_S 0
+
+#define DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C)
+/* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_UHCI1_INTR_MAP 0x0000001F
+#define DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S))
+#define DPORT_APP_UHCI1_INTR_MAP_V 0x1F
+#define DPORT_APP_UHCI1_INTR_MAP_S 0
+
+#define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250)
+/* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S))
+#define DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F
+#define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0
+
+#define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254)
+/* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S))
+#define DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F
+#define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0
+
+#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258)
+/* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S))
+#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F
+#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0
+
+#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C)
+/* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S))
+#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F
+#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0
+
+#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260)
+/* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S))
+#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F
+#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0
+
+#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264)
+/* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S))
+#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F
+#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0
+
+#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268)
+/* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S))
+#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F
+#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0
+
+#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C)
+/* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S))
+#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F
+#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0
+
+#define DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270)
+/* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F
+#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S))
+#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F
+#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0
+
+#define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274)
+/* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F
+#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S))
+#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F
+#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0
+
+#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278)
+/* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
+#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S))
+#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
+#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0
+
+#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C)
+/* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
+#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S))
+#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
+#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0
+
+#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280)
+/* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
+#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S))
+#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
+#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0
+
+#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284)
+/* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
+#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S))
+#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
+#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0
+
+#define DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288)
+/* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SPI_INTR_0_MAP 0x0000001F
+#define DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S))
+#define DPORT_APP_SPI_INTR_0_MAP_V 0x1F
+#define DPORT_APP_SPI_INTR_0_MAP_S 0
+
+#define DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C)
+/* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SPI_INTR_1_MAP 0x0000001F
+#define DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S))
+#define DPORT_APP_SPI_INTR_1_MAP_V 0x1F
+#define DPORT_APP_SPI_INTR_1_MAP_S 0
+
+#define DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290)
+/* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SPI_INTR_2_MAP 0x0000001F
+#define DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S))
+#define DPORT_APP_SPI_INTR_2_MAP_V 0x1F
+#define DPORT_APP_SPI_INTR_2_MAP_S 0
+
+#define DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294)
+/* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SPI_INTR_3_MAP 0x0000001F
+#define DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S))
+#define DPORT_APP_SPI_INTR_3_MAP_V 0x1F
+#define DPORT_APP_SPI_INTR_3_MAP_S 0
+
+#define DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298)
+/* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_I2S0_INT_MAP 0x0000001F
+#define DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S))
+#define DPORT_APP_I2S0_INT_MAP_V 0x1F
+#define DPORT_APP_I2S0_INT_MAP_S 0
+
+#define DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C)
+/* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_I2S1_INT_MAP 0x0000001F
+#define DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S))
+#define DPORT_APP_I2S1_INT_MAP_V 0x1F
+#define DPORT_APP_I2S1_INT_MAP_S 0
+
+#define DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0)
+/* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_UART_INTR_MAP 0x0000001F
+#define DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S))
+#define DPORT_APP_UART_INTR_MAP_V 0x1F
+#define DPORT_APP_UART_INTR_MAP_S 0
+
+#define DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4)
+/* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_UART1_INTR_MAP 0x0000001F
+#define DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S))
+#define DPORT_APP_UART1_INTR_MAP_V 0x1F
+#define DPORT_APP_UART1_INTR_MAP_S 0
+
+#define DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8)
+/* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_UART2_INTR_MAP 0x0000001F
+#define DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S))
+#define DPORT_APP_UART2_INTR_MAP_V 0x1F
+#define DPORT_APP_UART2_INTR_MAP_S 0
+
+#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC)
+/* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F
+#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S))
+#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F
+#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0
+
+#define DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0)
+/* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_EMAC_INT_MAP 0x0000001F
+#define DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S))
+#define DPORT_APP_EMAC_INT_MAP_V 0x1F
+#define DPORT_APP_EMAC_INT_MAP_S 0
+
+#define DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4)
+/* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_PWM0_INTR_MAP 0x0000001F
+#define DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S))
+#define DPORT_APP_PWM0_INTR_MAP_V 0x1F
+#define DPORT_APP_PWM0_INTR_MAP_S 0
+
+#define DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8)
+/* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_PWM1_INTR_MAP 0x0000001F
+#define DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S))
+#define DPORT_APP_PWM1_INTR_MAP_V 0x1F
+#define DPORT_APP_PWM1_INTR_MAP_S 0
+
+#define DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC)
+/* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_PWM2_INTR_MAP 0x0000001F
+#define DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S))
+#define DPORT_APP_PWM2_INTR_MAP_V 0x1F
+#define DPORT_APP_PWM2_INTR_MAP_S 0
+
+#define DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0)
+/* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_PWM3_INTR_MAP 0x0000001F
+#define DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S))
+#define DPORT_APP_PWM3_INTR_MAP_V 0x1F
+#define DPORT_APP_PWM3_INTR_MAP_S 0
+
+#define DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4)
+/* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_LEDC_INT_MAP 0x0000001F
+#define DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S))
+#define DPORT_APP_LEDC_INT_MAP_V 0x1F
+#define DPORT_APP_LEDC_INT_MAP_S 0
+
+#define DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8)
+/* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_EFUSE_INT_MAP 0x0000001F
+#define DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S))
+#define DPORT_APP_EFUSE_INT_MAP_V 0x1F
+#define DPORT_APP_EFUSE_INT_MAP_S 0
+
+#define DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC)
+/* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_CAN_INT_MAP 0x0000001F
+#define DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S))
+#define DPORT_APP_CAN_INT_MAP_V 0x1F
+#define DPORT_APP_CAN_INT_MAP_S 0
+
+#define DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0)
+/* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F
+#define DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S))
+#define DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F
+#define DPORT_APP_RTC_CORE_INTR_MAP_S 0
+
+#define DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4)
+/* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_RMT_INTR_MAP 0x0000001F
+#define DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S))
+#define DPORT_APP_RMT_INTR_MAP_V 0x1F
+#define DPORT_APP_RMT_INTR_MAP_S 0
+
+#define DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8)
+/* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_PCNT_INTR_MAP 0x0000001F
+#define DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S))
+#define DPORT_APP_PCNT_INTR_MAP_V 0x1F
+#define DPORT_APP_PCNT_INTR_MAP_S 0
+
+#define DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC)
+/* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F
+#define DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S))
+#define DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F
+#define DPORT_APP_I2C_EXT0_INTR_MAP_S 0
+
+#define DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0)
+/* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F
+#define DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S))
+#define DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F
+#define DPORT_APP_I2C_EXT1_INTR_MAP_S 0
+
+#define DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4)
+/* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_RSA_INTR_MAP 0x0000001F
+#define DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S))
+#define DPORT_APP_RSA_INTR_MAP_V 0x1F
+#define DPORT_APP_RSA_INTR_MAP_S 0
+
+#define DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8)
+/* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F
+#define DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S))
+#define DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F
+#define DPORT_APP_SPI1_DMA_INT_MAP_S 0
+
+#define DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC)
+/* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F
+#define DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S))
+#define DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F
+#define DPORT_APP_SPI2_DMA_INT_MAP_S 0
+
+#define DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0)
+/* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F
+#define DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S))
+#define DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F
+#define DPORT_APP_SPI3_DMA_INT_MAP_S 0
+
+#define DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4)
+/* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_WDG_INT_MAP 0x0000001F
+#define DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S))
+#define DPORT_APP_WDG_INT_MAP_V 0x1F
+#define DPORT_APP_WDG_INT_MAP_S 0
+
+#define DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8)
+/* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TIMER_INT1_MAP 0x0000001F
+#define DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S))
+#define DPORT_APP_TIMER_INT1_MAP_V 0x1F
+#define DPORT_APP_TIMER_INT1_MAP_S 0
+
+#define DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC)
+/* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TIMER_INT2_MAP 0x0000001F
+#define DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S))
+#define DPORT_APP_TIMER_INT2_MAP_V 0x1F
+#define DPORT_APP_TIMER_INT2_MAP_S 0
+
+#define DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300)
+/* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S))
+#define DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F
+#define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0
+
+#define DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304)
+/* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S))
+#define DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F
+#define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0
+
+#define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308)
+/* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S))
+#define DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F
+#define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0
+
+#define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C)
+/* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S))
+#define DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F
+#define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0
+
+#define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310)
+/* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S))
+#define DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F
+#define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0
+
+#define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314)
+/* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S))
+#define DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F
+#define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0
+
+#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318)
+/* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S))
+#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F
+#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0
+
+#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C)
+/* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S))
+#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F
+#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0
+
+#define DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320)
+/* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_MMU_IA_INT_MAP 0x0000001F
+#define DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S))
+#define DPORT_APP_MMU_IA_INT_MAP_V 0x1F
+#define DPORT_APP_MMU_IA_INT_MAP_S 0
+
+#define DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324)
+/* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_MPU_IA_INT_MAP 0x0000001F
+#define DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S))
+#define DPORT_APP_MPU_IA_INT_MAP_V 0x1F
+#define DPORT_APP_MPU_IA_INT_MAP_S 0
+
+#define DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328)
+/* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F
+#define DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S))
+#define DPORT_APP_CACHE_IA_INT_MAP_V 0x1F
+#define DPORT_APP_CACHE_IA_INT_MAP_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C)
+/* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S))
+#define DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_UART_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330)
+/* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S))
+#define DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334)
+/* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S))
+#define DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338)
+/* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S))
+#define DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C)
+/* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S))
+#define DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340)
+/* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S))
+#define DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_FE_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344)
+/* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S))
+#define DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348)
+/* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S))
+#define DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C)
+/* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S))
+#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350)
+/* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S))
+#define DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354)
+/* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S))
+#define DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358)
+/* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S))
+#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C)
+/* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S))
+#define DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360)
+/* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S))
+#define DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364)
+/* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S))
+#define DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368)
+/* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S))
+#define DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C)
+/* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S))
+#define DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_BT_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370)
+/* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S))
+#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374)
+/* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S))
+#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378)
+/* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S))
+#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C)
+/* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S))
+#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380)
+/* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S))
+#define DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384)
+/* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S))
+#define DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388)
+/* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S))
+#define DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C)
+/* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S))
+#define DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390)
+/* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S))
+#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394)
+/* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S))
+#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398)
+/* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S))
+#define DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_BB_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C)
+/* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S))
+#define DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0)
+/* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S))
+#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4)
+/* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S))
+#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8)
+/* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S))
+#define DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC)
+/* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S))
+#define DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0)
+/* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S))
+#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4)
+/* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S))
+#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8)
+/* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S))
+#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC)
+/* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S))
+#define DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0)
+/* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S))
+#define DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4)
+/* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S))
+#define DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8)
+/* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S))
+#define DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC)
+/* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S))
+#define DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0)
+/* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S))
+#define DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4)
+/* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S))
+#define DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8)
+/* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S))
+#define DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC)
+/* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S))
+#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0)
+/* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S))
+#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4)
+/* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S))
+#define DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F
+#define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0
+
+#define DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8)
+/* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */
+/*description: */
+#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F
+#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S))
+#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF
+#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26
+/* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */
+/*description: */
+#define DPORT_INTERNAL_SRAM_IA 0x00000FFF
+#define DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S))
+#define DPORT_INTERNAL_SRAM_IA_V 0xFFF
+#define DPORT_INTERNAL_SRAM_IA_S 14
+/* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */
+/*description: */
+#define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F
+#define DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S))
+#define DPORT_INTERNAL_SRAM_MMU_AD_V 0xF
+#define DPORT_INTERNAL_SRAM_MMU_AD_S 10
+/* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */
+/*description: */
+#define DPORT_SHARE_ROM_IA 0x0000000F
+#define DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S))
+#define DPORT_SHARE_ROM_IA_V 0xF
+#define DPORT_SHARE_ROM_IA_S 6
+/* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_SHARE_ROM_MPU_AD 0x00000003
+#define DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S))
+#define DPORT_SHARE_ROM_MPU_AD_V 0x3
+#define DPORT_SHARE_ROM_MPU_AD_S 4
+/* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_ROM_IA (BIT(3))
+#define DPORT_APP_ROM_IA_M (BIT(3))
+#define DPORT_APP_ROM_IA_V 0x1
+#define DPORT_APP_ROM_IA_S 3
+/* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_ROM_MPU_AD (BIT(2))
+#define DPORT_APP_ROM_MPU_AD_M (BIT(2))
+#define DPORT_APP_ROM_MPU_AD_V 0x1
+#define DPORT_APP_ROM_MPU_AD_S 2
+/* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ROM_IA (BIT(1))
+#define DPORT_PRO_ROM_IA_M (BIT(1))
+#define DPORT_PRO_ROM_IA_V 0x1
+#define DPORT_PRO_ROM_IA_S 1
+/* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ROM_MPU_AD (BIT(0))
+#define DPORT_PRO_ROM_MPU_AD_M (BIT(0))
+#define DPORT_PRO_ROM_MPU_AD_V 0x1
+#define DPORT_PRO_ROM_MPU_AD_S 0
+
+#define DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC)
+/* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHBLITE_IA (BIT(10))
+#define DPORT_AHBLITE_IA_M (BIT(10))
+#define DPORT_AHBLITE_IA_V 0x1
+#define DPORT_AHBLITE_IA_S 10
+/* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHBLITE_ACCESS_DENY (BIT(9))
+#define DPORT_AHBLITE_ACCESS_DENY_M (BIT(9))
+#define DPORT_AHBLITE_ACCESS_DENY_V 0x1
+#define DPORT_AHBLITE_ACCESS_DENY_S 9
+/* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AHB_ACCESS_DENY (BIT(8))
+#define DPORT_AHB_ACCESS_DENY_M (BIT(8))
+#define DPORT_AHB_ACCESS_DENY_V 0x1
+#define DPORT_AHB_ACCESS_DENY_S 8
+/* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_PIDGEN_IA 0x00000003
+#define DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S))
+#define DPORT_PIDGEN_IA_V 0x3
+#define DPORT_PIDGEN_IA_S 6
+/* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_ARB_IA 0x00000003
+#define DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S))
+#define DPORT_ARB_IA_V 0x3
+#define DPORT_ARB_IA_S 4
+/* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F
+#define DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S))
+#define DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF
+#define DPORT_INTERNAL_SRAM_MMU_MISS_S 0
+
+#define DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0)
+/* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_RX_END (BIT(23))
+#define DPORT_PRO_RX_END_M (BIT(23))
+#define DPORT_PRO_RX_END_V 0x1
+#define DPORT_PRO_RX_END_S 23
+/* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_SLAVE_WDATA_V (BIT(22))
+#define DPORT_PRO_SLAVE_WDATA_V_M (BIT(22))
+#define DPORT_PRO_SLAVE_WDATA_V_V 0x1
+#define DPORT_PRO_SLAVE_WDATA_V_S 22
+/* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_SLAVE_WR (BIT(21))
+#define DPORT_PRO_SLAVE_WR_M (BIT(21))
+#define DPORT_PRO_SLAVE_WR_V 0x1
+#define DPORT_PRO_SLAVE_WR_S 21
+/* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_TX_END (BIT(20))
+#define DPORT_PRO_TX_END_M (BIT(20))
+#define DPORT_PRO_TX_END_V 0x1
+#define DPORT_PRO_TX_END_S 20
+/* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_WR_BAK_TO_READ (BIT(19))
+#define DPORT_PRO_WR_BAK_TO_READ_M (BIT(19))
+#define DPORT_PRO_WR_BAK_TO_READ_V 0x1
+#define DPORT_PRO_WR_BAK_TO_READ_S 19
+/* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_STATE 0x00000FFF
+#define DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S))
+#define DPORT_PRO_CACHE_STATE_V 0xFFF
+#define DPORT_PRO_CACHE_STATE_S 7
+/* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_IA 0x0000003F
+#define DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S))
+#define DPORT_PRO_CACHE_IA_V 0x3F
+#define DPORT_PRO_CACHE_IA_S 1
+/* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MMU_IA (BIT(0))
+#define DPORT_PRO_CACHE_MMU_IA_M (BIT(0))
+#define DPORT_PRO_CACHE_MMU_IA_V 0x1
+#define DPORT_PRO_CACHE_MMU_IA_S 0
+
+#define DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4)
+/* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF
+#define DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S))
+#define DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF
+#define DPORT_PRO_CTAG_RAM_RDATA_S 0
+
+#define DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8)
+/* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_VADDR 0x07FFFFFF
+#define DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S))
+#define DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF
+#define DPORT_PRO_CACHE_VADDR_S 0
+
+#define DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC)
+/* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15))
+#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15))
+#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1
+#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15
+/* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F
+#define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S))
+#define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F
+#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9
+/* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define DPORT_PRO_MMU_RDATA 0x000001FF
+#define DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S))
+#define DPORT_PRO_MMU_RDATA_V 0x1FF
+#define DPORT_PRO_MMU_RDATA_S 0
+
+#define DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400)
+/* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF
+#define DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S))
+#define DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF
+#define DPORT_PRO_DRAM1ADDR0_IA_S 0
+
+#define DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404)
+/* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF
+#define DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S))
+#define DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF
+#define DPORT_PRO_DROM0ADDR0_IA_S 0
+
+#define DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408)
+/* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF
+#define DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S))
+#define DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF
+#define DPORT_PRO_IRAM0ADDR_IA_S 0
+
+#define DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C)
+/* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF
+#define DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S))
+#define DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF
+#define DPORT_PRO_IRAM1ADDR_IA_S 0
+
+#define DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410)
+/* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF
+#define DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S))
+#define DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF
+#define DPORT_PRO_IROM0ADDR_IA_S 0
+
+#define DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414)
+/* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF
+#define DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S))
+#define DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF
+#define DPORT_PRO_OPSDRAMADDR_IA_S 0
+
+#define DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418)
+/* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_RX_END (BIT(23))
+#define DPORT_APP_RX_END_M (BIT(23))
+#define DPORT_APP_RX_END_V 0x1
+#define DPORT_APP_RX_END_S 23
+/* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_SLAVE_WDATA_V (BIT(22))
+#define DPORT_APP_SLAVE_WDATA_V_M (BIT(22))
+#define DPORT_APP_SLAVE_WDATA_V_V 0x1
+#define DPORT_APP_SLAVE_WDATA_V_S 22
+/* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_SLAVE_WR (BIT(21))
+#define DPORT_APP_SLAVE_WR_M (BIT(21))
+#define DPORT_APP_SLAVE_WR_V 0x1
+#define DPORT_APP_SLAVE_WR_S 21
+/* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_TX_END (BIT(20))
+#define DPORT_APP_TX_END_M (BIT(20))
+#define DPORT_APP_TX_END_V 0x1
+#define DPORT_APP_TX_END_S 20
+/* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_WR_BAK_TO_READ (BIT(19))
+#define DPORT_APP_WR_BAK_TO_READ_M (BIT(19))
+#define DPORT_APP_WR_BAK_TO_READ_V 0x1
+#define DPORT_APP_WR_BAK_TO_READ_S 19
+/* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_STATE 0x00000FFF
+#define DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S))
+#define DPORT_APP_CACHE_STATE_V 0xFFF
+#define DPORT_APP_CACHE_STATE_S 7
+/* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_IA 0x0000003F
+#define DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S))
+#define DPORT_APP_CACHE_IA_V 0x3F
+#define DPORT_APP_CACHE_IA_S 1
+/* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_MMU_IA (BIT(0))
+#define DPORT_APP_CACHE_MMU_IA_M (BIT(0))
+#define DPORT_APP_CACHE_MMU_IA_V 0x1
+#define DPORT_APP_CACHE_MMU_IA_S 0
+
+#define DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C)
+/* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF
+#define DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S))
+#define DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF
+#define DPORT_APP_CTAG_RAM_RDATA_S 0
+
+#define DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420)
+/* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_VADDR 0x07FFFFFF
+#define DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S))
+#define DPORT_APP_CACHE_VADDR_V 0x7FFFFFF
+#define DPORT_APP_CACHE_VADDR_S 0
+
+#define DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424)
+/* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15))
+#define DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15))
+#define DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1
+#define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15
+/* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */
+/*description: */
+#define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F
+#define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S))
+#define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F
+#define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9
+/* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define DPORT_APP_MMU_RDATA 0x000001FF
+#define DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S))
+#define DPORT_APP_MMU_RDATA_V 0x1FF
+#define DPORT_APP_MMU_RDATA_S 0
+
+#define DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428)
+/* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF
+#define DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S))
+#define DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF
+#define DPORT_APP_DRAM1ADDR0_IA_S 0
+
+#define DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C)
+/* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF
+#define DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S))
+#define DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF
+#define DPORT_APP_DROM0ADDR0_IA_S 0
+
+#define DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430)
+/* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF
+#define DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S))
+#define DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF
+#define DPORT_APP_IRAM0ADDR_IA_S 0
+
+#define DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434)
+/* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF
+#define DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S))
+#define DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF
+#define DPORT_APP_IRAM1ADDR_IA_S 0
+
+#define DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438)
+/* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_APP_IROM0ADDR_IA 0x000FFFFF
+#define DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S))
+#define DPORT_APP_IROM0ADDR_IA_V 0xFFFFF
+#define DPORT_APP_IROM0ADDR_IA_S 0
+
+#define DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C)
+/* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF
+#define DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S))
+#define DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF
+#define DPORT_APP_OPSDRAMADDR_IA_S 0
+
+#define DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440)
+/* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8))
+#define DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8))
+#define DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1
+#define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8
+/* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4))
+#define DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4))
+#define DPORT_PRO_CPU_RECORD_DISABLE_V 0x1
+#define DPORT_PRO_CPU_RECORD_DISABLE_S 4
+/* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0))
+#define DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0))
+#define DPORT_PRO_CPU_RECORD_ENABLE_V 0x1
+#define DPORT_PRO_CPU_RECORD_ENABLE_S 0
+
+#define DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444)
+/* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CPU_RECORDING (BIT(0))
+#define DPORT_PRO_CPU_RECORDING_M (BIT(0))
+#define DPORT_PRO_CPU_RECORDING_V 0x1
+#define DPORT_PRO_CPU_RECORDING_S 0
+
+#define DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448)
+/* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */
+/*description: */
+#define DPORT_RECORD_PRO_PID 0x00000007
+#define DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S))
+#define DPORT_RECORD_PRO_PID_V 0x7
+#define DPORT_RECORD_PRO_PID_S 0
+
+#define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C)
+/* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S))
+#define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGINST_S 0
+
+#define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450)
+/* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF
+#define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S))
+#define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF
+#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0
+
+#define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454)
+/* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S))
+#define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGDATA_S 0
+
+#define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458)
+/* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S))
+#define DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGPC_S 0
+
+#define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C)
+/* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S))
+#define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0
+
+#define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460)
+/* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S))
+#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0
+
+#define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464)
+/* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S))
+#define DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0
+
+#define DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468)
+/* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8))
+#define DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8))
+#define DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1
+#define DPORT_APP_CPU_PDEBUG_ENABLE_S 8
+/* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CPU_RECORD_DISABLE (BIT(4))
+#define DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4))
+#define DPORT_APP_CPU_RECORD_DISABLE_V 0x1
+#define DPORT_APP_CPU_RECORD_DISABLE_S 4
+/* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CPU_RECORD_ENABLE (BIT(0))
+#define DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0))
+#define DPORT_APP_CPU_RECORD_ENABLE_V 0x1
+#define DPORT_APP_CPU_RECORD_ENABLE_S 0
+
+#define DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C)
+/* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APP_CPU_RECORDING (BIT(0))
+#define DPORT_APP_CPU_RECORDING_M (BIT(0))
+#define DPORT_APP_CPU_RECORDING_V 0x1
+#define DPORT_APP_CPU_RECORDING_S 0
+
+#define DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470)
+/* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */
+/*description: */
+#define DPORT_RECORD_APP_PID 0x00000007
+#define DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S))
+#define DPORT_RECORD_APP_PID_V 0x7
+#define DPORT_RECORD_APP_PID_S 0
+
+#define DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474)
+/* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S))
+#define DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGINST_S 0
+
+#define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478)
+/* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF
+#define DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S))
+#define DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF
+#define DPORT_RECORD_APP_PDEBUGSTATUS_S 0
+
+#define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C)
+/* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S))
+#define DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGDATA_S 0
+
+#define DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480)
+/* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S))
+#define DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGPC_S 0
+
+#define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484)
+/* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S))
+#define DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0
+
+#define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488)
+/* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S))
+#define DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0
+
+#define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C)
+/* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S))
+#define DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0
+
+#define DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490)
+/* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_RSA_PD (BIT(0))
+#define DPORT_RSA_PD_M (BIT(0))
+#define DPORT_RSA_PD_V 0x1
+#define DPORT_RSA_PD_S 0
+
+#define DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494)
+/* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_ROM_MPU_TABLE0 0x00000003
+#define DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S))
+#define DPORT_ROM_MPU_TABLE0_V 0x3
+#define DPORT_ROM_MPU_TABLE0_S 0
+
+#define DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498)
+/* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_ROM_MPU_TABLE1 0x00000003
+#define DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S))
+#define DPORT_ROM_MPU_TABLE1_V 0x3
+#define DPORT_ROM_MPU_TABLE1_S 0
+
+#define DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C)
+/* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_ROM_MPU_TABLE2 0x00000003
+#define DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S))
+#define DPORT_ROM_MPU_TABLE2_V 0x3
+#define DPORT_ROM_MPU_TABLE2_S 0
+
+#define DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0)
+/* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_ROM_MPU_TABLE3 0x00000003
+#define DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S))
+#define DPORT_ROM_MPU_TABLE3_V 0x3
+#define DPORT_ROM_MPU_TABLE3_S 0
+
+#define DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4)
+/* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE0 0x00000003
+#define DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S))
+#define DPORT_SHROM_MPU_TABLE0_V 0x3
+#define DPORT_SHROM_MPU_TABLE0_S 0
+
+#define DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8)
+/* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE1 0x00000003
+#define DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S))
+#define DPORT_SHROM_MPU_TABLE1_V 0x3
+#define DPORT_SHROM_MPU_TABLE1_S 0
+
+#define DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC)
+/* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE2 0x00000003
+#define DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S))
+#define DPORT_SHROM_MPU_TABLE2_V 0x3
+#define DPORT_SHROM_MPU_TABLE2_S 0
+
+#define DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0)
+/* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE3 0x00000003
+#define DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S))
+#define DPORT_SHROM_MPU_TABLE3_V 0x3
+#define DPORT_SHROM_MPU_TABLE3_S 0
+
+#define DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4)
+/* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE4 0x00000003
+#define DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S))
+#define DPORT_SHROM_MPU_TABLE4_V 0x3
+#define DPORT_SHROM_MPU_TABLE4_S 0
+
+#define DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8)
+/* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE5 0x00000003
+#define DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S))
+#define DPORT_SHROM_MPU_TABLE5_V 0x3
+#define DPORT_SHROM_MPU_TABLE5_S 0
+
+#define DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC)
+/* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE6 0x00000003
+#define DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S))
+#define DPORT_SHROM_MPU_TABLE6_V 0x3
+#define DPORT_SHROM_MPU_TABLE6_S 0
+
+#define DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0)
+/* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE7 0x00000003
+#define DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S))
+#define DPORT_SHROM_MPU_TABLE7_V 0x3
+#define DPORT_SHROM_MPU_TABLE7_S 0
+
+#define DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4)
+/* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE8 0x00000003
+#define DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S))
+#define DPORT_SHROM_MPU_TABLE8_V 0x3
+#define DPORT_SHROM_MPU_TABLE8_S 0
+
+#define DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8)
+/* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE9 0x00000003
+#define DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S))
+#define DPORT_SHROM_MPU_TABLE9_V 0x3
+#define DPORT_SHROM_MPU_TABLE9_S 0
+
+#define DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC)
+/* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE10 0x00000003
+#define DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S))
+#define DPORT_SHROM_MPU_TABLE10_V 0x3
+#define DPORT_SHROM_MPU_TABLE10_S 0
+
+#define DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0)
+/* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE11 0x00000003
+#define DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S))
+#define DPORT_SHROM_MPU_TABLE11_V 0x3
+#define DPORT_SHROM_MPU_TABLE11_S 0
+
+#define DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4)
+/* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE12 0x00000003
+#define DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S))
+#define DPORT_SHROM_MPU_TABLE12_V 0x3
+#define DPORT_SHROM_MPU_TABLE12_S 0
+
+#define DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8)
+/* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE13 0x00000003
+#define DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S))
+#define DPORT_SHROM_MPU_TABLE13_V 0x3
+#define DPORT_SHROM_MPU_TABLE13_S 0
+
+#define DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC)
+/* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE14 0x00000003
+#define DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S))
+#define DPORT_SHROM_MPU_TABLE14_V 0x3
+#define DPORT_SHROM_MPU_TABLE14_S 0
+
+#define DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0)
+/* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE15 0x00000003
+#define DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S))
+#define DPORT_SHROM_MPU_TABLE15_V 0x3
+#define DPORT_SHROM_MPU_TABLE15_S 0
+
+#define DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4)
+/* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE16 0x00000003
+#define DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S))
+#define DPORT_SHROM_MPU_TABLE16_V 0x3
+#define DPORT_SHROM_MPU_TABLE16_S 0
+
+#define DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8)
+/* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE17 0x00000003
+#define DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S))
+#define DPORT_SHROM_MPU_TABLE17_V 0x3
+#define DPORT_SHROM_MPU_TABLE17_S 0
+
+#define DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC)
+/* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE18 0x00000003
+#define DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S))
+#define DPORT_SHROM_MPU_TABLE18_V 0x3
+#define DPORT_SHROM_MPU_TABLE18_S 0
+
+#define DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0)
+/* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE19 0x00000003
+#define DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S))
+#define DPORT_SHROM_MPU_TABLE19_V 0x3
+#define DPORT_SHROM_MPU_TABLE19_S 0
+
+#define DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4)
+/* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE20 0x00000003
+#define DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S))
+#define DPORT_SHROM_MPU_TABLE20_V 0x3
+#define DPORT_SHROM_MPU_TABLE20_S 0
+
+#define DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8)
+/* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE21 0x00000003
+#define DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S))
+#define DPORT_SHROM_MPU_TABLE21_V 0x3
+#define DPORT_SHROM_MPU_TABLE21_S 0
+
+#define DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC)
+/* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE22 0x00000003
+#define DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S))
+#define DPORT_SHROM_MPU_TABLE22_V 0x3
+#define DPORT_SHROM_MPU_TABLE22_S 0
+
+#define DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500)
+/* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: */
+#define DPORT_SHROM_MPU_TABLE23 0x00000003
+#define DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S))
+#define DPORT_SHROM_MPU_TABLE23_V 0x3
+#define DPORT_SHROM_MPU_TABLE23_S 0
+
+#define DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504)
+/* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */
+/*description: */
+#define DPORT_IMMU_TABLE0 0x0000007F
+#define DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S))
+#define DPORT_IMMU_TABLE0_V 0x7F
+#define DPORT_IMMU_TABLE0_S 0
+
+#define DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508)
+/* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
+/*description: */
+#define DPORT_IMMU_TABLE1 0x0000007F
+#define DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S))
+#define DPORT_IMMU_TABLE1_V 0x7F
+#define DPORT_IMMU_TABLE1_S 0
+
+#define DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C)
+/* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */
+/*description: */
+#define DPORT_IMMU_TABLE2 0x0000007F
+#define DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S))
+#define DPORT_IMMU_TABLE2_V 0x7F
+#define DPORT_IMMU_TABLE2_S 0
+
+#define DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510)
+/* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */
+/*description: */
+#define DPORT_IMMU_TABLE3 0x0000007F
+#define DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S))
+#define DPORT_IMMU_TABLE3_V 0x7F
+#define DPORT_IMMU_TABLE3_S 0
+
+#define DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514)
+/* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */
+/*description: */
+#define DPORT_IMMU_TABLE4 0x0000007F
+#define DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S))
+#define DPORT_IMMU_TABLE4_V 0x7F
+#define DPORT_IMMU_TABLE4_S 0
+
+#define DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518)
+/* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */
+/*description: */
+#define DPORT_IMMU_TABLE5 0x0000007F
+#define DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S))
+#define DPORT_IMMU_TABLE5_V 0x7F
+#define DPORT_IMMU_TABLE5_S 0
+
+#define DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C)
+/* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */
+/*description: */
+#define DPORT_IMMU_TABLE6 0x0000007F
+#define DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S))
+#define DPORT_IMMU_TABLE6_V 0x7F
+#define DPORT_IMMU_TABLE6_S 0
+
+#define DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520)
+/* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */
+/*description: */
+#define DPORT_IMMU_TABLE7 0x0000007F
+#define DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S))
+#define DPORT_IMMU_TABLE7_V 0x7F
+#define DPORT_IMMU_TABLE7_S 0
+
+#define DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524)
+/* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */
+/*description: */
+#define DPORT_IMMU_TABLE8 0x0000007F
+#define DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S))
+#define DPORT_IMMU_TABLE8_V 0x7F
+#define DPORT_IMMU_TABLE8_S 0
+
+#define DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528)
+/* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */
+/*description: */
+#define DPORT_IMMU_TABLE9 0x0000007F
+#define DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S))
+#define DPORT_IMMU_TABLE9_V 0x7F
+#define DPORT_IMMU_TABLE9_S 0
+
+#define DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C)
+/* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */
+/*description: */
+#define DPORT_IMMU_TABLE10 0x0000007F
+#define DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S))
+#define DPORT_IMMU_TABLE10_V 0x7F
+#define DPORT_IMMU_TABLE10_S 0
+
+#define DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530)
+/* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */
+/*description: */
+#define DPORT_IMMU_TABLE11 0x0000007F
+#define DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S))
+#define DPORT_IMMU_TABLE11_V 0x7F
+#define DPORT_IMMU_TABLE11_S 0
+
+#define DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534)
+/* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */
+/*description: */
+#define DPORT_IMMU_TABLE12 0x0000007F
+#define DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S))
+#define DPORT_IMMU_TABLE12_V 0x7F
+#define DPORT_IMMU_TABLE12_S 0
+
+#define DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538)
+/* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */
+/*description: */
+#define DPORT_IMMU_TABLE13 0x0000007F
+#define DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S))
+#define DPORT_IMMU_TABLE13_V 0x7F
+#define DPORT_IMMU_TABLE13_S 0
+
+#define DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C)
+/* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */
+/*description: */
+#define DPORT_IMMU_TABLE14 0x0000007F
+#define DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S))
+#define DPORT_IMMU_TABLE14_V 0x7F
+#define DPORT_IMMU_TABLE14_S 0
+
+#define DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540)
+/* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */
+/*description: */
+#define DPORT_IMMU_TABLE15 0x0000007F
+#define DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S))
+#define DPORT_IMMU_TABLE15_V 0x7F
+#define DPORT_IMMU_TABLE15_S 0
+
+#define DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544)
+/* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */
+/*description: */
+#define DPORT_DMMU_TABLE0 0x0000007F
+#define DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S))
+#define DPORT_DMMU_TABLE0_V 0x7F
+#define DPORT_DMMU_TABLE0_S 0
+
+#define DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548)
+/* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
+/*description: */
+#define DPORT_DMMU_TABLE1 0x0000007F
+#define DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S))
+#define DPORT_DMMU_TABLE1_V 0x7F
+#define DPORT_DMMU_TABLE1_S 0
+
+#define DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C)
+/* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */
+/*description: */
+#define DPORT_DMMU_TABLE2 0x0000007F
+#define DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S))
+#define DPORT_DMMU_TABLE2_V 0x7F
+#define DPORT_DMMU_TABLE2_S 0
+
+#define DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550)
+/* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */
+/*description: */
+#define DPORT_DMMU_TABLE3 0x0000007F
+#define DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S))
+#define DPORT_DMMU_TABLE3_V 0x7F
+#define DPORT_DMMU_TABLE3_S 0
+
+#define DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554)
+/* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */
+/*description: */
+#define DPORT_DMMU_TABLE4 0x0000007F
+#define DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S))
+#define DPORT_DMMU_TABLE4_V 0x7F
+#define DPORT_DMMU_TABLE4_S 0
+
+#define DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558)
+/* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */
+/*description: */
+#define DPORT_DMMU_TABLE5 0x0000007F
+#define DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S))
+#define DPORT_DMMU_TABLE5_V 0x7F
+#define DPORT_DMMU_TABLE5_S 0
+
+#define DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C)
+/* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */
+/*description: */
+#define DPORT_DMMU_TABLE6 0x0000007F
+#define DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S))
+#define DPORT_DMMU_TABLE6_V 0x7F
+#define DPORT_DMMU_TABLE6_S 0
+
+#define DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560)
+/* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */
+/*description: */
+#define DPORT_DMMU_TABLE7 0x0000007F
+#define DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S))
+#define DPORT_DMMU_TABLE7_V 0x7F
+#define DPORT_DMMU_TABLE7_S 0
+
+#define DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564)
+/* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */
+/*description: */
+#define DPORT_DMMU_TABLE8 0x0000007F
+#define DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S))
+#define DPORT_DMMU_TABLE8_V 0x7F
+#define DPORT_DMMU_TABLE8_S 0
+
+#define DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568)
+/* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */
+/*description: */
+#define DPORT_DMMU_TABLE9 0x0000007F
+#define DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S))
+#define DPORT_DMMU_TABLE9_V 0x7F
+#define DPORT_DMMU_TABLE9_S 0
+
+#define DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C)
+/* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */
+/*description: */
+#define DPORT_DMMU_TABLE10 0x0000007F
+#define DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S))
+#define DPORT_DMMU_TABLE10_V 0x7F
+#define DPORT_DMMU_TABLE10_S 0
+
+#define DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570)
+/* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */
+/*description: */
+#define DPORT_DMMU_TABLE11 0x0000007F
+#define DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S))
+#define DPORT_DMMU_TABLE11_V 0x7F
+#define DPORT_DMMU_TABLE11_S 0
+
+#define DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574)
+/* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */
+/*description: */
+#define DPORT_DMMU_TABLE12 0x0000007F
+#define DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S))
+#define DPORT_DMMU_TABLE12_V 0x7F
+#define DPORT_DMMU_TABLE12_S 0
+
+#define DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578)
+/* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */
+/*description: */
+#define DPORT_DMMU_TABLE13 0x0000007F
+#define DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S))
+#define DPORT_DMMU_TABLE13_V 0x7F
+#define DPORT_DMMU_TABLE13_S 0
+
+#define DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C)
+/* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */
+/*description: */
+#define DPORT_DMMU_TABLE14 0x0000007F
+#define DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S))
+#define DPORT_DMMU_TABLE14_V 0x7F
+#define DPORT_DMMU_TABLE14_S 0
+
+#define DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580)
+/* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */
+/*description: */
+#define DPORT_DMMU_TABLE15 0x0000007F
+#define DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S))
+#define DPORT_DMMU_TABLE15_V 0x7F
+#define DPORT_DMMU_TABLE15_S 0
+
+#define DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584)
+/* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0))
+#define DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0))
+#define DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1
+#define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0
+
+#define DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588)
+/* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define DPORT_PRO_INTRUSION_RECORD 0x0000000F
+#define DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S))
+#define DPORT_PRO_INTRUSION_RECORD_V 0xF
+#define DPORT_PRO_INTRUSION_RECORD_S 0
+
+#define DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C)
+/* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0))
+#define DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0))
+#define DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1
+#define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0
+
+#define DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590)
+/* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define DPORT_APP_INTRUSION_RECORD 0x0000000F
+#define DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S))
+#define DPORT_APP_INTRUSION_RECORD_V 0xF
+#define DPORT_APP_INTRUSION_RECORD_S 0
+
+#define DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594)
+/* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PBUS_MEM_FORCE_PD (BIT(3))
+#define DPORT_PBUS_MEM_FORCE_PD_M (BIT(3))
+#define DPORT_PBUS_MEM_FORCE_PD_V 0x1
+#define DPORT_PBUS_MEM_FORCE_PD_S 3
+/* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PBUS_MEM_FORCE_PU (BIT(2))
+#define DPORT_PBUS_MEM_FORCE_PU_M (BIT(2))
+#define DPORT_PBUS_MEM_FORCE_PU_V 0x1
+#define DPORT_PBUS_MEM_FORCE_PU_S 2
+/* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_AGC_MEM_FORCE_PD (BIT(1))
+#define DPORT_AGC_MEM_FORCE_PD_M (BIT(1))
+#define DPORT_AGC_MEM_FORCE_PD_V 0x1
+#define DPORT_AGC_MEM_FORCE_PD_S 1
+/* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_AGC_MEM_FORCE_PU (BIT(0))
+#define DPORT_AGC_MEM_FORCE_PU_M (BIT(0))
+#define DPORT_AGC_MEM_FORCE_PU_V 0x1
+#define DPORT_AGC_MEM_FORCE_PU_S 0
+
+#define DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598)
+/* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define DPORT_MMU_IA_INT_EN 0x00FFFFFF
+#define DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S))
+#define DPORT_MMU_IA_INT_EN_V 0xFFFFFF
+#define DPORT_MMU_IA_INT_EN_S 0
+
+#define DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C)
+/* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */
+/*description: */
+#define DPORT_MPU_IA_INT_EN 0x0001FFFF
+#define DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S))
+#define DPORT_MPU_IA_INT_EN_V 0x1FFFF
+#define DPORT_MPU_IA_INT_EN_S 0
+
+#define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0)
+/* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
+/*description: */
+#define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF
+#define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S))
+#define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF
+#define DPORT_CACHE_IA_INT_EN_S 0
+
+#define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4)
+/* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SW_BOOTLOADER_SEL (BIT(0))
+#define DPORT_SW_BOOTLOADER_SEL_M (BIT(0))
+#define DPORT_SW_BOOTLOADER_SEL_V 0x1
+#define DPORT_SW_BOOTLOADER_SEL_S 0
+
+#define DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8)
+/* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */
+/*description: */
+#define DPORT_SPI3_DMA_CHAN_SEL 0x00000003
+#define DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S))
+#define DPORT_SPI3_DMA_CHAN_SEL_V 0x3
+#define DPORT_SPI3_DMA_CHAN_SEL_S 4
+/* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */
+/*description: */
+#define DPORT_SPI2_DMA_CHAN_SEL 0x00000003
+#define DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S))
+#define DPORT_SPI2_DMA_CHAN_SEL_V 0x3
+#define DPORT_SPI2_DMA_CHAN_SEL_S 2
+/* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */
+/*description: */
+#define DPORT_SPI1_DMA_CHAN_SEL 0x00000003
+#define DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S))
+#define DPORT_SPI1_DMA_CHAN_SEL_V 0x3
+#define DPORT_SPI1_DMA_CHAN_SEL_S 0
+
+#define DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC)
+/* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_PRO_OUT_VECBASE_SEL 0x00000003
+#define DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S))
+#define DPORT_PRO_OUT_VECBASE_SEL_V 0x3
+#define DPORT_PRO_OUT_VECBASE_SEL_S 0
+
+#define DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0)
+/* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: */
+#define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF
+#define DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S))
+#define DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF
+#define DPORT_PRO_OUT_VECBASE_REG_S 0
+
+#define DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4)
+/* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_APP_OUT_VECBASE_SEL 0x00000003
+#define DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S))
+#define DPORT_APP_OUT_VECBASE_SEL_V 0x3
+#define DPORT_APP_OUT_VECBASE_SEL_S 0
+
+#define DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8)
+/* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: */
+#define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF
+#define DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S))
+#define DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF
+#define DPORT_APP_OUT_VECBASE_REG_S 0
+
+#define DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC)
+/* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */
+/*description: */
+#define DPORT_DATE 0x0FFFFFFF
+#define DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S))
+#define DPORT_DATE_V 0xFFFFFFF
+#define DPORT_DATE_S 0
+#define DPORT_DPORT_DATE_VERSION 0x1605190
-#define IMMU_TABLE8 (DR_REG_DPORT_BASE + 0x524)
-#define DPORT_IMMU_TABLE8 0x0000007F
-#define DPORT_IMMU_TABLE8_S 0
-#define IMMU_TABLE9 (DR_REG_DPORT_BASE + 0x528)
-#define DPORT_IMMU_TABLE9 0x0000007F
-#define DPORT_IMMU_TABLE9_S 0
-#define IMMU_TABLE10 (DR_REG_DPORT_BASE + 0x52C)
-#define DPORT_IMMU_TABLE10 0x0000007F
-#define DPORT_IMMU_TABLE10_S 0
-#define IMMU_TABLE11 (DR_REG_DPORT_BASE + 0x530)
-#define DPORT_IMMU_TABLE11 0x0000007F
-#define DPORT_IMMU_TABLE11_S 0
+#endif /*_SOC_DPORT_REG_H_ */
-#define IMMU_TABLE12 (DR_REG_DPORT_BASE + 0x534)
-#define DPORT_IMMU_TABLE12 0x0000007F
-#define DPORT_IMMU_TABLE12_S 0
-
-#define IMMU_TABLE13 (DR_REG_DPORT_BASE + 0x538)
-#define DPORT_IMMU_TABLE13 0x0000007F
-#define DPORT_IMMU_TABLE13_S 0
-
-#define IMMU_TABLE14 (DR_REG_DPORT_BASE + 0x53C)
-#define DPORT_IMMU_TABLE14 0x0000007F
-#define DPORT_IMMU_TABLE14_S 0
-
-#define IMMU_TABLE15 (DR_REG_DPORT_BASE + 0x540)
-#define DPORT_IMMU_TABLE15 0x0000007F
-#define DPORT_IMMU_TABLE15_S 0
-
-#define DMMU_TABLE0 (DR_REG_DPORT_BASE + 0x544)
-#define DPORT_DMMU_TABLE0 0x0000007F
-#define DPORT_DMMU_TABLE0_S 0
-
-#define DMMU_TABLE1 (DR_REG_DPORT_BASE + 0x548)
-#define DPORT_DMMU_TABLE1 0x0000007F
-#define DPORT_DMMU_TABLE1_S 0
-
-#define DMMU_TABLE2 (DR_REG_DPORT_BASE + 0x54C)
-#define DPORT_DMMU_TABLE2 0x0000007F
-#define DPORT_DMMU_TABLE2_S 0
-
-#define DMMU_TABLE3 (DR_REG_DPORT_BASE + 0x550)
-#define DPORT_DMMU_TABLE3 0x0000007F
-#define DPORT_DMMU_TABLE3_S 0
-
-#define DMMU_TABLE4 (DR_REG_DPORT_BASE + 0x554)
-#define DPORT_DMMU_TABLE4 0x0000007F
-#define DPORT_DMMU_TABLE4_S 0
-
-#define DMMU_TABLE5 (DR_REG_DPORT_BASE + 0x558)
-#define DPORT_DMMU_TABLE5 0x0000007F
-#define DPORT_DMMU_TABLE5_S 0
-
-#define DMMU_TABLE6 (DR_REG_DPORT_BASE + 0x55C)
-#define DPORT_DMMU_TABLE6 0x0000007F
-#define DPORT_DMMU_TABLE6_S 0
-
-#define DMMU_TABLE7 (DR_REG_DPORT_BASE + 0x560)
-#define DPORT_DMMU_TABLE7 0x0000007F
-#define DPORT_DMMU_TABLE7_S 0
-
-#define DMMU_TABLE8 (DR_REG_DPORT_BASE + 0x564)
-#define DPORT_DMMU_TABLE8 0x0000007F
-#define DPORT_DMMU_TABLE8_S 0
-
-#define DMMU_TABLE9 (DR_REG_DPORT_BASE + 0x568)
-#define DPORT_DMMU_TABLE9 0x0000007F
-#define DPORT_DMMU_TABLE9_S 0
-
-#define DMMU_TABLE10 (DR_REG_DPORT_BASE + 0x56C)
-#define DPORT_DMMU_TABLE10 0x0000007F
-#define DPORT_DMMU_TABLE10_S 0
-
-#define DMMU_TABLE11 (DR_REG_DPORT_BASE + 0x570)
-#define DPORT_DMMU_TABLE11 0x0000007F
-#define DPORT_DMMU_TABLE11_S 0
-
-#define DMMU_TABLE12 (DR_REG_DPORT_BASE + 0x574)
-#define DPORT_DMMU_TABLE12 0x0000007F
-#define DPORT_DMMU_TABLE12_S 0
-
-#define DMMU_TABLE13 (DR_REG_DPORT_BASE + 0x578)
-#define DPORT_DMMU_TABLE13 0x0000007F
-#define DPORT_DMMU_TABLE13_S 0
-
-#define DMMU_TABLE14 (DR_REG_DPORT_BASE + 0x57C)
-#define DPORT_DMMU_TABLE14 0x0000007F
-#define DPORT_DMMU_TABLE14_S 0
-
-#define DMMU_TABLE15 (DR_REG_DPORT_BASE + 0x580)
-#define DPORT_DMMU_TABLE15 0x0000007F
-#define DPORT_DMMU_TABLE15_S 0
-
-#define PRO_INTRUSION_CTRL (DR_REG_DPORT_BASE + 0x584)
-#define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0))
-#define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0
-
-#define PRO_INTRUSION_STATUS (DR_REG_DPORT_BASE + 0x588)
-#define DPORT_PRO_INTRUSION_RECORD 0x0000000F
-#define DPORT_PRO_INTRUSION_RECORD_S 0
-
-#define APP_INTRUSION_CTRL (DR_REG_DPORT_BASE + 0x58C)
-#define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0))
-#define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0
-
-#define APP_INTRUSION_STATUS (DR_REG_DPORT_BASE + 0x590)
-#define DPORT_APP_INTRUSION_RECORD 0x0000000F
-#define DPORT_APP_INTRUSION_RECORD_S 0
-
-#define FRONT_END_MEM_PD (DR_REG_DPORT_BASE + 0x594)
-#define DPORT_PBUS_MEM_FORCE_PD (BIT(3))
-#define DPORT_PBUS_MEM_FORCE_PD_S 3
-#define DPORT_PBUS_MEM_FORCE_PU (BIT(2))
-#define DPORT_PBUS_MEM_FORCE_PU_S 2
-#define DPORT_AGC_MEM_FORCE_PD (BIT(1))
-#define DPORT_AGC_MEM_FORCE_PD_S 1
-#define DPORT_AGC_MEM_FORCE_PU (BIT(0))
-#define DPORT_AGC_MEM_FORCE_PU_S 0
-
-#define MMU_IA_INT_EN (DR_REG_DPORT_BASE + 0x598)
-#define DPORT_MMU_IA_INT_EN 0x00FFFFFF
-#define DPORT_MMU_IA_INT_EN_S 0
-
-#define MPU_IA_INT_EN (DR_REG_DPORT_BASE + 0x59C)
-#define DPORT_MPU_IA_INT_EN 0x0001FFFF
-#define DPORT_MPU_IA_INT_EN_S 0
-
-#define CACHE_IA_INT_EN (DR_REG_DPORT_BASE + 0x5A0)
-#define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF
-#define DPORT_CACHE_IA_INT_EN_S 0
-
-#define SECURE_BOOT_CTRL (DR_REG_DPORT_BASE + 0x5A4)
-#define DPORT_SW_BOOTLOADER_SEL (BIT(0))
-#define DPORT_SW_BOOTLOADER_SEL_S 0
-
-#define SPI_DMA_CHAN_SEL (DR_REG_DPORT_BASE + 0x5A8)
-#define DPORT_SPI3_DMA_CHAN_SEL 0x00000003
-#define DPORT_SPI3_DMA_CHAN_SEL_S 4
-#define DPORT_SPI2_DMA_CHAN_SEL 0x00000003
-#define DPORT_SPI2_DMA_CHAN_SEL_S 2
-#define DPORT_SPI1_DMA_CHAN_SEL 0x00000003
-#define DPORT_SPI1_DMA_CHAN_SEL_S 0
-
-#define PRO_VECBASE_CTRL (DR_REG_DPORT_BASE + 0x5AC)
-#define DPORT_PRO_OUT_VECBASE_SEL 0x00000003
-#define DPORT_PRO_OUT_VECBASE_SEL_S 0
-
-#define PRO_VECBASE_SET (DR_REG_DPORT_BASE + 0x5B0)
-#define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF
-#define DPORT_PRO_OUT_VECBASE_REG_S 0
-
-#define APP_VECBASE_CTRL (DR_REG_DPORT_BASE + 0x5B4)
-#define DPORT_APP_OUT_VECBASE_SEL 0x00000003
-#define DPORT_APP_OUT_VECBASE_SEL_S 0
-
-#define APP_VECBASE_SET (DR_REG_DPORT_BASE + 0x5B8)
-#define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF
-#define DPORT_APP_OUT_VECBASE_REG_S 0
-
-#define DPORT_REG_DATE (DR_REG_DPORT_BASE + 0xFFC)
-#define DPORT_DPORT_DATE 0x0FFFFFFF
-#define DPORT_DPORT_DATE_S 0
-#define DPORT_DPORT_DATE_VERSION 0x1605190
-#endif /* _SOC_DPORT_REG_H_ */
#ifndef _SOC_EFUSE_REG_H_
#define _SOC_EFUSE_REG_H_
+
#include "soc.h"
+#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000)
+/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[27:20] ;default: 8'b0 ; */
+/*description: read for flash_crypt_cnt*/
+#define EFUSE_RD_FLASH_CRYPT_CNT 0x000000FF
+#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S))
+#define EFUSE_RD_FLASH_CRYPT_CNT_V 0xFF
+#define EFUSE_RD_FLASH_CRYPT_CNT_S 20
+/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */
+/*description: read for efuse_rd_disable*/
+#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F
+#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S))
+#define EFUSE_RD_EFUSE_RD_DIS_V 0xF
+#define EFUSE_RD_EFUSE_RD_DIS_S 16
+/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: read for efuse_wr_disable*/
+#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF
+#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S))
+#define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF
+#define EFUSE_RD_EFUSE_WR_DIS_S 0
+
+#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004)
+/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: read for low 32bit WIFI_MAC_Address*/
+#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF
+#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S))
+#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF
+#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0
+
+#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008)
+/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: read for high 24bit WIFI_MAC_Address*/
+#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF
+#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S))
+#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF
+#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0
+
+#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
+/* EFUSE_RD_CHIP_VER_RESERVE : RO ;bitpos:[16:9] ;default: 8'b0 ; */
+/*description: */
+#define EFUSE_RD_CHIP_VER_RESERVE 0x000000FF
+#define EFUSE_RD_CHIP_VER_RESERVE_M ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S))
+#define EFUSE_RD_CHIP_VER_RESERVE_V 0xFF
+#define EFUSE_RD_CHIP_VER_RESERVE_S 9
+/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
+/*description: read for SPI_pad_config_hd*/
+#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F
+#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S))
+#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F
+#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4
+/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3))
+#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3))
+#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1
+#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3
+/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_CHIP_VER_32PAD (BIT(2))
+#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2))
+#define EFUSE_RD_CHIP_VER_32PAD_V 0x1
+#define EFUSE_RD_CHIP_VER_32PAD_S 2
+/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1))
+#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1))
+#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1
+#define EFUSE_RD_CHIP_VER_DIS_BT_S 1
+/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0))
+#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0))
+#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1
+#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0
+
+#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010)
+/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: read for sdio_force*/
+#define EFUSE_RD_SDIO_FORCE (BIT(16))
+#define EFUSE_RD_SDIO_FORCE_M (BIT(16))
+#define EFUSE_RD_SDIO_FORCE_V 0x1
+#define EFUSE_RD_SDIO_FORCE_S 16
+/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: read for SDIO_TIEH*/
+#define EFUSE_RD_SDIO_TIEH (BIT(15))
+#define EFUSE_RD_SDIO_TIEH_M (BIT(15))
+#define EFUSE_RD_SDIO_TIEH_V 0x1
+#define EFUSE_RD_SDIO_TIEH_S 15
+/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: read for XPD_SDIO_REG*/
+#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
+#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14))
+#define EFUSE_RD_XPD_SDIO_REG_V 0x1
+#define EFUSE_RD_XPD_SDIO_REG_S 14
+/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_DREFL 0x00000003
+#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S))
+#define EFUSE_RD_SDIO_DREFL_V 0x3
+#define EFUSE_RD_SDIO_DREFL_S 12
+/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_DREFM 0x00000003
+#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S))
+#define EFUSE_RD_SDIO_DREFM_V 0x3
+#define EFUSE_RD_SDIO_DREFM_S 10
+/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_DREFH 0x00000003
+#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S))
+#define EFUSE_RD_SDIO_DREFH_V 0x3
+#define EFUSE_RD_SDIO_DREFH_S 8
+/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define EFUSE_RD_CK8M_FREQ 0x000000FF
+#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S))
+#define EFUSE_RD_CK8M_FREQ_V 0xFF
+#define EFUSE_RD_CK8M_FREQ_S 0
+
+#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014)
+/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: read for flash_crypt_config*/
+#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F
+#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S))
+#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF
+#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
+/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */
+/*description: */
+#define EFUSE_RD_INST_CONFIG 0x000000FF
+#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S))
+#define EFUSE_RD_INST_CONFIG_V 0xFF
+#define EFUSE_RD_INST_CONFIG_S 20
+/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */
+/*description: read for SPI_pad_config_cs0*/
+#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F
+#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S))
+#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F
+#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15
+/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: read for SPI_pad_config_d*/
+#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F
+#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S))
+#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F
+#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10
+/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: read for SPI_pad_config_q*/
+#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F
+#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S))
+#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F
+#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5
+/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: read for SPI_pad_config_clk*/
+#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F
+#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S))
+#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F
+#define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0
+
+#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018)
+/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: read for key_status*/
+#define EFUSE_RD_KEY_STATUS (BIT(10))
+#define EFUSE_RD_KEY_STATUS_M (BIT(10))
+#define EFUSE_RD_KEY_STATUS_V 0x1
+#define EFUSE_RD_KEY_STATUS_S 10
+/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: read for download_dis_cache*/
+#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9))
+#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9))
+#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1
+#define EFUSE_RD_DISABLE_DL_CACHE_S 9
+/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: read for download_dis_decrypt*/
+#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8))
+#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8))
+#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1
+#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8
+/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: read for download_dis_encrypt*/
+#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7))
+#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7))
+#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1
+#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7
+/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: read for JTAG_disable*/
+#define EFUSE_RD_DISABLE_JTAG (BIT(6))
+#define EFUSE_RD_DISABLE_JTAG_M (BIT(6))
+#define EFUSE_RD_DISABLE_JTAG_V 0x1
+#define EFUSE_RD_DISABLE_JTAG_S 6
+/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: read for abstract_done_1*/
+#define EFUSE_RD_ABS_DONE_1 (BIT(5))
+#define EFUSE_RD_ABS_DONE_1_M (BIT(5))
+#define EFUSE_RD_ABS_DONE_1_V 0x1
+#define EFUSE_RD_ABS_DONE_1_S 5
+/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: read for abstract_done_0*/
+#define EFUSE_RD_ABS_DONE_0 (BIT(4))
+#define EFUSE_RD_ABS_DONE_0_M (BIT(4))
+#define EFUSE_RD_ABS_DONE_0_V 0x1
+#define EFUSE_RD_ABS_DONE_0_S 4
+/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3))
+#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3))
+#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1
+#define EFUSE_RD_DISABLE_SDIO_HOST_S 3
+/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: read for console_debug_disable*/
+#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2))
+#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2))
+#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1
+#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2
+/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: read for coding_scheme*/
+#define EFUSE_RD_CODING_SCHEME 0x00000003
+#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S))
+#define EFUSE_RD_CODING_SCHEME_V 0x3
+#define EFUSE_RD_CODING_SCHEME_S 0
+
+#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c)
+/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
+/*description: program for flash_crypt_cnt*/
+#define EFUSE_FLASH_CRYPT_CNT 0x000000FF
+#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S))
+#define EFUSE_FLASH_CRYPT_CNT_V 0xFF
+#define EFUSE_FLASH_CRYPT_CNT_S 20
+/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */
+/*description: program for efuse_rd_disable*/
+#define EFUSE_RD_DIS 0x0000000F
+#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
+#define EFUSE_RD_DIS_V 0xF
+#define EFUSE_RD_DIS_S 16
+/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: program for efuse_wr_disable*/
+#define EFUSE_WR_DIS 0x0000FFFF
+#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V 0xFFFF
+#define EFUSE_WR_DIS_S 0
+
+#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020)
+/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: program for low 32bit WIFI_MAC_Address*/
+#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF
+#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S))
+#define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF
+#define EFUSE_WIFI_MAC_CRC_LOW_S 0
+
+#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024)
+/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: program for high 24bit WIFI_MAC_Address*/
+#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF
+#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S))
+#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF
+#define EFUSE_WIFI_MAC_CRC_HIGH_S 0
+
+#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028)
+/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[16:9] ;default: 8'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_RESERVE 0x000000FF
+#define EFUSE_CHIP_VER_RESERVE_M ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S))
+#define EFUSE_CHIP_VER_RESERVE_V 0xFF
+#define EFUSE_CHIP_VER_RESERVE_S 9
+/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
+/*description: program for SPI_pad_config_hd*/
+#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F
+#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S))
+#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F
+#define EFUSE_SPI_PAD_CONFIG_HD_S 4
+/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3))
+#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3))
+#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1
+#define EFUSE_CHIP_VER_DIS_CACHE_S 3
+/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_32PAD (BIT(2))
+#define EFUSE_CHIP_VER_32PAD_M (BIT(2))
+#define EFUSE_CHIP_VER_32PAD_V 0x1
+#define EFUSE_CHIP_VER_32PAD_S 2
+/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_DIS_BT (BIT(1))
+#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1))
+#define EFUSE_CHIP_VER_DIS_BT_V 0x1
+#define EFUSE_CHIP_VER_DIS_BT_S 1
+/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0))
+#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0))
+#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1
+#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0
+
+#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c)
+/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: program for sdio_force*/
+#define EFUSE_SDIO_FORCE (BIT(16))
+#define EFUSE_SDIO_FORCE_M (BIT(16))
+#define EFUSE_SDIO_FORCE_V 0x1
+#define EFUSE_SDIO_FORCE_S 16
+/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: program for SDIO_TIEH*/
+#define EFUSE_SDIO_TIEH (BIT(15))
+#define EFUSE_SDIO_TIEH_M (BIT(15))
+#define EFUSE_SDIO_TIEH_V 0x1
+#define EFUSE_SDIO_TIEH_S 15
+/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: program for XPD_SDIO_REG*/
+#define EFUSE_XPD_SDIO_REG (BIT(14))
+#define EFUSE_XPD_SDIO_REG_M (BIT(14))
+#define EFUSE_XPD_SDIO_REG_V 0x1
+#define EFUSE_XPD_SDIO_REG_S 14
+/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFL 0x00000003
+#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S))
+#define EFUSE_SDIO_DREFL_V 0x3
+#define EFUSE_SDIO_DREFL_S 12
+/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFM 0x00000003
+#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S))
+#define EFUSE_SDIO_DREFM_V 0x3
+#define EFUSE_SDIO_DREFM_S 10
+/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFH 0x00000003
+#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S))
+#define EFUSE_SDIO_DREFH_V 0x3
+#define EFUSE_SDIO_DREFH_S 8
+/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define EFUSE_CK8M_FREQ 0x000000FF
+#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S))
+#define EFUSE_CK8M_FREQ_V 0xFF
+#define EFUSE_CK8M_FREQ_S 0
+
+#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030)
+/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: program for flash_crypt_config*/
+#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F
+#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S))
+#define EFUSE_FLASH_CRYPT_CONFIG_V 0xF
+#define EFUSE_FLASH_CRYPT_CONFIG_S 28
+/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
+/*description: */
+#define EFUSE_INST_CONFIG 0x000000FF
+#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S))
+#define EFUSE_INST_CONFIG_V 0xFF
+#define EFUSE_INST_CONFIG_S 20
+/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
+/*description: program for SPI_pad_config_cs0*/
+#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F
+#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S))
+#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F
+#define EFUSE_SPI_PAD_CONFIG_CS0_S 15
+/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: program for SPI_pad_config_d*/
+#define EFUSE_SPI_PAD_CONFIG_D 0x0000001F
+#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S))
+#define EFUSE_SPI_PAD_CONFIG_D_V 0x1F
+#define EFUSE_SPI_PAD_CONFIG_D_S 10
+/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: program for SPI_pad_config_q*/
+#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F
+#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S))
+#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F
+#define EFUSE_SPI_PAD_CONFIG_Q_S 5
+/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: program for SPI_pad_config_clk*/
+#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F
+#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S))
+#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F
+#define EFUSE_SPI_PAD_CONFIG_CLK_S 0
+
+#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034)
+/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: program for key_status*/
+#define EFUSE_KEY_STATUS (BIT(10))
+#define EFUSE_KEY_STATUS_M (BIT(10))
+#define EFUSE_KEY_STATUS_V 0x1
+#define EFUSE_KEY_STATUS_S 10
+/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: program for download_dis_cache*/
+#define EFUSE_DISABLE_DL_CACHE (BIT(9))
+#define EFUSE_DISABLE_DL_CACHE_M (BIT(9))
+#define EFUSE_DISABLE_DL_CACHE_V 0x1
+#define EFUSE_DISABLE_DL_CACHE_S 9
+/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: program for download_dis_decrypt*/
+#define EFUSE_DISABLE_DL_DECRYPT (BIT(8))
+#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8))
+#define EFUSE_DISABLE_DL_DECRYPT_V 0x1
+#define EFUSE_DISABLE_DL_DECRYPT_S 8
+/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: program for download_dis_encrypt*/
+#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7))
+#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7))
+#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1
+#define EFUSE_DISABLE_DL_ENCRYPT_S 7
+/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: program for JTAG_disable*/
+#define EFUSE_DISABLE_JTAG (BIT(6))
+#define EFUSE_DISABLE_JTAG_M (BIT(6))
+#define EFUSE_DISABLE_JTAG_V 0x1
+#define EFUSE_DISABLE_JTAG_S 6
+/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: program for abstract_done_1*/
+#define EFUSE_ABS_DONE_1 (BIT(5))
+#define EFUSE_ABS_DONE_1_M (BIT(5))
+#define EFUSE_ABS_DONE_1_V 0x1
+#define EFUSE_ABS_DONE_1_S 5
+/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: program for abstract_done_0*/
+#define EFUSE_ABS_DONE_0 (BIT(4))
+#define EFUSE_ABS_DONE_0_M (BIT(4))
+#define EFUSE_ABS_DONE_0_V 0x1
+#define EFUSE_ABS_DONE_0_S 4
+/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DISABLE_SDIO_HOST (BIT(3))
+#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3))
+#define EFUSE_DISABLE_SDIO_HOST_V 0x1
+#define EFUSE_DISABLE_SDIO_HOST_S 3
+/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: program for console_debug_disable*/
+#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2))
+#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2))
+#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1
+#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2
+/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: program for coding_scheme*/
+#define EFUSE_CODING_SCHEME 0x00000003
+#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S))
+#define EFUSE_CODING_SCHEME_V 0x3
+#define EFUSE_CODING_SCHEME_S 0
+
+#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038)
+/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK1*/
+#define EFUSE_BLK1_DOUT0 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S))
+#define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT0_S 0
+
+#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c)
+/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK1*/
+#define EFUSE_BLK1_DOUT1 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S))
+#define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT1_S 0
+
+#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040)
+/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK1*/
+#define EFUSE_BLK1_DOUT2 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S))
+#define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT2_S 0
+
+#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044)
+/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK1*/
+#define EFUSE_BLK1_DOUT3 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S))
+#define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT3_S 0
+
+#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048)
+/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK1*/
+#define EFUSE_BLK1_DOUT4 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S))
+#define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT4_S 0
+
+#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c)
+/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK1*/
+#define EFUSE_BLK1_DOUT5 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S))
+#define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT5_S 0
+
+#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050)
+/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK1*/
+#define EFUSE_BLK1_DOUT6 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S))
+#define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT6_S 0
+
+#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054)
+/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK1*/
+#define EFUSE_BLK1_DOUT7 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S))
+#define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF
+#define EFUSE_BLK1_DOUT7_S 0
+
+#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058)
+/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK2*/
+#define EFUSE_BLK2_DOUT0 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S))
+#define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT0_S 0
+
+#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c)
+/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK2*/
+#define EFUSE_BLK2_DOUT1 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S))
+#define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT1_S 0
+
+#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060)
+/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK2*/
+#define EFUSE_BLK2_DOUT2 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S))
+#define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT2_S 0
+
+#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064)
+/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK2*/
+#define EFUSE_BLK2_DOUT3 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S))
+#define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT3_S 0
+
+#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068)
+/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK2*/
+#define EFUSE_BLK2_DOUT4 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S))
+#define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT4_S 0
+
+#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c)
+/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK2*/
+#define EFUSE_BLK2_DOUT5 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S))
+#define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT5_S 0
+
+#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070)
+/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK2*/
+#define EFUSE_BLK2_DOUT6 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S))
+#define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT6_S 0
+
+#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074)
+/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK2*/
+#define EFUSE_BLK2_DOUT7 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S))
+#define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF
+#define EFUSE_BLK2_DOUT7_S 0
+
+#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078)
+/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK3*/
+#define EFUSE_BLK3_DOUT0 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S))
+#define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT0_S 0
+
+#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c)
+/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK3*/
+#define EFUSE_BLK3_DOUT1 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S))
+#define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT1_S 0
+
+#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080)
+/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK3*/
+#define EFUSE_BLK3_DOUT2 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S))
+#define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT2_S 0
+
+#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084)
+/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK3*/
+#define EFUSE_BLK3_DOUT3 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S))
+#define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT3_S 0
+
+#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088)
+/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK3*/
+#define EFUSE_BLK3_DOUT4 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S))
+#define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT4_S 0
+
+#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c)
+/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK3*/
+#define EFUSE_BLK3_DOUT5 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S))
+#define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT5_S 0
+
+#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090)
+/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK3*/
+#define EFUSE_BLK3_DOUT6 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S))
+#define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT6_S 0
+
+#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094)
+/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: read for BLOCK3*/
+#define EFUSE_BLK3_DOUT7 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S))
+#define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF
+#define EFUSE_BLK3_DOUT7_S 0
+
+#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098)
+/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK1*/
+#define EFUSE_BLK1_DIN0 0xFFFFFFFF
+#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S))
+#define EFUSE_BLK1_DIN0_V 0xFFFFFFFF
+#define EFUSE_BLK1_DIN0_S 0
+
+#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c)
+/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK1*/
+#define EFUSE_BLK1_DIN1 0xFFFFFFFF
+#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S))
+#define EFUSE_BLK1_DIN1_V 0xFFFFFFFF
+#define EFUSE_BLK1_DIN1_S 0
+
+#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0)
+/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK1*/
+#define EFUSE_BLK1_DIN2 0xFFFFFFFF
+#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S))
+#define EFUSE_BLK1_DIN2_V 0xFFFFFFFF
+#define EFUSE_BLK1_DIN2_S 0
+
+#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4)
+/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK1*/
+#define EFUSE_BLK1_DIN3 0xFFFFFFFF
+#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S))
+#define EFUSE_BLK1_DIN3_V 0xFFFFFFFF
+#define EFUSE_BLK1_DIN3_S 0
+
+#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8)
+/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK1*/
+#define EFUSE_BLK1_DIN4 0xFFFFFFFF
+#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S))
+#define EFUSE_BLK1_DIN4_V 0xFFFFFFFF
+#define EFUSE_BLK1_DIN4_S 0
+
+#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac)
+/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK1*/
+#define EFUSE_BLK1_DIN5 0xFFFFFFFF
+#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S))
+#define EFUSE_BLK1_DIN5_V 0xFFFFFFFF
+#define EFUSE_BLK1_DIN5_S 0
+
+#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0)
+/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK1*/
+#define EFUSE_BLK1_DIN6 0xFFFFFFFF
+#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S))
+#define EFUSE_BLK1_DIN6_V 0xFFFFFFFF
+#define EFUSE_BLK1_DIN6_S 0
+
+#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4)
+/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK1*/
+#define EFUSE_BLK1_DIN7 0xFFFFFFFF
+#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S))
+#define EFUSE_BLK1_DIN7_V 0xFFFFFFFF
+#define EFUSE_BLK1_DIN7_S 0
+
+#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8)
+/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK2*/
+#define EFUSE_BLK2_DIN0 0xFFFFFFFF
+#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S))
+#define EFUSE_BLK2_DIN0_V 0xFFFFFFFF
+#define EFUSE_BLK2_DIN0_S 0
+
+#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc)
+/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK2*/
+#define EFUSE_BLK2_DIN1 0xFFFFFFFF
+#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S))
+#define EFUSE_BLK2_DIN1_V 0xFFFFFFFF
+#define EFUSE_BLK2_DIN1_S 0
+
+#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0)
+/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK2*/
+#define EFUSE_BLK2_DIN2 0xFFFFFFFF
+#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S))
+#define EFUSE_BLK2_DIN2_V 0xFFFFFFFF
+#define EFUSE_BLK2_DIN2_S 0
+
+#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4)
+/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK2*/
+#define EFUSE_BLK2_DIN3 0xFFFFFFFF
+#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S))
+#define EFUSE_BLK2_DIN3_V 0xFFFFFFFF
+#define EFUSE_BLK2_DIN3_S 0
+
+#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8)
+/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK2*/
+#define EFUSE_BLK2_DIN4 0xFFFFFFFF
+#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S))
+#define EFUSE_BLK2_DIN4_V 0xFFFFFFFF
+#define EFUSE_BLK2_DIN4_S 0
+
+#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc)
+/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK2*/
+#define EFUSE_BLK2_DIN5 0xFFFFFFFF
+#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S))
+#define EFUSE_BLK2_DIN5_V 0xFFFFFFFF
+#define EFUSE_BLK2_DIN5_S 0
+
+#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0)
+/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK2*/
+#define EFUSE_BLK2_DIN6 0xFFFFFFFF
+#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S))
+#define EFUSE_BLK2_DIN6_V 0xFFFFFFFF
+#define EFUSE_BLK2_DIN6_S 0
+
+#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4)
+/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK2*/
+#define EFUSE_BLK2_DIN7 0xFFFFFFFF
+#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S))
+#define EFUSE_BLK2_DIN7_V 0xFFFFFFFF
+#define EFUSE_BLK2_DIN7_S 0
+
+#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8)
+/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK3*/
+#define EFUSE_BLK3_DIN0 0xFFFFFFFF
+#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S))
+#define EFUSE_BLK3_DIN0_V 0xFFFFFFFF
+#define EFUSE_BLK3_DIN0_S 0
+
+#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc)
+/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK3*/
+#define EFUSE_BLK3_DIN1 0xFFFFFFFF
+#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S))
+#define EFUSE_BLK3_DIN1_V 0xFFFFFFFF
+#define EFUSE_BLK3_DIN1_S 0
+
+#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0)
+/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK3*/
+#define EFUSE_BLK3_DIN2 0xFFFFFFFF
+#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S))
+#define EFUSE_BLK3_DIN2_V 0xFFFFFFFF
+#define EFUSE_BLK3_DIN2_S 0
+
+#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4)
+/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK3*/
+#define EFUSE_BLK3_DIN3 0xFFFFFFFF
+#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S))
+#define EFUSE_BLK3_DIN3_V 0xFFFFFFFF
+#define EFUSE_BLK3_DIN3_S 0
+
+#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8)
+/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK3*/
+#define EFUSE_BLK3_DIN4 0xFFFFFFFF
+#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S))
+#define EFUSE_BLK3_DIN4_V 0xFFFFFFFF
+#define EFUSE_BLK3_DIN4_S 0
+
+#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec)
+/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK3*/
+#define EFUSE_BLK3_DIN5 0xFFFFFFFF
+#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S))
+#define EFUSE_BLK3_DIN5_V 0xFFFFFFFF
+#define EFUSE_BLK3_DIN5_S 0
+
+#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0)
+/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK3*/
+#define EFUSE_BLK3_DIN6 0xFFFFFFFF
+#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S))
+#define EFUSE_BLK3_DIN6_V 0xFFFFFFFF
+#define EFUSE_BLK3_DIN6_S 0
+
+#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4)
+/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: program for BLOCK3*/
+#define EFUSE_BLK3_DIN7 0xFFFFFFFF
+#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S))
+#define EFUSE_BLK3_DIN7_V 0xFFFFFFFF
+#define EFUSE_BLK3_DIN7_S 0
+
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8)
+/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_CLK_EN (BIT(16))
+#define EFUSE_CLK_EN_M (BIT(16))
+#define EFUSE_CLK_EN_V 0x1
+#define EFUSE_CLK_EN_S 16
+/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */
+/*description: efuse timing configure*/
+#define EFUSE_CLK_SEL1 0x000000FF
+#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S))
+#define EFUSE_CLK_SEL1_V 0xFF
+#define EFUSE_CLK_SEL1_S 8
+/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */
+/*description: efuse timing configure*/
+#define EFUSE_CLK_SEL0 0x000000FF
+#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S))
+#define EFUSE_CLK_SEL0_V 0xFF
+#define EFUSE_CLK_SEL0_S 0
+
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc)
+/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: */
+#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16))
+#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16))
+#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1
+#define EFUSE_FORCE_NO_WR_RD_DIS_S 16
+/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: efuse operation code*/
+#define EFUSE_OP_CODE 0x0000FFFF
+#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
+#define EFUSE_OP_CODE_V 0xFFFF
+#define EFUSE_OP_CODE_S 0
+
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100)
+/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_DEBUG 0xFFFFFFFF
+#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S))
+#define EFUSE_DEBUG_V 0xFFFFFFFF
+#define EFUSE_DEBUG_S 0
+
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104)
+/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: command for program*/
+#define EFUSE_PGM_CMD (BIT(1))
+#define EFUSE_PGM_CMD_M (BIT(1))
+#define EFUSE_PGM_CMD_V 0x1
+#define EFUSE_PGM_CMD_S 1
+/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: command for read*/
+#define EFUSE_READ_CMD (BIT(0))
+#define EFUSE_READ_CMD_M (BIT(0))
+#define EFUSE_READ_CMD_V 0x1
+#define EFUSE_READ_CMD_S 0
+
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108)
+/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program done interrupt raw status*/
+#define EFUSE_PGM_DONE_INT_RAW (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_V 0x1
+#define EFUSE_PGM_DONE_INT_RAW_S 1
+/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: read done interrupt raw status*/
+#define EFUSE_READ_DONE_INT_RAW (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_V 0x1
+#define EFUSE_READ_DONE_INT_RAW_S 0
+
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c)
+/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program done interrupt status*/
+#define EFUSE_PGM_DONE_INT_ST (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_V 0x1
+#define EFUSE_PGM_DONE_INT_ST_S 1
+/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: read done interrupt status*/
+#define EFUSE_READ_DONE_INT_ST (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_V 0x1
+#define EFUSE_READ_DONE_INT_ST_S 0
+
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110)
+/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program done interrupt enable*/
+#define EFUSE_PGM_DONE_INT_ENA (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_V 0x1
+#define EFUSE_PGM_DONE_INT_ENA_S 1
+/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: read done interrupt enable*/
+#define EFUSE_READ_DONE_INT_ENA (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_V 0x1
+#define EFUSE_READ_DONE_INT_ENA_S 0
+
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114)
+/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program done interrupt clear*/
+#define EFUSE_PGM_DONE_INT_CLR (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_V 0x1
+#define EFUSE_PGM_DONE_INT_CLR_S 1
+/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: read done interrupt clear*/
+#define EFUSE_READ_DONE_INT_CLR (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_V 0x1
+#define EFUSE_READ_DONE_INT_CLR_S 0
+
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118)
+/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DAC_CLK_PAD_SEL (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_V 0x1
+#define EFUSE_DAC_CLK_PAD_SEL_S 8
+/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */
+/*description: efuse timing configure*/
+#define EFUSE_DAC_CLK_DIV 0x000000FF
+#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
+#define EFUSE_DAC_CLK_DIV_V 0xFF
+#define EFUSE_DAC_CLK_DIV_S 0
+
+#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c)
+/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */
+/*description: the decode result of 3/4 coding scheme has warning*/
+#define EFUSE_DEC_WARNINGS 0x00000FFF
+#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S))
+#define EFUSE_DEC_WARNINGS_V 0xFFF
+#define EFUSE_DEC_WARNINGS_S 0
+
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC)
+/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */
+/*description: */
+#define EFUSE_DATE 0xFFFFFFFF
+#define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
+#define EFUSE_DATE_V 0xFFFFFFFF
+#define EFUSE_DATE_S 0
+
+
+
+
+#endif /*_SOC_EFUSE_REG_H_ */
-#define EFUSE_BLK0_RDATA0 (DR_REG_EFUSE_BASE + 0x000)
-#define EFUSE_RD_FLASH_CRYPT_CNT 0x000000FF
-#define EFUSE_RD_FLASH_CRYPT_CNT_S 20
-#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F
-#define EFUSE_RD_EFUSE_RD_DIS_S 16
-#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF
-#define EFUSE_RD_EFUSE_WR_DIS_S 0
-
-#define EFUSE_BLK0_RDATA1 (DR_REG_EFUSE_BASE + 0x004)
-#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF
-#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0
-
-#define EFUSE_BLK0_RDATA2 (DR_REG_EFUSE_BASE + 0x008)
-#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF
-#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0
-
-#define EFUSE_BLK0_RDATA3 (DR_REG_EFUSE_BASE + 0x00c)
-#define EFUSE_RD_CHIP_VER_RESERVE 0x00001FFF
-#define EFUSE_RD_CHIP_VER_RESERVE_S 4
-#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3))
-#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3
-#define EFUSE_RD_CHIP_VER_32PAD (BIT(2))
-#define EFUSE_RD_CHIP_VER_32PAD_S 2
-#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1))
-#define EFUSE_RD_CHIP_VER_DIS_BT_S 1
-#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0))
-#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0
-
-#define EFUSE_BLK0_RDATA4 (DR_REG_EFUSE_BASE + 0x010)
-#define EFUSE_RD_SDIO_FORCE (BIT(16))
-#define EFUSE_RD_SDIO_FORCE_S 16
-#define EFUSE_RD_SDIO_TIEH (BIT(15))
-#define EFUSE_RD_SDIO_TIEH_S 15
-#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
-#define EFUSE_RD_XPD_SDIO_REG_S 14
-#define EFUSE_RD_SDIO_DREFL 0x00000003
-#define EFUSE_RD_SDIO_DREFL_S 12
-#define EFUSE_RD_SDIO_DREFM 0x00000003
-#define EFUSE_RD_SDIO_DREFM_S 10
-#define EFUSE_RD_SDIO_DREFH 0x00000003
-#define EFUSE_RD_SDIO_DREFH_S 8
-#define EFUSE_RD_CK8M_FREQ 0x000000FF
-#define EFUSE_RD_CK8M_FREQ_S 0
-
-#define EFUSE_BLK0_RDATA5 (DR_REG_EFUSE_BASE + 0x014)
-#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F
-#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
-#define EFUSE_RD_INST_CONFIG 0x000000FF
-#define EFUSE_RD_INST_CONFIG_S 20
-#define EFUSE_RD_SPI_PAD_CONFIG 0x000FFFFF
-#define EFUSE_RD_SPI_PAD_CONFIG_S 0
-
-#define EFUSE_BLK0_RDATA6 (DR_REG_EFUSE_BASE + 0x018)
-#define EFUSE_RD_KEY_STATUS (BIT(10))
-#define EFUSE_RD_KEY_STATUS_S 10
-#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9))
-#define EFUSE_RD_DISABLE_DL_CACHE_S 9
-#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8))
-#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8
-#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7))
-#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7
-#define EFUSE_RD_DISABLE_JTAG (BIT(6))
-#define EFUSE_RD_DISABLE_JTAG_S 6
-#define EFUSE_RD_ABS_DONE_1 (BIT(5))
-#define EFUSE_RD_ABS_DONE_1_S 5
-#define EFUSE_RD_ABS_DONE_0 (BIT(4))
-#define EFUSE_RD_ABS_DONE_0_S 4
-#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3))
-#define EFUSE_RD_DISABLE_SDIO_HOST_S 3
-#define EFUSE_RD_DIG_RESERVE (BIT(2))
-#define EFUSE_RD_DIG_RESERVE_S 2
-#define EFUSE_RD_CODING_SCHEME 0x00000003
-#define EFUSE_RD_CODING_SCHEME_S 0
-
-#define EFUSE_BLK0_WDATA0 (DR_REG_EFUSE_BASE + 0x01c)
-#define EFUSE_FLASH_CRYPT_CNT 0x000000FF
-#define EFUSE_FLASH_CRYPT_CNT_S 20
-#define EFUSE_EFUSE_RD_DIS 0x0000000F
-#define EFUSE_EFUSE_RD_DIS_S 16
-#define EFUSE_EFUSE_WR_DIS 0x0000FFFF
-#define EFUSE_EFUSE_WR_DIS_S 0
-
-#define EFUSE_BLK0_WDATA1 (DR_REG_EFUSE_BASE + 0x020)
-#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF
-#define EFUSE_WIFI_MAC_CRC_LOW_S 0
-
-#define EFUSE_BLK0_WDATA2 (DR_REG_EFUSE_BASE + 0x024)
-#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF
-#define EFUSE_WIFI_MAC_CRC_HIGH_S 0
-
-#define EFUSE_BLK0_WDATA3 (DR_REG_EFUSE_BASE + 0x028)
-#define EFUSE_CHIP_VER_RESERVE 0x00001FFF
-#define EFUSE_CHIP_VER_RESERVE_S 4
-#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3))
-#define EFUSE_CHIP_VER_DIS_CACHE_S 3
-#define EFUSE_CHIP_VER_32PAD (BIT(2))
-#define EFUSE_CHIP_VER_32PAD_S 2
-#define EFUSE_CHIP_VER_DIS_BT (BIT(1))
-#define EFUSE_CHIP_VER_DIS_BT_S 1
-#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0))
-#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0
-
-#define EFUSE_BLK0_WDATA4 (DR_REG_EFUSE_BASE + 0x02c)
-#define EFUSE_SDIO_FORCE (BIT(16))
-#define EFUSE_SDIO_FORCE_S 16
-#define EFUSE_SDIO_TIEH (BIT(15))
-#define EFUSE_SDIO_TIEH_S 15
-#define EFUSE_XPD_SDIO_REG (BIT(14))
-#define EFUSE_XPD_SDIO_REG_S 14
-#define EFUSE_SDIO_DREFL 0x00000003
-#define EFUSE_SDIO_DREFL_S 12
-#define EFUSE_SDIO_DREFM 0x00000003
-#define EFUSE_SDIO_DREFM_S 10
-#define EFUSE_SDIO_DREFH 0x00000003
-#define EFUSE_SDIO_DREFH_S 8
-#define EFUSE_CK8M_FREQ 0x000000FF
-#define EFUSE_CK8M_FREQ_S 0
-
-#define EFUSE_BLK0_WDATA5 (DR_REG_EFUSE_BASE + 0x030)
-#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F
-#define EFUSE_FLASH_CRYPT_CONFIG_S 28
-#define EFUSE_INST_CONFIG 0x000000FF
-#define EFUSE_INST_CONFIG_S 20
-#define EFUSE_SPI_PAD_CONFIG 0x000FFFFF
-#define EFUSE_SPI_PAD_CONFIG_S 0
-
-#define EFUSE_BLK0_WDATA6 (DR_REG_EFUSE_BASE + 0x034)
-#define EFUSE_KEY_STATUS (BIT(10))
-#define EFUSE_KEY_STATUS_S 10
-#define EFUSE_DISABLE_DL_CACHE (BIT(9))
-#define EFUSE_DISABLE_DL_CACHE_S 9
-#define EFUSE_DISABLE_DL_DECRYPT (BIT(8))
-#define EFUSE_DISABLE_DL_DECRYPT_S 8
-#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7))
-#define EFUSE_DISABLE_DL_ENCRYPT_S 7
-#define EFUSE_DISABLE_JTAG (BIT(6))
-#define EFUSE_DISABLE_JTAG_S 6
-#define EFUSE_ABS_DONE_1 (BIT(5))
-#define EFUSE_ABS_DONE_1_S 5
-#define EFUSE_ABS_DONE_0 (BIT(4))
-#define EFUSE_ABS_DONE_0_S 4
-#define EFUSE_DISABLE_SDIO_HOST (BIT(3))
-#define EFUSE_DISABLE_SDIO_HOST_S 3
-#define EFUSE_DIG_RESERVE (BIT(2))
-#define EFUSE_DIG_RESERVE_S 2
-#define EFUSE_CODING_SCHEME 0x00000003
-#define EFUSE_CODING_SCHEME_S 0
-
-#define EFUSE_BLK1_RDATA0 (DR_REG_EFUSE_BASE + 0x038)
-#define EFUSE_EFUSE_BLK1_DOUT0 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DOUT0_S 0
-
-#define EFUSE_BLK1_RDATA1 (DR_REG_EFUSE_BASE + 0x03c)
-#define EFUSE_EFUSE_BLK1_DOUT1 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DOUT1_S 0
-
-#define EFUSE_BLK1_RDATA2 (DR_REG_EFUSE_BASE + 0x040)
-#define EFUSE_EFUSE_BLK1_DOUT2 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DOUT2_S 0
-
-#define EFUSE_BLK1_RDATA3 (DR_REG_EFUSE_BASE + 0x044)
-#define EFUSE_EFUSE_BLK1_DOUT3 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DOUT3_S 0
-
-#define EFUSE_BLK1_RDATA4 (DR_REG_EFUSE_BASE + 0x048)
-#define EFUSE_EFUSE_BLK1_DOUT4 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DOUT4_S 0
-
-#define EFUSE_BLK1_RDATA5 (DR_REG_EFUSE_BASE + 0x04c)
-#define EFUSE_EFUSE_BLK1_DOUT5 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DOUT5_S 0
-
-#define EFUSE_BLK1_RDATA6 (DR_REG_EFUSE_BASE + 0x050)
-#define EFUSE_EFUSE_BLK1_DOUT6 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DOUT6_S 0
-
-#define EFUSE_BLK1_RDATA7 (DR_REG_EFUSE_BASE + 0x054)
-#define EFUSE_EFUSE_BLK1_DOUT7 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DOUT7_S 0
-
-#define EFUSE_BLK2_RDATA0 (DR_REG_EFUSE_BASE + 0x058)
-#define EFUSE_EFUSE_BLK2_DOUT0 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DOUT0_S 0
-
-#define EFUSE_BLK2_RDATA1 (DR_REG_EFUSE_BASE + 0x05c)
-#define EFUSE_EFUSE_BLK2_DOUT1 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DOUT1_S 0
-
-#define EFUSE_BLK2_RDATA2 (DR_REG_EFUSE_BASE + 0x060)
-#define EFUSE_EFUSE_BLK2_DOUT2 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DOUT2_S 0
-
-#define EFUSE_BLK2_RDATA3 (DR_REG_EFUSE_BASE + 0x064)
-#define EFUSE_EFUSE_BLK2_DOUT3 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DOUT3_S 0
-
-#define EFUSE_BLK2_RDATA4 (DR_REG_EFUSE_BASE + 0x068)
-#define EFUSE_EFUSE_BLK2_DOUT4 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DOUT4_S 0
-
-#define EFUSE_BLK2_RDATA5 (DR_REG_EFUSE_BASE + 0x06c)
-#define EFUSE_EFUSE_BLK2_DOUT5 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DOUT5_S 0
-
-#define EFUSE_BLK2_RDATA6 (DR_REG_EFUSE_BASE + 0x070)
-#define EFUSE_EFUSE_BLK2_DOUT6 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DOUT6_S 0
-
-#define EFUSE_BLK2_RDATA7 (DR_REG_EFUSE_BASE + 0x074)
-#define EFUSE_EFUSE_BLK2_DOUT7 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DOUT7_S 0
-
-#define EFUSE_BLK3_RDATA0 (DR_REG_EFUSE_BASE + 0x078)
-#define EFUSE_EFUSE_BLK3_DOUT0 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DOUT0_S 0
-
-#define EFUSE_BLK3_RDATA1 (DR_REG_EFUSE_BASE + 0x07c)
-#define EFUSE_EFUSE_BLK3_DOUT1 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DOUT1_S 0
-
-#define EFUSE_BLK3_RDATA2 (DR_REG_EFUSE_BASE + 0x080)
-#define EFUSE_EFUSE_BLK3_DOUT2 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DOUT2_S 0
-
-#define EFUSE_BLK3_RDATA3 (DR_REG_EFUSE_BASE + 0x084)
-#define EFUSE_EFUSE_BLK3_DOUT3 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DOUT3_S 0
-
-#define EFUSE_BLK3_RDATA4 (DR_REG_EFUSE_BASE + 0x088)
-#define EFUSE_EFUSE_BLK3_DOUT4 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DOUT4_S 0
-
-#define EFUSE_BLK3_RDATA5 (DR_REG_EFUSE_BASE + 0x08c)
-#define EFUSE_EFUSE_BLK3_DOUT5 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DOUT5_S 0
-
-#define EFUSE_BLK3_RDATA6 (DR_REG_EFUSE_BASE + 0x090)
-#define EFUSE_EFUSE_BLK3_DOUT6 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DOUT6_S 0
-
-#define EFUSE_BLK3_RDATA7 (DR_REG_EFUSE_BASE + 0x094)
-#define EFUSE_EFUSE_BLK3_DOUT7 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DOUT7_S 0
-
-#define EFUSE_BLK1_WDATA0 (DR_REG_EFUSE_BASE + 0x098)
-#define EFUSE_EFUSE_BLK1_DIN0 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DIN0_S 0
-#define EFUSE_BLK1_WDATA1 (DR_REG_EFUSE_BASE + 0x09c)
-#define EFUSE_EFUSE_BLK1_DIN1 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DIN1_S 0
-
-#define EFUSE_BLK1_WDATA2 (DR_REG_EFUSE_BASE + 0x0a0)
-#define EFUSE_EFUSE_BLK1_DIN2 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DIN2_S 0
-
-#define EFUSE_BLK1_WDATA3 (DR_REG_EFUSE_BASE + 0x0a4)
-#define EFUSE_EFUSE_BLK1_DIN3 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DIN3_S 0
-
-#define EFUSE_BLK1_WDATA4 (DR_REG_EFUSE_BASE + 0x0a8)
-#define EFUSE_EFUSE_BLK1_DIN4 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DIN4_S 0
-
-#define EFUSE_BLK1_WDATA5 (DR_REG_EFUSE_BASE + 0x0ac)
-#define EFUSE_EFUSE_BLK1_DIN5 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DIN5_S 0
-
-#define EFUSE_BLK1_WDATA6 (DR_REG_EFUSE_BASE + 0x0b0)
-#define EFUSE_EFUSE_BLK1_DIN6 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DIN6_S 0
-
-#define EFUSE_BLK1_WDATA7 (DR_REG_EFUSE_BASE + 0x0b4)
-#define EFUSE_EFUSE_BLK1_DIN7 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK1_DIN7_S 0
-
-#define EFUSE_BLK2_WDATA0 (DR_REG_EFUSE_BASE + 0x0b8)
-#define EFUSE_EFUSE_BLK2_DIN0 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DIN0_S 0
-
-#define EFUSE_BLK2_WDATA1 (DR_REG_EFUSE_BASE + 0x0bc)
-#define EFUSE_EFUSE_BLK2_DIN1 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DIN1_S 0
-
-#define EFUSE_BLK2_WDATA2 (DR_REG_EFUSE_BASE + 0x0c0)
-#define EFUSE_EFUSE_BLK2_DIN2 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DIN2_S 0
-
-#define EFUSE_BLK2_WDATA3 (DR_REG_EFUSE_BASE + 0x0c4)
-#define EFUSE_EFUSE_BLK2_DIN3 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DIN3_S 0
-
-#define EFUSE_BLK2_WDATA4 (DR_REG_EFUSE_BASE + 0x0c8)
-#define EFUSE_EFUSE_BLK2_DIN4 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DIN4_S 0
-
-#define EFUSE_BLK2_WDATA5 (DR_REG_EFUSE_BASE + 0x0cc)
-#define EFUSE_EFUSE_BLK2_DIN5 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DIN5_S 0
-
-#define EFUSE_BLK2_WDATA6 (DR_REG_EFUSE_BASE + 0x0d0)
-#define EFUSE_EFUSE_BLK2_DIN6 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DIN6_S 0
-
-#define EFUSE_BLK2_WDATA7 (DR_REG_EFUSE_BASE + 0x0d4)
-#define EFUSE_EFUSE_BLK2_DIN7 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK2_DIN7_S 0
-
-#define EFUSE_BLK3_WDATA0 (DR_REG_EFUSE_BASE + 0x0d8)
-#define EFUSE_EFUSE_BLK3_DIN0 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DIN0_S 0
-
-#define EFUSE_BLK3_WDATA1 (DR_REG_EFUSE_BASE + 0x0dc)
-#define EFUSE_EFUSE_BLK3_DIN1 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DIN1_S 0
-
-#define EFUSE_BLK3_WDATA2 (DR_REG_EFUSE_BASE + 0x0e0)
-#define EFUSE_EFUSE_BLK3_DIN2 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DIN2_S 0
-
-#define EFUSE_BLK3_WDATA3 (DR_REG_EFUSE_BASE + 0x0e4)
-#define EFUSE_EFUSE_BLK3_DIN3 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DIN3_S 0
-
-#define EFUSE_BLK3_WDATA4 (DR_REG_EFUSE_BASE + 0x0e8)
-#define EFUSE_EFUSE_BLK3_DIN4 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DIN4_S 0
-
-#define EFUSE_BLK3_WDATA5 (DR_REG_EFUSE_BASE + 0x0ec)
-#define EFUSE_EFUSE_BLK3_DIN5 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DIN5_S 0
-
-#define EFUSE_BLK3_WDATA6 (DR_REG_EFUSE_BASE + 0x0f0)
-#define EFUSE_EFUSE_BLK3_DIN6 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DIN6_S 0
-
-#define EFUSE_BLK3_WDATA7 (DR_REG_EFUSE_BASE + 0x0f4)
-#define EFUSE_EFUSE_BLK3_DIN7 0xFFFFFFFF
-#define EFUSE_EFUSE_BLK3_DIN7_S 0
-
-#define EFUSE_CLK (DR_REG_EFUSE_BASE + 0x0f8)
-#define EFUSE_CLK_EN (BIT(16))
-#define EFUSE_CLK_EN_S 16
-#define EFUSE_EFUSE_CLK_SEL1 0x000000FF
-#define EFUSE_EFUSE_CLK_SEL1_S 8
-#define EFUSE_EFUSE_CLK_SEL0 0x000000FF
-#define EFUSE_EFUSE_CLK_SEL0_S 0
-
-#define EFUSE_CONF (DR_REG_EFUSE_BASE + 0x0fc)
-#define EFUSE_EFUSE_FORCE_NO_WR_RD_DIS (BIT(16))
-#define EFUSE_EFUSE_FORCE_NO_WR_RD_DIS_S 16
-#define EFUSE_EFUSE_OP_CODE 0x0000FFFF
-#define EFUSE_EFUSE_OP_CODE_S 0
-
-#define EFUSE_STATUS (DR_REG_EFUSE_BASE + 0x100)
-#define EFUSE_EFUSE_DEBUG 0xFFFFFFFF
-#define EFUSE_EFUSE_DEBUG_S 0
-
-#define EFUSE_CMD (DR_REG_EFUSE_BASE + 0x104)
-#define EFUSE_EFUSE_PGM_CMD (BIT(1))
-#define EFUSE_EFUSE_PGM_CMD_S 1
-#define EFUSE_EFUSE_READ_CMD (BIT(0))
-#define EFUSE_EFUSE_READ_CMD_S 0
-
-#define EFUSE_INT_RAW (DR_REG_EFUSE_BASE + 0x108)
-#define EFUSE_EFUSE_PGM_DONE_INT_RAW (BIT(1))
-#define EFUSE_EFUSE_PGM_DONE_INT_RAW_S 1
-#define EFUSE_EFUSE_READ_DONE_INT_RAW (BIT(0))
-#define EFUSE_EFUSE_READ_DONE_INT_RAW_S 0
-
-#define EFUSE_INT_ST (DR_REG_EFUSE_BASE + 0x10c)
-#define EFUSE_EFUSE_PGM_DONE_INT_ST (BIT(1))
-#define EFUSE_EFUSE_PGM_DONE_INT_ST_S 1
-#define EFUSE_EFUSE_READ_DONE_INT_ST (BIT(0))
-#define EFUSE_EFUSE_READ_DONE_INT_ST_S 0
-
-#define EFUSE_INT_ENA (DR_REG_EFUSE_BASE + 0x110)
-#define EFUSE_EFUSE_PGM_DONE_INT_ENA (BIT(1))
-#define EFUSE_EFUSE_PGM_DONE_INT_ENA_S 1
-#define EFUSE_EFUSE_READ_DONE_INT_ENA (BIT(0))
-#define EFUSE_EFUSE_READ_DONE_INT_ENA_S 0
-
-#define EFUSE_INT_CLR (DR_REG_EFUSE_BASE + 0x114)
-#define EFUSE_EFUSE_PGM_DONE_INT_CLR (BIT(1))
-#define EFUSE_EFUSE_PGM_DONE_INT_CLR_S 1
-#define EFUSE_EFUSE_READ_DONE_INT_CLR (BIT(0))
-#define EFUSE_EFUSE_READ_DONE_INT_CLR_S 0
-
-#define EFUSE_DAC_CONF (DR_REG_EFUSE_BASE + 0x118)
-#define EFUSE_EFUSE_DAC_CLK_PAD_SEL (BIT(8))
-#define EFUSE_EFUSE_DAC_CLK_PAD_SEL_S 8
-#define EFUSE_EFUSE_DAC_CLK_DIV 0x000000FF
-#define EFUSE_EFUSE_DAC_CLK_DIV_S 0
-
-#define EFUSE_DEC_STATUS (DR_REG_EFUSE_BASE + 0x11c)
-#define EFUSE_EFUSE_DEC_WARNINGS 0x00000FFF
-#define EFUSE_EFUSE_DEC_WARNINGS_S 0
-
-#define EFUSE_DATE (DR_REG_EFUSE_BASE + 0x1FC)
-#define EFUSE_EFUSE_DATE 0xFFFFFFFF
-#define EFUSE_EFUSE_DATE_S 0
-#define EFUSE_EFUSE_DATE_VERSION 0x16042600
-
-#endif /* _SOC_EFUSE_REG_H_ */
#define _SOC_GPIO_REG_H_
#include "soc.h"
+#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0000)
+/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: NA*/
+#define GPIO_BT_SEL 0xFFFFFFFF
+#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
+#define GPIO_BT_SEL_V 0xFFFFFFFF
+#define GPIO_BT_SEL_S 0
+
+#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x0004)
+/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 output value*/
+#define GPIO_OUT_DATA 0xFFFFFFFF
+#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
+#define GPIO_OUT_DATA_V 0xFFFFFFFF
+#define GPIO_OUT_DATA_S 0
+
+#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x0008)
+/* GPIO_OUT_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 output value write 1 to set*/
+#define GPIO_OUT_DATA_W1TS 0xFFFFFFFF
+#define GPIO_OUT_DATA_W1TS_M ((GPIO_OUT_DATA_W1TS_V)<<(GPIO_OUT_DATA_W1TS_S))
+#define GPIO_OUT_DATA_W1TS_V 0xFFFFFFFF
+#define GPIO_OUT_DATA_W1TS_S 0
+
+#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0x000c)
+/* GPIO_OUT_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 output value write 1 to clear*/
+#define GPIO_OUT_DATA_W1TC 0xFFFFFFFF
+#define GPIO_OUT_DATA_W1TC_M ((GPIO_OUT_DATA_W1TC_V)<<(GPIO_OUT_DATA_W1TC_S))
+#define GPIO_OUT_DATA_W1TC_V 0xFFFFFFFF
+#define GPIO_OUT_DATA_W1TC_S 0
+
+#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x0010)
+/* GPIO_OUT1_DATA : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 output value*/
+#define GPIO_OUT1_DATA 0x000000FF
+#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S))
+#define GPIO_OUT1_DATA_V 0xFF
+#define GPIO_OUT1_DATA_S 0
+
+#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x0014)
+/* GPIO_OUT1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 output value write 1 to set*/
+#define GPIO_OUT1_DATA_W1TS 0x000000FF
+#define GPIO_OUT1_DATA_W1TS_M ((GPIO_OUT1_DATA_W1TS_V)<<(GPIO_OUT1_DATA_W1TS_S))
+#define GPIO_OUT1_DATA_W1TS_V 0xFF
+#define GPIO_OUT1_DATA_W1TS_S 0
+
+#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x0018)
+/* GPIO_OUT1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 output value write 1 to clear*/
+#define GPIO_OUT1_DATA_W1TC 0x000000FF
+#define GPIO_OUT1_DATA_W1TC_M ((GPIO_OUT1_DATA_W1TC_V)<<(GPIO_OUT1_DATA_W1TC_S))
+#define GPIO_OUT1_DATA_W1TC_V 0xFF
+#define GPIO_OUT1_DATA_W1TC_S 0
+
+#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x001c)
+/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: SDIO PADS on/off control from outside*/
+#define GPIO_SDIO_SEL 0x000000FF
+#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
+#define GPIO_SDIO_SEL_V 0xFF
+#define GPIO_SDIO_SEL_S 0
+
+#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x0020)
+/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 output enable*/
+#define GPIO_ENABLE_DATA 0xFFFFFFFF
+#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
+#define GPIO_ENABLE_DATA_V 0xFFFFFFFF
+#define GPIO_ENABLE_DATA_S 0
+
+#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x0024)
+/* GPIO_ENABLE_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 output enable write 1 to set*/
+#define GPIO_ENABLE_DATA_W1TS 0xFFFFFFFF
+#define GPIO_ENABLE_DATA_W1TS_M ((GPIO_ENABLE_DATA_W1TS_V)<<(GPIO_ENABLE_DATA_W1TS_S))
+#define GPIO_ENABLE_DATA_W1TS_V 0xFFFFFFFF
+#define GPIO_ENABLE_DATA_W1TS_S 0
+
+#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x0028)
+/* GPIO_ENABLE_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 output enable write 1 to clear*/
+#define GPIO_ENABLE_DATA_W1TC 0xFFFFFFFF
+#define GPIO_ENABLE_DATA_W1TC_M ((GPIO_ENABLE_DATA_W1TC_V)<<(GPIO_ENABLE_DATA_W1TC_S))
+#define GPIO_ENABLE_DATA_W1TC_V 0xFFFFFFFF
+#define GPIO_ENABLE_DATA_W1TC_S 0
+
+#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x002c)
+/* GPIO_ENABLE1_DATA : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 output enable*/
+#define GPIO_ENABLE1_DATA 0x000000FF
+#define GPIO_ENABLE1_DATA_M ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S))
+#define GPIO_ENABLE1_DATA_V 0xFF
+#define GPIO_ENABLE1_DATA_S 0
+
+#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x0030)
+/* GPIO_ENABLE1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 output enable write 1 to set*/
+#define GPIO_ENABLE1_DATA_W1TS 0x000000FF
+#define GPIO_ENABLE1_DATA_W1TS_M ((GPIO_ENABLE1_DATA_W1TS_V)<<(GPIO_ENABLE1_DATA_W1TS_S))
+#define GPIO_ENABLE1_DATA_W1TS_V 0xFF
+#define GPIO_ENABLE1_DATA_W1TS_S 0
+
+#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x0034)
+/* GPIO_ENABLE1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 output enable write 1 to clear*/
+#define GPIO_ENABLE1_DATA_W1TC 0x000000FF
+#define GPIO_ENABLE1_DATA_W1TC_M ((GPIO_ENABLE1_DATA_W1TC_V)<<(GPIO_ENABLE1_DATA_W1TC_S))
+#define GPIO_ENABLE1_DATA_W1TC_V 0xFF
+#define GPIO_ENABLE1_DATA_W1TC_S 0
+
+#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038)
+/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */
+/*description: GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel
+ boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5}*/
+#define GPIO_STRAPPING 0x0000FFFF
+#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
+#define GPIO_STRAPPING_V 0xFFFF
+#define GPIO_STRAPPING_S 0
+
+#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x003c)
+/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default: ; */
+/*description: GPIO0~31 input value*/
+#define GPIO_IN_DATA 0xFFFFFFFF
+#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
+#define GPIO_IN_DATA_V 0xFFFFFFFF
+#define GPIO_IN_DATA_S 0
+
+#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x0040)
+/* GPIO_IN1_DATA : RO ;bitpos:[7:0] ;default: ; */
+/*description: GPIO32~39 input value*/
+#define GPIO_IN1_DATA 0x000000FF
+#define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S))
+#define GPIO_IN1_DATA_V 0xFF
+#define GPIO_IN1_DATA_S 0
+
+#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x0044)
+/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 interrupt status*/
+#define GPIO_STATUS_INT 0xFFFFFFFF
+#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
+#define GPIO_STATUS_INT_V 0xFFFFFFFF
+#define GPIO_STATUS_INT_S 0
+
+#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x0048)
+/* GPIO_STATUS_INT_W1TS : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 interrupt status write 1 to set*/
+#define GPIO_STATUS_INT_W1TS 0xFFFFFFFF
+#define GPIO_STATUS_INT_W1TS_M ((GPIO_STATUS_INT_W1TS_V)<<(GPIO_STATUS_INT_W1TS_S))
+#define GPIO_STATUS_INT_W1TS_V 0xFFFFFFFF
+#define GPIO_STATUS_INT_W1TS_S 0
+
+#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x004c)
+/* GPIO_STATUS_INT_W1TC : R/W ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 interrupt status write 1 to clear*/
+#define GPIO_STATUS_INT_W1TC 0xFFFFFFFF
+#define GPIO_STATUS_INT_W1TC_M ((GPIO_STATUS_INT_W1TC_V)<<(GPIO_STATUS_INT_W1TC_S))
+#define GPIO_STATUS_INT_W1TC_V 0xFFFFFFFF
+#define GPIO_STATUS_INT_W1TC_S 0
+
+#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x0050)
+/* GPIO_STATUS1_INT : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 interrupt status*/
+#define GPIO_STATUS1_INT 0x000000FF
+#define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S))
+#define GPIO_STATUS1_INT_V 0xFF
+#define GPIO_STATUS1_INT_S 0
+
+#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x0054)
+/* GPIO_STATUS1_INT_W1TS : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 interrupt status write 1 to set*/
+#define GPIO_STATUS1_INT_W1TS 0x000000FF
+#define GPIO_STATUS1_INT_W1TS_M ((GPIO_STATUS1_INT_W1TS_V)<<(GPIO_STATUS1_INT_W1TS_S))
+#define GPIO_STATUS1_INT_W1TS_V 0xFF
+#define GPIO_STATUS1_INT_W1TS_S 0
+
+#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x0058)
+/* GPIO_STATUS1_INT_W1TC : R/W ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 interrupt status write 1 to clear*/
+#define GPIO_STATUS1_INT_W1TC 0x000000FF
+#define GPIO_STATUS1_INT_W1TC_M ((GPIO_STATUS1_INT_W1TC_V)<<(GPIO_STATUS1_INT_W1TC_S))
+#define GPIO_STATUS1_INT_W1TC_V 0xFF
+#define GPIO_STATUS1_INT_W1TC_S 0
+
+#define GPIO_ACPU_INT_REG (DR_REG_GPIO_BASE + 0x0060)
+/* GPIO_APPCPU_INT : RO ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 APP CPU interrupt status*/
+#define GPIO_APPCPU_INT 0xFFFFFFFF
+#define GPIO_APPCPU_INT_M ((GPIO_APPCPU_INT_V)<<(GPIO_APPCPU_INT_S))
+#define GPIO_APPCPU_INT_V 0xFFFFFFFF
+#define GPIO_APPCPU_INT_S 0
+
+#define GPIO_ACPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x0064)
+/* GPIO_APPCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 APP CPU non-maskable interrupt status*/
+#define GPIO_APPCPU_NMI_INT 0xFFFFFFFF
+#define GPIO_APPCPU_NMI_INT_M ((GPIO_APPCPU_NMI_INT_V)<<(GPIO_APPCPU_NMI_INT_S))
+#define GPIO_APPCPU_NMI_INT_V 0xFFFFFFFF
+#define GPIO_APPCPU_NMI_INT_S 0
+
+#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x0068)
+/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 PRO CPU interrupt status*/
+#define GPIO_PROCPU_INT 0xFFFFFFFF
+#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
+#define GPIO_PROCPU_INT_V 0xFFFFFFFF
+#define GPIO_PROCPU_INT_S 0
+
+#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x006c)
+/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */
+/*description: GPIO0~31 PRO CPU non-maskable interrupt status*/
+#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF
+#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
+#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF
+#define GPIO_PROCPU_NMI_INT_S 0
+
+#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x0070)
+/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: x ; */
+/*description: SDIO's extent GPIO0~31 interrupt*/
+#define GPIO_SDIO_INT 0xFFFFFFFF
+#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
+#define GPIO_SDIO_INT_V 0xFFFFFFFF
+#define GPIO_SDIO_INT_S 0
+
+#define GPIO_ACPU_INT1_REG (DR_REG_GPIO_BASE + 0x0074)
+/* GPIO_APPCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 APP CPU interrupt status*/
+#define GPIO_APPCPU_INT_H 0x000000FF
+#define GPIO_APPCPU_INT_H_M ((GPIO_APPCPU_INT_H_V)<<(GPIO_APPCPU_INT_H_S))
+#define GPIO_APPCPU_INT_H_V 0xFF
+#define GPIO_APPCPU_INT_H_S 0
+
+#define GPIO_ACPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0078)
+/* GPIO_APPCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 APP CPU non-maskable interrupt status*/
+#define GPIO_APPCPU_NMI_INT_H 0x000000FF
+#define GPIO_APPCPU_NMI_INT_H_M ((GPIO_APPCPU_NMI_INT_H_V)<<(GPIO_APPCPU_NMI_INT_H_S))
+#define GPIO_APPCPU_NMI_INT_H_V 0xFF
+#define GPIO_APPCPU_NMI_INT_H_S 0
+
+#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x007c)
+/* GPIO_PROCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 PRO CPU interrupt status*/
+#define GPIO_PROCPU_INT_H 0x000000FF
+#define GPIO_PROCPU_INT_H_M ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S))
+#define GPIO_PROCPU_INT_H_V 0xFF
+#define GPIO_PROCPU_INT_H_S 0
+
+#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0080)
+/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */
+/*description: GPIO32~39 PRO CPU non-maskable interrupt status*/
+#define GPIO_PROCPU_NMI_INT_H 0x000000FF
+#define GPIO_PROCPU_NMI_INT_H_M ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S))
+#define GPIO_PROCPU_NMI_INT_H_V 0xFF
+#define GPIO_PROCPU_NMI_INT_H_S 0
+
+#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x0084)
+/* GPIO_SDIO_INT_H : RO ;bitpos:[7:0] ;default: x ; */
+/*description: SDIO's extent GPIO32~39 interrupt*/
+#define GPIO_SDIO_INT_H 0x000000FF
+#define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S))
+#define GPIO_SDIO_INT_H_V 0xFF
+#define GPIO_SDIO_INT_H_S 0
+
+#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x0088)
+/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN0_INT_ENA 0x0000001F
+#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
+#define GPIO_PIN0_INT_ENA_V 0x1F
+#define GPIO_PIN0_INT_ENA_S 13
+/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN0_CONFIG 0x00000003
+#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
+#define GPIO_PIN0_CONFIG_V 0x3
+#define GPIO_PIN0_CONFIG_S 11
+/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN0_WAKEUP_ENABLE_S 10
+/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN0_INT_TYPE 0x00000007
+#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
+#define GPIO_PIN0_INT_TYPE_V 0x7
+#define GPIO_PIN0_INT_TYPE_S 7
+/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN0_PAD_DRIVER (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_V 0x1
+#define GPIO_PIN0_PAD_DRIVER_S 2
+
+#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x008c)
+/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN1_INT_ENA 0x0000001F
+#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
+#define GPIO_PIN1_INT_ENA_V 0x1F
+#define GPIO_PIN1_INT_ENA_S 13
+/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN1_CONFIG 0x00000003
+#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
+#define GPIO_PIN1_CONFIG_V 0x3
+#define GPIO_PIN1_CONFIG_S 11
+/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN1_WAKEUP_ENABLE_S 10
+/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN1_INT_TYPE 0x00000007
+#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
+#define GPIO_PIN1_INT_TYPE_V 0x7
+#define GPIO_PIN1_INT_TYPE_S 7
+/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN1_PAD_DRIVER (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_V 0x1
+#define GPIO_PIN1_PAD_DRIVER_S 2
+
+#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x0090)
+/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN2_INT_ENA 0x0000001F
+#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
+#define GPIO_PIN2_INT_ENA_V 0x1F
+#define GPIO_PIN2_INT_ENA_S 13
+/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN2_CONFIG 0x00000003
+#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
+#define GPIO_PIN2_CONFIG_V 0x3
+#define GPIO_PIN2_CONFIG_S 11
+/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN2_WAKEUP_ENABLE_S 10
+/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN2_INT_TYPE 0x00000007
+#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
+#define GPIO_PIN2_INT_TYPE_V 0x7
+#define GPIO_PIN2_INT_TYPE_S 7
+/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN2_PAD_DRIVER (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_V 0x1
+#define GPIO_PIN2_PAD_DRIVER_S 2
+
+#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x0094)
+/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN3_INT_ENA 0x0000001F
+#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
+#define GPIO_PIN3_INT_ENA_V 0x1F
+#define GPIO_PIN3_INT_ENA_S 13
+/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN3_CONFIG 0x00000003
+#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
+#define GPIO_PIN3_CONFIG_V 0x3
+#define GPIO_PIN3_CONFIG_S 11
+/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN3_WAKEUP_ENABLE_S 10
+/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN3_INT_TYPE 0x00000007
+#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
+#define GPIO_PIN3_INT_TYPE_V 0x7
+#define GPIO_PIN3_INT_TYPE_S 7
+/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN3_PAD_DRIVER (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_V 0x1
+#define GPIO_PIN3_PAD_DRIVER_S 2
+
+#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x0098)
+/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN4_INT_ENA 0x0000001F
+#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
+#define GPIO_PIN4_INT_ENA_V 0x1F
+#define GPIO_PIN4_INT_ENA_S 13
+/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN4_CONFIG 0x00000003
+#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
+#define GPIO_PIN4_CONFIG_V 0x3
+#define GPIO_PIN4_CONFIG_S 11
+/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN4_WAKEUP_ENABLE_S 10
+/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN4_INT_TYPE 0x00000007
+#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
+#define GPIO_PIN4_INT_TYPE_V 0x7
+#define GPIO_PIN4_INT_TYPE_S 7
+/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN4_PAD_DRIVER (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_V 0x1
+#define GPIO_PIN4_PAD_DRIVER_S 2
+
+#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x009c)
+/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN5_INT_ENA 0x0000001F
+#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
+#define GPIO_PIN5_INT_ENA_V 0x1F
+#define GPIO_PIN5_INT_ENA_S 13
+/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN5_CONFIG 0x00000003
+#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
+#define GPIO_PIN5_CONFIG_V 0x3
+#define GPIO_PIN5_CONFIG_S 11
+/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN5_WAKEUP_ENABLE_S 10
+/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN5_INT_TYPE 0x00000007
+#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
+#define GPIO_PIN5_INT_TYPE_V 0x7
+#define GPIO_PIN5_INT_TYPE_S 7
+/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN5_PAD_DRIVER (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_V 0x1
+#define GPIO_PIN5_PAD_DRIVER_S 2
+
+#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x00a0)
+/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN6_INT_ENA 0x0000001F
+#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
+#define GPIO_PIN6_INT_ENA_V 0x1F
+#define GPIO_PIN6_INT_ENA_S 13
+/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN6_CONFIG 0x00000003
+#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
+#define GPIO_PIN6_CONFIG_V 0x3
+#define GPIO_PIN6_CONFIG_S 11
+/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN6_WAKEUP_ENABLE_S 10
+/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN6_INT_TYPE 0x00000007
+#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
+#define GPIO_PIN6_INT_TYPE_V 0x7
+#define GPIO_PIN6_INT_TYPE_S 7
+/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN6_PAD_DRIVER (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_V 0x1
+#define GPIO_PIN6_PAD_DRIVER_S 2
+
+#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x00a4)
+/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN7_INT_ENA 0x0000001F
+#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
+#define GPIO_PIN7_INT_ENA_V 0x1F
+#define GPIO_PIN7_INT_ENA_S 13
+/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN7_CONFIG 0x00000003
+#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
+#define GPIO_PIN7_CONFIG_V 0x3
+#define GPIO_PIN7_CONFIG_S 11
+/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN7_WAKEUP_ENABLE_S 10
+/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN7_INT_TYPE 0x00000007
+#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
+#define GPIO_PIN7_INT_TYPE_V 0x7
+#define GPIO_PIN7_INT_TYPE_S 7
+/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN7_PAD_DRIVER (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_V 0x1
+#define GPIO_PIN7_PAD_DRIVER_S 2
+
+#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x00a8)
+/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN8_INT_ENA 0x0000001F
+#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
+#define GPIO_PIN8_INT_ENA_V 0x1F
+#define GPIO_PIN8_INT_ENA_S 13
+/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN8_CONFIG 0x00000003
+#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
+#define GPIO_PIN8_CONFIG_V 0x3
+#define GPIO_PIN8_CONFIG_S 11
+/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN8_WAKEUP_ENABLE_S 10
+/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN8_INT_TYPE 0x00000007
+#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
+#define GPIO_PIN8_INT_TYPE_V 0x7
+#define GPIO_PIN8_INT_TYPE_S 7
+/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN8_PAD_DRIVER (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_V 0x1
+#define GPIO_PIN8_PAD_DRIVER_S 2
+
+#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x00ac)
+/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN9_INT_ENA 0x0000001F
+#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
+#define GPIO_PIN9_INT_ENA_V 0x1F
+#define GPIO_PIN9_INT_ENA_S 13
+/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN9_CONFIG 0x00000003
+#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
+#define GPIO_PIN9_CONFIG_V 0x3
+#define GPIO_PIN9_CONFIG_S 11
+/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN9_WAKEUP_ENABLE_S 10
+/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN9_INT_TYPE 0x00000007
+#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
+#define GPIO_PIN9_INT_TYPE_V 0x7
+#define GPIO_PIN9_INT_TYPE_S 7
+/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN9_PAD_DRIVER (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_V 0x1
+#define GPIO_PIN9_PAD_DRIVER_S 2
+
+#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x00b0)
+/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN10_INT_ENA 0x0000001F
+#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
+#define GPIO_PIN10_INT_ENA_V 0x1F
+#define GPIO_PIN10_INT_ENA_S 13
+/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN10_CONFIG 0x00000003
+#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
+#define GPIO_PIN10_CONFIG_V 0x3
+#define GPIO_PIN10_CONFIG_S 11
+/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN10_WAKEUP_ENABLE_S 10
+/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN10_INT_TYPE 0x00000007
+#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
+#define GPIO_PIN10_INT_TYPE_V 0x7
+#define GPIO_PIN10_INT_TYPE_S 7
+/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN10_PAD_DRIVER (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_V 0x1
+#define GPIO_PIN10_PAD_DRIVER_S 2
+
+#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x00b4)
+/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN11_INT_ENA 0x0000001F
+#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
+#define GPIO_PIN11_INT_ENA_V 0x1F
+#define GPIO_PIN11_INT_ENA_S 13
+/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN11_CONFIG 0x00000003
+#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
+#define GPIO_PIN11_CONFIG_V 0x3
+#define GPIO_PIN11_CONFIG_S 11
+/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN11_WAKEUP_ENABLE_S 10
+/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN11_INT_TYPE 0x00000007
+#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
+#define GPIO_PIN11_INT_TYPE_V 0x7
+#define GPIO_PIN11_INT_TYPE_S 7
+/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN11_PAD_DRIVER (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_V 0x1
+#define GPIO_PIN11_PAD_DRIVER_S 2
+
+#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x00b8)
+/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN12_INT_ENA 0x0000001F
+#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
+#define GPIO_PIN12_INT_ENA_V 0x1F
+#define GPIO_PIN12_INT_ENA_S 13
+/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN12_CONFIG 0x00000003
+#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
+#define GPIO_PIN12_CONFIG_V 0x3
+#define GPIO_PIN12_CONFIG_S 11
+/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN12_WAKEUP_ENABLE_S 10
+/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN12_INT_TYPE 0x00000007
+#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
+#define GPIO_PIN12_INT_TYPE_V 0x7
+#define GPIO_PIN12_INT_TYPE_S 7
+/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN12_PAD_DRIVER (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_V 0x1
+#define GPIO_PIN12_PAD_DRIVER_S 2
+
+#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x00bc)
+/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN13_INT_ENA 0x0000001F
+#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
+#define GPIO_PIN13_INT_ENA_V 0x1F
+#define GPIO_PIN13_INT_ENA_S 13
+/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN13_CONFIG 0x00000003
+#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
+#define GPIO_PIN13_CONFIG_V 0x3
+#define GPIO_PIN13_CONFIG_S 11
+/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN13_WAKEUP_ENABLE_S 10
+/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN13_INT_TYPE 0x00000007
+#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
+#define GPIO_PIN13_INT_TYPE_V 0x7
+#define GPIO_PIN13_INT_TYPE_S 7
+/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN13_PAD_DRIVER (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_V 0x1
+#define GPIO_PIN13_PAD_DRIVER_S 2
+
+#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x00c0)
+/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN14_INT_ENA 0x0000001F
+#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
+#define GPIO_PIN14_INT_ENA_V 0x1F
+#define GPIO_PIN14_INT_ENA_S 13
+/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN14_CONFIG 0x00000003
+#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
+#define GPIO_PIN14_CONFIG_V 0x3
+#define GPIO_PIN14_CONFIG_S 11
+/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN14_WAKEUP_ENABLE_S 10
+/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN14_INT_TYPE 0x00000007
+#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
+#define GPIO_PIN14_INT_TYPE_V 0x7
+#define GPIO_PIN14_INT_TYPE_S 7
+/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN14_PAD_DRIVER (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_V 0x1
+#define GPIO_PIN14_PAD_DRIVER_S 2
+
+#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x00c4)
+/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN15_INT_ENA 0x0000001F
+#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
+#define GPIO_PIN15_INT_ENA_V 0x1F
+#define GPIO_PIN15_INT_ENA_S 13
+/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN15_CONFIG 0x00000003
+#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
+#define GPIO_PIN15_CONFIG_V 0x3
+#define GPIO_PIN15_CONFIG_S 11
+/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN15_WAKEUP_ENABLE_S 10
+/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN15_INT_TYPE 0x00000007
+#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
+#define GPIO_PIN15_INT_TYPE_V 0x7
+#define GPIO_PIN15_INT_TYPE_S 7
+/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN15_PAD_DRIVER (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_V 0x1
+#define GPIO_PIN15_PAD_DRIVER_S 2
+
+#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x00c8)
+/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN16_INT_ENA 0x0000001F
+#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
+#define GPIO_PIN16_INT_ENA_V 0x1F
+#define GPIO_PIN16_INT_ENA_S 13
+/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN16_CONFIG 0x00000003
+#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
+#define GPIO_PIN16_CONFIG_V 0x3
+#define GPIO_PIN16_CONFIG_S 11
+/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN16_WAKEUP_ENABLE_S 10
+/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN16_INT_TYPE 0x00000007
+#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
+#define GPIO_PIN16_INT_TYPE_V 0x7
+#define GPIO_PIN16_INT_TYPE_S 7
+/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN16_PAD_DRIVER (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_V 0x1
+#define GPIO_PIN16_PAD_DRIVER_S 2
+
+#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x00cc)
+/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN17_INT_ENA 0x0000001F
+#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
+#define GPIO_PIN17_INT_ENA_V 0x1F
+#define GPIO_PIN17_INT_ENA_S 13
+/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN17_CONFIG 0x00000003
+#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
+#define GPIO_PIN17_CONFIG_V 0x3
+#define GPIO_PIN17_CONFIG_S 11
+/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN17_WAKEUP_ENABLE_S 10
+/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN17_INT_TYPE 0x00000007
+#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
+#define GPIO_PIN17_INT_TYPE_V 0x7
+#define GPIO_PIN17_INT_TYPE_S 7
+/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN17_PAD_DRIVER (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_V 0x1
+#define GPIO_PIN17_PAD_DRIVER_S 2
+
+#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x00d0)
+/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN18_INT_ENA 0x0000001F
+#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
+#define GPIO_PIN18_INT_ENA_V 0x1F
+#define GPIO_PIN18_INT_ENA_S 13
+/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN18_CONFIG 0x00000003
+#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
+#define GPIO_PIN18_CONFIG_V 0x3
+#define GPIO_PIN18_CONFIG_S 11
+/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN18_WAKEUP_ENABLE_S 10
+/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN18_INT_TYPE 0x00000007
+#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
+#define GPIO_PIN18_INT_TYPE_V 0x7
+#define GPIO_PIN18_INT_TYPE_S 7
+/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN18_PAD_DRIVER (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_V 0x1
+#define GPIO_PIN18_PAD_DRIVER_S 2
+
+#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x00d4)
+/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN19_INT_ENA 0x0000001F
+#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
+#define GPIO_PIN19_INT_ENA_V 0x1F
+#define GPIO_PIN19_INT_ENA_S 13
+/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN19_CONFIG 0x00000003
+#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
+#define GPIO_PIN19_CONFIG_V 0x3
+#define GPIO_PIN19_CONFIG_S 11
+/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN19_WAKEUP_ENABLE_S 10
+/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN19_INT_TYPE 0x00000007
+#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
+#define GPIO_PIN19_INT_TYPE_V 0x7
+#define GPIO_PIN19_INT_TYPE_S 7
+/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN19_PAD_DRIVER (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_V 0x1
+#define GPIO_PIN19_PAD_DRIVER_S 2
+
+#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x00d8)
+/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-mask interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-mask interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN20_INT_ENA 0x0000001F
+#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
+#define GPIO_PIN20_INT_ENA_V 0x1F
+#define GPIO_PIN20_INT_ENA_S 13
+/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN20_CONFIG 0x00000003
+#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
+#define GPIO_PIN20_CONFIG_V 0x3
+#define GPIO_PIN20_CONFIG_S 11
+/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN20_WAKEUP_ENABLE_S 10
+/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN20_INT_TYPE 0x00000007
+#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
+#define GPIO_PIN20_INT_TYPE_V 0x7
+#define GPIO_PIN20_INT_TYPE_S 7
+/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN20_PAD_DRIVER (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_V 0x1
+#define GPIO_PIN20_PAD_DRIVER_S 2
+
+#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x00dc)
+/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN21_INT_ENA 0x0000001F
+#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
+#define GPIO_PIN21_INT_ENA_V 0x1F
+#define GPIO_PIN21_INT_ENA_S 13
+/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN21_CONFIG 0x00000003
+#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
+#define GPIO_PIN21_CONFIG_V 0x3
+#define GPIO_PIN21_CONFIG_S 11
+/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN21_WAKEUP_ENABLE_S 10
+/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN21_INT_TYPE 0x00000007
+#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
+#define GPIO_PIN21_INT_TYPE_V 0x7
+#define GPIO_PIN21_INT_TYPE_S 7
+/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN21_PAD_DRIVER (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_V 0x1
+#define GPIO_PIN21_PAD_DRIVER_S 2
+
+#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x00e0)
+/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: */
+#define GPIO_PIN22_INT_ENA 0x0000001F
+#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
+#define GPIO_PIN22_INT_ENA_V 0x1F
+#define GPIO_PIN22_INT_ENA_S 13
+/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN22_CONFIG 0x00000003
+#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
+#define GPIO_PIN22_CONFIG_V 0x3
+#define GPIO_PIN22_CONFIG_S 11
+/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN22_WAKEUP_ENABLE_S 10
+/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN22_INT_TYPE 0x00000007
+#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
+#define GPIO_PIN22_INT_TYPE_V 0x7
+#define GPIO_PIN22_INT_TYPE_S 7
+/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: */
+#define GPIO_PIN22_PAD_DRIVER (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_V 0x1
+#define GPIO_PIN22_PAD_DRIVER_S 2
+
+#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x00e4)
+/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN23_INT_ENA 0x0000001F
+#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
+#define GPIO_PIN23_INT_ENA_V 0x1F
+#define GPIO_PIN23_INT_ENA_S 13
+/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN23_CONFIG 0x00000003
+#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
+#define GPIO_PIN23_CONFIG_V 0x3
+#define GPIO_PIN23_CONFIG_S 11
+/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN23_WAKEUP_ENABLE_S 10
+/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN23_INT_TYPE 0x00000007
+#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
+#define GPIO_PIN23_INT_TYPE_V 0x7
+#define GPIO_PIN23_INT_TYPE_S 7
+/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN23_PAD_DRIVER (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_V 0x1
+#define GPIO_PIN23_PAD_DRIVER_S 2
+
+#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x00e8)
+/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN24_INT_ENA 0x0000001F
+#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
+#define GPIO_PIN24_INT_ENA_V 0x1F
+#define GPIO_PIN24_INT_ENA_S 13
+/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN24_CONFIG 0x00000003
+#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
+#define GPIO_PIN24_CONFIG_V 0x3
+#define GPIO_PIN24_CONFIG_S 11
+/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN24_WAKEUP_ENABLE_S 10
+/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN24_INT_TYPE 0x00000007
+#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
+#define GPIO_PIN24_INT_TYPE_V 0x7
+#define GPIO_PIN24_INT_TYPE_S 7
+/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN24_PAD_DRIVER (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_V 0x1
+#define GPIO_PIN24_PAD_DRIVER_S 2
+
+#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x00ec)
+/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN25_INT_ENA 0x0000001F
+#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
+#define GPIO_PIN25_INT_ENA_V 0x1F
+#define GPIO_PIN25_INT_ENA_S 13
+/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN25_CONFIG 0x00000003
+#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
+#define GPIO_PIN25_CONFIG_V 0x3
+#define GPIO_PIN25_CONFIG_S 11
+/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN25_WAKEUP_ENABLE_S 10
+/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN25_INT_TYPE 0x00000007
+#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
+#define GPIO_PIN25_INT_TYPE_V 0x7
+#define GPIO_PIN25_INT_TYPE_S 7
+/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN25_PAD_DRIVER (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_V 0x1
+#define GPIO_PIN25_PAD_DRIVER_S 2
+
+#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x00f0)
+/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN26_INT_ENA 0x0000001F
+#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S))
+#define GPIO_PIN26_INT_ENA_V 0x1F
+#define GPIO_PIN26_INT_ENA_S 13
+/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN26_CONFIG 0x00000003
+#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S))
+#define GPIO_PIN26_CONFIG_V 0x3
+#define GPIO_PIN26_CONFIG_S 11
+/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN26_WAKEUP_ENABLE_S 10
+/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN26_INT_TYPE 0x00000007
+#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S))
+#define GPIO_PIN26_INT_TYPE_V 0x7
+#define GPIO_PIN26_INT_TYPE_S 7
+/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN26_PAD_DRIVER (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_V 0x1
+#define GPIO_PIN26_PAD_DRIVER_S 2
+
+#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x00f4)
+/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN27_INT_ENA 0x0000001F
+#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S))
+#define GPIO_PIN27_INT_ENA_V 0x1F
+#define GPIO_PIN27_INT_ENA_S 13
+/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN27_CONFIG 0x00000003
+#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S))
+#define GPIO_PIN27_CONFIG_V 0x3
+#define GPIO_PIN27_CONFIG_S 11
+/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN27_WAKEUP_ENABLE_S 10
+/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN27_INT_TYPE 0x00000007
+#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S))
+#define GPIO_PIN27_INT_TYPE_V 0x7
+#define GPIO_PIN27_INT_TYPE_S 7
+/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN27_PAD_DRIVER (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_V 0x1
+#define GPIO_PIN27_PAD_DRIVER_S 2
+
+#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x00f8)
+/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN28_INT_ENA 0x0000001F
+#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S))
+#define GPIO_PIN28_INT_ENA_V 0x1F
+#define GPIO_PIN28_INT_ENA_S 13
+/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN28_CONFIG 0x00000003
+#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S))
+#define GPIO_PIN28_CONFIG_V 0x3
+#define GPIO_PIN28_CONFIG_S 11
+/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN28_WAKEUP_ENABLE_S 10
+/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN28_INT_TYPE 0x00000007
+#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S))
+#define GPIO_PIN28_INT_TYPE_V 0x7
+#define GPIO_PIN28_INT_TYPE_S 7
+/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN28_PAD_DRIVER (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_V 0x1
+#define GPIO_PIN28_PAD_DRIVER_S 2
+
+#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x00fc)
+/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN29_INT_ENA 0x0000001F
+#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S))
+#define GPIO_PIN29_INT_ENA_V 0x1F
+#define GPIO_PIN29_INT_ENA_S 13
+/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN29_CONFIG 0x00000003
+#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S))
+#define GPIO_PIN29_CONFIG_V 0x3
+#define GPIO_PIN29_CONFIG_S 11
+/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN29_WAKEUP_ENABLE_S 10
+/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN29_INT_TYPE 0x00000007
+#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S))
+#define GPIO_PIN29_INT_TYPE_V 0x7
+#define GPIO_PIN29_INT_TYPE_S 7
+/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN29_PAD_DRIVER (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_V 0x1
+#define GPIO_PIN29_PAD_DRIVER_S 2
+
+#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x0100)
+/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN30_INT_ENA 0x0000001F
+#define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S))
+#define GPIO_PIN30_INT_ENA_V 0x1F
+#define GPIO_PIN30_INT_ENA_S 13
+/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN30_CONFIG 0x00000003
+#define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S))
+#define GPIO_PIN30_CONFIG_V 0x3
+#define GPIO_PIN30_CONFIG_S 11
+/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN30_WAKEUP_ENABLE_S 10
+/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN30_INT_TYPE 0x00000007
+#define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S))
+#define GPIO_PIN30_INT_TYPE_V 0x7
+#define GPIO_PIN30_INT_TYPE_S 7
+/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN30_PAD_DRIVER (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_V 0x1
+#define GPIO_PIN30_PAD_DRIVER_S 2
+
+#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x0104)
+/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN31_INT_ENA 0x0000001F
+#define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S))
+#define GPIO_PIN31_INT_ENA_V 0x1F
+#define GPIO_PIN31_INT_ENA_S 13
+/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN31_CONFIG 0x00000003
+#define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S))
+#define GPIO_PIN31_CONFIG_V 0x3
+#define GPIO_PIN31_CONFIG_S 11
+/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN31_WAKEUP_ENABLE_S 10
+/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN31_INT_TYPE 0x00000007
+#define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S))
+#define GPIO_PIN31_INT_TYPE_V 0x7
+#define GPIO_PIN31_INT_TYPE_S 7
+/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN31_PAD_DRIVER (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_V 0x1
+#define GPIO_PIN31_PAD_DRIVER_S 2
+
+#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x0108)
+/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN32_INT_ENA 0x0000001F
+#define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S))
+#define GPIO_PIN32_INT_ENA_V 0x1F
+#define GPIO_PIN32_INT_ENA_S 13
+/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN32_CONFIG 0x00000003
+#define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S))
+#define GPIO_PIN32_CONFIG_V 0x3
+#define GPIO_PIN32_CONFIG_S 11
+/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN32_WAKEUP_ENABLE_S 10
+/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN32_INT_TYPE 0x00000007
+#define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S))
+#define GPIO_PIN32_INT_TYPE_V 0x7
+#define GPIO_PIN32_INT_TYPE_S 7
+/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN32_PAD_DRIVER (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_V 0x1
+#define GPIO_PIN32_PAD_DRIVER_S 2
+
+#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x010c)
+/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN33_INT_ENA 0x0000001F
+#define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S))
+#define GPIO_PIN33_INT_ENA_V 0x1F
+#define GPIO_PIN33_INT_ENA_S 13
+/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN33_CONFIG 0x00000003
+#define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S))
+#define GPIO_PIN33_CONFIG_V 0x3
+#define GPIO_PIN33_CONFIG_S 11
+/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN33_WAKEUP_ENABLE_S 10
+/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN33_INT_TYPE 0x00000007
+#define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S))
+#define GPIO_PIN33_INT_TYPE_V 0x7
+#define GPIO_PIN33_INT_TYPE_S 7
+/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN33_PAD_DRIVER (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_V 0x1
+#define GPIO_PIN33_PAD_DRIVER_S 2
+
+#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0x0110)
+/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN34_INT_ENA 0x0000001F
+#define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S))
+#define GPIO_PIN34_INT_ENA_V 0x1F
+#define GPIO_PIN34_INT_ENA_S 13
+/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN34_CONFIG 0x00000003
+#define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S))
+#define GPIO_PIN34_CONFIG_V 0x3
+#define GPIO_PIN34_CONFIG_S 11
+/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN34_WAKEUP_ENABLE_S 10
+/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN34_INT_TYPE 0x00000007
+#define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S))
+#define GPIO_PIN34_INT_TYPE_V 0x7
+#define GPIO_PIN34_INT_TYPE_S 7
+/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN34_PAD_DRIVER (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_V 0x1
+#define GPIO_PIN34_PAD_DRIVER_S 2
+
+#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x0114)
+/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN35_INT_ENA 0x0000001F
+#define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S))
+#define GPIO_PIN35_INT_ENA_V 0x1F
+#define GPIO_PIN35_INT_ENA_S 13
+/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN35_CONFIG 0x00000003
+#define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S))
+#define GPIO_PIN35_CONFIG_V 0x3
+#define GPIO_PIN35_CONFIG_S 11
+/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN35_WAKEUP_ENABLE_S 10
+/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN35_INT_TYPE 0x00000007
+#define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S))
+#define GPIO_PIN35_INT_TYPE_V 0x7
+#define GPIO_PIN35_INT_TYPE_S 7
+/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN35_PAD_DRIVER (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_V 0x1
+#define GPIO_PIN35_PAD_DRIVER_S 2
+
+#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x0118)
+/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN36_INT_ENA 0x0000001F
+#define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S))
+#define GPIO_PIN36_INT_ENA_V 0x1F
+#define GPIO_PIN36_INT_ENA_S 13
+/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN36_CONFIG 0x00000003
+#define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S))
+#define GPIO_PIN36_CONFIG_V 0x3
+#define GPIO_PIN36_CONFIG_S 11
+/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN36_WAKEUP_ENABLE_S 10
+/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN36_INT_TYPE 0x00000007
+#define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S))
+#define GPIO_PIN36_INT_TYPE_V 0x7
+#define GPIO_PIN36_INT_TYPE_S 7
+/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN36_PAD_DRIVER (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_V 0x1
+#define GPIO_PIN36_PAD_DRIVER_S 2
+
+#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x011c)
+/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN37_INT_ENA 0x0000001F
+#define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S))
+#define GPIO_PIN37_INT_ENA_V 0x1F
+#define GPIO_PIN37_INT_ENA_S 13
+/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN37_CONFIG 0x00000003
+#define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S))
+#define GPIO_PIN37_CONFIG_V 0x3
+#define GPIO_PIN37_CONFIG_S 11
+/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN37_WAKEUP_ENABLE_S 10
+/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN37_INT_TYPE 0x00000007
+#define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S))
+#define GPIO_PIN37_INT_TYPE_V 0x7
+#define GPIO_PIN37_INT_TYPE_S 7
+/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN37_PAD_DRIVER (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_V 0x1
+#define GPIO_PIN37_PAD_DRIVER_S 2
+
+#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x0120)
+/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN38_INT_ENA 0x0000001F
+#define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S))
+#define GPIO_PIN38_INT_ENA_V 0x1F
+#define GPIO_PIN38_INT_ENA_S 13
+/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN38_CONFIG 0x00000003
+#define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S))
+#define GPIO_PIN38_CONFIG_V 0x3
+#define GPIO_PIN38_CONFIG_S 11
+/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN38_WAKEUP_ENABLE_S 10
+/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN38_INT_TYPE 0x00000007
+#define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S))
+#define GPIO_PIN38_INT_TYPE_V 0x7
+#define GPIO_PIN38_INT_TYPE_S 7
+/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN38_PAD_DRIVER (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_V 0x1
+#define GPIO_PIN38_PAD_DRIVER_S 2
+
+#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x0124)
+/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
+/*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt
+ enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/
+#define GPIO_PIN39_INT_ENA 0x0000001F
+#define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S))
+#define GPIO_PIN39_INT_ENA_V 0x1F
+#define GPIO_PIN39_INT_ENA_S 13
+/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
+/*description: NA*/
+#define GPIO_PIN39_CONFIG 0x00000003
+#define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S))
+#define GPIO_PIN39_CONFIG_V 0x3
+#define GPIO_PIN39_CONFIG_S 11
+/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN39_WAKEUP_ENABLE_S 10
+/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define GPIO_PIN39_INT_TYPE 0x00000007
+#define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S))
+#define GPIO_PIN39_INT_TYPE_V 0x7
+#define GPIO_PIN39_INT_TYPE_S 7
+/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define GPIO_PIN39_PAD_DRIVER (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_V 0x1
+#define GPIO_PIN39_PAD_DRIVER_S 2
+
+#define GPIO_cali_conf_REG (DR_REG_GPIO_BASE + 0x0128)
+/* GPIO_CALI_START : R/W ;bitpos:[31] ;default: x ; */
+/*description: */
+#define GPIO_CALI_START (BIT(31))
+#define GPIO_CALI_START_M (BIT(31))
+#define GPIO_CALI_START_V 0x1
+#define GPIO_CALI_START_S 31
+/* GPIO_CALI_RTC_MAX : R/W ;bitpos:[9:0] ;default: x ; */
+/*description: */
+#define GPIO_CALI_RTC_MAX 0x000003FF
+#define GPIO_CALI_RTC_MAX_M ((GPIO_CALI_RTC_MAX_V)<<(GPIO_CALI_RTC_MAX_S))
+#define GPIO_CALI_RTC_MAX_V 0x3FF
+#define GPIO_CALI_RTC_MAX_S 0
+
+#define GPIO_cali_data_REG (DR_REG_GPIO_BASE + 0x012c)
+/* GPIO_CALI_RDY_SYNC2 : RO ;bitpos:[31] ;default: ; */
+/*description: */
+#define GPIO_CALI_RDY_SYNC2 (BIT(31))
+#define GPIO_CALI_RDY_SYNC2_M (BIT(31))
+#define GPIO_CALI_RDY_SYNC2_V 0x1
+#define GPIO_CALI_RDY_SYNC2_S 31
+/* GPIO_CALI_RDY_REAL : RO ;bitpos:[30] ;default: ; */
+/*description: */
+#define GPIO_CALI_RDY_REAL (BIT(30))
+#define GPIO_CALI_RDY_REAL_M (BIT(30))
+#define GPIO_CALI_RDY_REAL_V 0x1
+#define GPIO_CALI_RDY_REAL_S 30
+/* GPIO_CALI_VALUE_SYNC2 : RO ;bitpos:[19:0] ;default: ; */
+/*description: */
+#define GPIO_CALI_VALUE_SYNC2 0x000FFFFF
+#define GPIO_CALI_VALUE_SYNC2_M ((GPIO_CALI_VALUE_SYNC2_V)<<(GPIO_CALI_VALUE_SYNC2_S))
+#define GPIO_CALI_VALUE_SYNC2_V 0xFFFFF
+#define GPIO_CALI_VALUE_SYNC2_S 0
+
+#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0130)
+/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG0_IN_SEL (BIT(7))
+#define GPIO_SIG0_IN_SEL_M (BIT(7))
+#define GPIO_SIG0_IN_SEL_V 0x1
+#define GPIO_SIG0_IN_SEL_S 7
+/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC0_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC0_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC0_IN_INV_SEL_V 0x1
+#define GPIO_FUNC0_IN_INV_SEL_S 6
+/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC0_IN_SEL 0x0000003F
+#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
+#define GPIO_FUNC0_IN_SEL_V 0x3F
+#define GPIO_FUNC0_IN_SEL_S 0
+
+#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0134)
+/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG1_IN_SEL (BIT(7))
+#define GPIO_SIG1_IN_SEL_M (BIT(7))
+#define GPIO_SIG1_IN_SEL_V 0x1
+#define GPIO_SIG1_IN_SEL_S 7
+/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC1_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_V 0x1
+#define GPIO_FUNC1_IN_INV_SEL_S 6
+/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC1_IN_SEL 0x0000003F
+#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
+#define GPIO_FUNC1_IN_SEL_V 0x3F
+#define GPIO_FUNC1_IN_SEL_S 0
+
+#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0138)
+/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG2_IN_SEL (BIT(7))
+#define GPIO_SIG2_IN_SEL_M (BIT(7))
+#define GPIO_SIG2_IN_SEL_V 0x1
+#define GPIO_SIG2_IN_SEL_S 7
+/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC2_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_V 0x1
+#define GPIO_FUNC2_IN_INV_SEL_S 6
+/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC2_IN_SEL 0x0000003F
+#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
+#define GPIO_FUNC2_IN_SEL_V 0x3F
+#define GPIO_FUNC2_IN_SEL_S 0
+
+#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x013c)
+/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG3_IN_SEL (BIT(7))
+#define GPIO_SIG3_IN_SEL_M (BIT(7))
+#define GPIO_SIG3_IN_SEL_V 0x1
+#define GPIO_SIG3_IN_SEL_S 7
+/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC3_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_V 0x1
+#define GPIO_FUNC3_IN_INV_SEL_S 6
+/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC3_IN_SEL 0x0000003F
+#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
+#define GPIO_FUNC3_IN_SEL_V 0x3F
+#define GPIO_FUNC3_IN_SEL_S 0
+
+#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0140)
+/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG4_IN_SEL (BIT(7))
+#define GPIO_SIG4_IN_SEL_M (BIT(7))
+#define GPIO_SIG4_IN_SEL_V 0x1
+#define GPIO_SIG4_IN_SEL_S 7
+/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC4_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_V 0x1
+#define GPIO_FUNC4_IN_INV_SEL_S 6
+/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC4_IN_SEL 0x0000003F
+#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
+#define GPIO_FUNC4_IN_SEL_V 0x3F
+#define GPIO_FUNC4_IN_SEL_S 0
+
+#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0144)
+/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG5_IN_SEL (BIT(7))
+#define GPIO_SIG5_IN_SEL_M (BIT(7))
+#define GPIO_SIG5_IN_SEL_V 0x1
+#define GPIO_SIG5_IN_SEL_S 7
+/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC5_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_V 0x1
+#define GPIO_FUNC5_IN_INV_SEL_S 6
+/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC5_IN_SEL 0x0000003F
+#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
+#define GPIO_FUNC5_IN_SEL_V 0x3F
+#define GPIO_FUNC5_IN_SEL_S 0
+
+#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0148)
+/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG6_IN_SEL (BIT(7))
+#define GPIO_SIG6_IN_SEL_M (BIT(7))
+#define GPIO_SIG6_IN_SEL_V 0x1
+#define GPIO_SIG6_IN_SEL_S 7
+/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC6_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_V 0x1
+#define GPIO_FUNC6_IN_INV_SEL_S 6
+/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC6_IN_SEL 0x0000003F
+#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
+#define GPIO_FUNC6_IN_SEL_V 0x3F
+#define GPIO_FUNC6_IN_SEL_S 0
+
+#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x014c)
+/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG7_IN_SEL (BIT(7))
+#define GPIO_SIG7_IN_SEL_M (BIT(7))
+#define GPIO_SIG7_IN_SEL_V 0x1
+#define GPIO_SIG7_IN_SEL_S 7
+/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC7_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_V 0x1
+#define GPIO_FUNC7_IN_INV_SEL_S 6
+/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC7_IN_SEL 0x0000003F
+#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
+#define GPIO_FUNC7_IN_SEL_V 0x3F
+#define GPIO_FUNC7_IN_SEL_S 0
+
+#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0150)
+/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG8_IN_SEL (BIT(7))
+#define GPIO_SIG8_IN_SEL_M (BIT(7))
+#define GPIO_SIG8_IN_SEL_V 0x1
+#define GPIO_SIG8_IN_SEL_S 7
+/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC8_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_V 0x1
+#define GPIO_FUNC8_IN_INV_SEL_S 6
+/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC8_IN_SEL 0x0000003F
+#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
+#define GPIO_FUNC8_IN_SEL_V 0x3F
+#define GPIO_FUNC8_IN_SEL_S 0
+
+#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0154)
+/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG9_IN_SEL (BIT(7))
+#define GPIO_SIG9_IN_SEL_M (BIT(7))
+#define GPIO_SIG9_IN_SEL_V 0x1
+#define GPIO_SIG9_IN_SEL_S 7
+/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC9_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_V 0x1
+#define GPIO_FUNC9_IN_INV_SEL_S 6
+/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC9_IN_SEL 0x0000003F
+#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
+#define GPIO_FUNC9_IN_SEL_V 0x3F
+#define GPIO_FUNC9_IN_SEL_S 0
+
+#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0158)
+/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG10_IN_SEL (BIT(7))
+#define GPIO_SIG10_IN_SEL_M (BIT(7))
+#define GPIO_SIG10_IN_SEL_V 0x1
+#define GPIO_SIG10_IN_SEL_S 7
+/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC10_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_V 0x1
+#define GPIO_FUNC10_IN_INV_SEL_S 6
+/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC10_IN_SEL 0x0000003F
+#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
+#define GPIO_FUNC10_IN_SEL_V 0x3F
+#define GPIO_FUNC10_IN_SEL_S 0
+
+#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x015c)
+/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG11_IN_SEL (BIT(7))
+#define GPIO_SIG11_IN_SEL_M (BIT(7))
+#define GPIO_SIG11_IN_SEL_V 0x1
+#define GPIO_SIG11_IN_SEL_S 7
+/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC11_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_V 0x1
+#define GPIO_FUNC11_IN_INV_SEL_S 6
+/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC11_IN_SEL 0x0000003F
+#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
+#define GPIO_FUNC11_IN_SEL_V 0x3F
+#define GPIO_FUNC11_IN_SEL_S 0
+
+#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0160)
+/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG12_IN_SEL (BIT(7))
+#define GPIO_SIG12_IN_SEL_M (BIT(7))
+#define GPIO_SIG12_IN_SEL_V 0x1
+#define GPIO_SIG12_IN_SEL_S 7
+/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC12_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_V 0x1
+#define GPIO_FUNC12_IN_INV_SEL_S 6
+/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC12_IN_SEL 0x0000003F
+#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
+#define GPIO_FUNC12_IN_SEL_V 0x3F
+#define GPIO_FUNC12_IN_SEL_S 0
+
+#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0164)
+/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG13_IN_SEL (BIT(7))
+#define GPIO_SIG13_IN_SEL_M (BIT(7))
+#define GPIO_SIG13_IN_SEL_V 0x1
+#define GPIO_SIG13_IN_SEL_S 7
+/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC13_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_V 0x1
+#define GPIO_FUNC13_IN_INV_SEL_S 6
+/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC13_IN_SEL 0x0000003F
+#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
+#define GPIO_FUNC13_IN_SEL_V 0x3F
+#define GPIO_FUNC13_IN_SEL_S 0
+
+#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0168)
+/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG14_IN_SEL (BIT(7))
+#define GPIO_SIG14_IN_SEL_M (BIT(7))
+#define GPIO_SIG14_IN_SEL_V 0x1
+#define GPIO_SIG14_IN_SEL_S 7
+/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC14_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_V 0x1
+#define GPIO_FUNC14_IN_INV_SEL_S 6
+/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC14_IN_SEL 0x0000003F
+#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
+#define GPIO_FUNC14_IN_SEL_V 0x3F
+#define GPIO_FUNC14_IN_SEL_S 0
+
+#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x016c)
+/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG15_IN_SEL (BIT(7))
+#define GPIO_SIG15_IN_SEL_M (BIT(7))
+#define GPIO_SIG15_IN_SEL_V 0x1
+#define GPIO_SIG15_IN_SEL_S 7
+/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC15_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_V 0x1
+#define GPIO_FUNC15_IN_INV_SEL_S 6
+/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC15_IN_SEL 0x0000003F
+#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
+#define GPIO_FUNC15_IN_SEL_V 0x3F
+#define GPIO_FUNC15_IN_SEL_S 0
+
+#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0170)
+/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG16_IN_SEL (BIT(7))
+#define GPIO_SIG16_IN_SEL_M (BIT(7))
+#define GPIO_SIG16_IN_SEL_V 0x1
+#define GPIO_SIG16_IN_SEL_S 7
+/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC16_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_V 0x1
+#define GPIO_FUNC16_IN_INV_SEL_S 6
+/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC16_IN_SEL 0x0000003F
+#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
+#define GPIO_FUNC16_IN_SEL_V 0x3F
+#define GPIO_FUNC16_IN_SEL_S 0
+
+#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0174)
+/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG17_IN_SEL (BIT(7))
+#define GPIO_SIG17_IN_SEL_M (BIT(7))
+#define GPIO_SIG17_IN_SEL_V 0x1
+#define GPIO_SIG17_IN_SEL_S 7
+/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC17_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_V 0x1
+#define GPIO_FUNC17_IN_INV_SEL_S 6
+/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC17_IN_SEL 0x0000003F
+#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
+#define GPIO_FUNC17_IN_SEL_V 0x3F
+#define GPIO_FUNC17_IN_SEL_S 0
+
+#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0178)
+/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG18_IN_SEL (BIT(7))
+#define GPIO_SIG18_IN_SEL_M (BIT(7))
+#define GPIO_SIG18_IN_SEL_V 0x1
+#define GPIO_SIG18_IN_SEL_S 7
+/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC18_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_V 0x1
+#define GPIO_FUNC18_IN_INV_SEL_S 6
+/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC18_IN_SEL 0x0000003F
+#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
+#define GPIO_FUNC18_IN_SEL_V 0x3F
+#define GPIO_FUNC18_IN_SEL_S 0
+
+#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x017c)
+/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG19_IN_SEL (BIT(7))
+#define GPIO_SIG19_IN_SEL_M (BIT(7))
+#define GPIO_SIG19_IN_SEL_V 0x1
+#define GPIO_SIG19_IN_SEL_S 7
+/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC19_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_V 0x1
+#define GPIO_FUNC19_IN_INV_SEL_S 6
+/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC19_IN_SEL 0x0000003F
+#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
+#define GPIO_FUNC19_IN_SEL_V 0x3F
+#define GPIO_FUNC19_IN_SEL_S 0
+
+#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0180)
+/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG20_IN_SEL (BIT(7))
+#define GPIO_SIG20_IN_SEL_M (BIT(7))
+#define GPIO_SIG20_IN_SEL_V 0x1
+#define GPIO_SIG20_IN_SEL_S 7
+/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC20_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_V 0x1
+#define GPIO_FUNC20_IN_INV_SEL_S 6
+/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC20_IN_SEL 0x0000003F
+#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
+#define GPIO_FUNC20_IN_SEL_V 0x3F
+#define GPIO_FUNC20_IN_SEL_S 0
+
+#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0184)
+/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG21_IN_SEL (BIT(7))
+#define GPIO_SIG21_IN_SEL_M (BIT(7))
+#define GPIO_SIG21_IN_SEL_V 0x1
+#define GPIO_SIG21_IN_SEL_S 7
+/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC21_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_V 0x1
+#define GPIO_FUNC21_IN_INV_SEL_S 6
+/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC21_IN_SEL 0x0000003F
+#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
+#define GPIO_FUNC21_IN_SEL_V 0x3F
+#define GPIO_FUNC21_IN_SEL_S 0
+
+#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0188)
+/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG22_IN_SEL (BIT(7))
+#define GPIO_SIG22_IN_SEL_M (BIT(7))
+#define GPIO_SIG22_IN_SEL_V 0x1
+#define GPIO_SIG22_IN_SEL_S 7
+/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC22_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_V 0x1
+#define GPIO_FUNC22_IN_INV_SEL_S 6
+/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC22_IN_SEL 0x0000003F
+#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
+#define GPIO_FUNC22_IN_SEL_V 0x3F
+#define GPIO_FUNC22_IN_SEL_S 0
+
+#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x018c)
+/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG23_IN_SEL (BIT(7))
+#define GPIO_SIG23_IN_SEL_M (BIT(7))
+#define GPIO_SIG23_IN_SEL_V 0x1
+#define GPIO_SIG23_IN_SEL_S 7
+/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC23_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_V 0x1
+#define GPIO_FUNC23_IN_INV_SEL_S 6
+/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC23_IN_SEL 0x0000003F
+#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
+#define GPIO_FUNC23_IN_SEL_V 0x3F
+#define GPIO_FUNC23_IN_SEL_S 0
+
+#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0190)
+/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG24_IN_SEL (BIT(7))
+#define GPIO_SIG24_IN_SEL_M (BIT(7))
+#define GPIO_SIG24_IN_SEL_V 0x1
+#define GPIO_SIG24_IN_SEL_S 7
+/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC24_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_V 0x1
+#define GPIO_FUNC24_IN_INV_SEL_S 6
+/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC24_IN_SEL 0x0000003F
+#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
+#define GPIO_FUNC24_IN_SEL_V 0x3F
+#define GPIO_FUNC24_IN_SEL_S 0
+
+#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0194)
+/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG25_IN_SEL (BIT(7))
+#define GPIO_SIG25_IN_SEL_M (BIT(7))
+#define GPIO_SIG25_IN_SEL_V 0x1
+#define GPIO_SIG25_IN_SEL_S 7
+/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC25_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_V 0x1
+#define GPIO_FUNC25_IN_INV_SEL_S 6
+/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC25_IN_SEL 0x0000003F
+#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
+#define GPIO_FUNC25_IN_SEL_V 0x3F
+#define GPIO_FUNC25_IN_SEL_S 0
+
+#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0198)
+/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG26_IN_SEL (BIT(7))
+#define GPIO_SIG26_IN_SEL_M (BIT(7))
+#define GPIO_SIG26_IN_SEL_V 0x1
+#define GPIO_SIG26_IN_SEL_S 7
+/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC26_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_V 0x1
+#define GPIO_FUNC26_IN_INV_SEL_S 6
+/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC26_IN_SEL 0x0000003F
+#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
+#define GPIO_FUNC26_IN_SEL_V 0x3F
+#define GPIO_FUNC26_IN_SEL_S 0
+
+#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x019c)
+/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG27_IN_SEL (BIT(7))
+#define GPIO_SIG27_IN_SEL_M (BIT(7))
+#define GPIO_SIG27_IN_SEL_V 0x1
+#define GPIO_SIG27_IN_SEL_S 7
+/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC27_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_V 0x1
+#define GPIO_FUNC27_IN_INV_SEL_S 6
+/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC27_IN_SEL 0x0000003F
+#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
+#define GPIO_FUNC27_IN_SEL_V 0x3F
+#define GPIO_FUNC27_IN_SEL_S 0
+
+#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a0)
+/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG28_IN_SEL (BIT(7))
+#define GPIO_SIG28_IN_SEL_M (BIT(7))
+#define GPIO_SIG28_IN_SEL_V 0x1
+#define GPIO_SIG28_IN_SEL_S 7
+/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC28_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_V 0x1
+#define GPIO_FUNC28_IN_INV_SEL_S 6
+/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC28_IN_SEL 0x0000003F
+#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
+#define GPIO_FUNC28_IN_SEL_V 0x3F
+#define GPIO_FUNC28_IN_SEL_S 0
+
+#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a4)
+/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG29_IN_SEL (BIT(7))
+#define GPIO_SIG29_IN_SEL_M (BIT(7))
+#define GPIO_SIG29_IN_SEL_V 0x1
+#define GPIO_SIG29_IN_SEL_S 7
+/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC29_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_V 0x1
+#define GPIO_FUNC29_IN_INV_SEL_S 6
+/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC29_IN_SEL 0x0000003F
+#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
+#define GPIO_FUNC29_IN_SEL_V 0x3F
+#define GPIO_FUNC29_IN_SEL_S 0
+
+#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a8)
+/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG30_IN_SEL (BIT(7))
+#define GPIO_SIG30_IN_SEL_M (BIT(7))
+#define GPIO_SIG30_IN_SEL_V 0x1
+#define GPIO_SIG30_IN_SEL_S 7
+/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC30_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_V 0x1
+#define GPIO_FUNC30_IN_INV_SEL_S 6
+/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC30_IN_SEL 0x0000003F
+#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
+#define GPIO_FUNC30_IN_SEL_V 0x3F
+#define GPIO_FUNC30_IN_SEL_S 0
+
+#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ac)
+/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG31_IN_SEL (BIT(7))
+#define GPIO_SIG31_IN_SEL_M (BIT(7))
+#define GPIO_SIG31_IN_SEL_V 0x1
+#define GPIO_SIG31_IN_SEL_S 7
+/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC31_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_V 0x1
+#define GPIO_FUNC31_IN_INV_SEL_S 6
+/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC31_IN_SEL 0x0000003F
+#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
+#define GPIO_FUNC31_IN_SEL_V 0x3F
+#define GPIO_FUNC31_IN_SEL_S 0
+
+#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b0)
+/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG32_IN_SEL (BIT(7))
+#define GPIO_SIG32_IN_SEL_M (BIT(7))
+#define GPIO_SIG32_IN_SEL_V 0x1
+#define GPIO_SIG32_IN_SEL_S 7
+/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC32_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_V 0x1
+#define GPIO_FUNC32_IN_INV_SEL_S 6
+/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC32_IN_SEL 0x0000003F
+#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
+#define GPIO_FUNC32_IN_SEL_V 0x3F
+#define GPIO_FUNC32_IN_SEL_S 0
+
+#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b4)
+/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG33_IN_SEL (BIT(7))
+#define GPIO_SIG33_IN_SEL_M (BIT(7))
+#define GPIO_SIG33_IN_SEL_V 0x1
+#define GPIO_SIG33_IN_SEL_S 7
+/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC33_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_V 0x1
+#define GPIO_FUNC33_IN_INV_SEL_S 6
+/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC33_IN_SEL 0x0000003F
+#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
+#define GPIO_FUNC33_IN_SEL_V 0x3F
+#define GPIO_FUNC33_IN_SEL_S 0
+
+#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b8)
+/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG34_IN_SEL (BIT(7))
+#define GPIO_SIG34_IN_SEL_M (BIT(7))
+#define GPIO_SIG34_IN_SEL_V 0x1
+#define GPIO_SIG34_IN_SEL_S 7
+/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC34_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_V 0x1
+#define GPIO_FUNC34_IN_INV_SEL_S 6
+/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC34_IN_SEL 0x0000003F
+#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
+#define GPIO_FUNC34_IN_SEL_V 0x3F
+#define GPIO_FUNC34_IN_SEL_S 0
+
+#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01bc)
+/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG35_IN_SEL (BIT(7))
+#define GPIO_SIG35_IN_SEL_M (BIT(7))
+#define GPIO_SIG35_IN_SEL_V 0x1
+#define GPIO_SIG35_IN_SEL_S 7
+/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC35_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_V 0x1
+#define GPIO_FUNC35_IN_INV_SEL_S 6
+/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC35_IN_SEL 0x0000003F
+#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
+#define GPIO_FUNC35_IN_SEL_V 0x3F
+#define GPIO_FUNC35_IN_SEL_S 0
+
+#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c0)
+/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG36_IN_SEL (BIT(7))
+#define GPIO_SIG36_IN_SEL_M (BIT(7))
+#define GPIO_SIG36_IN_SEL_V 0x1
+#define GPIO_SIG36_IN_SEL_S 7
+/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC36_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_V 0x1
+#define GPIO_FUNC36_IN_INV_SEL_S 6
+/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC36_IN_SEL 0x0000003F
+#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
+#define GPIO_FUNC36_IN_SEL_V 0x3F
+#define GPIO_FUNC36_IN_SEL_S 0
+
+#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c4)
+/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG37_IN_SEL (BIT(7))
+#define GPIO_SIG37_IN_SEL_M (BIT(7))
+#define GPIO_SIG37_IN_SEL_V 0x1
+#define GPIO_SIG37_IN_SEL_S 7
+/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC37_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_V 0x1
+#define GPIO_FUNC37_IN_INV_SEL_S 6
+/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC37_IN_SEL 0x0000003F
+#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
+#define GPIO_FUNC37_IN_SEL_V 0x3F
+#define GPIO_FUNC37_IN_SEL_S 0
+
+#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c8)
+/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG38_IN_SEL (BIT(7))
+#define GPIO_SIG38_IN_SEL_M (BIT(7))
+#define GPIO_SIG38_IN_SEL_V 0x1
+#define GPIO_SIG38_IN_SEL_S 7
+/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC38_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_V 0x1
+#define GPIO_FUNC38_IN_INV_SEL_S 6
+/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC38_IN_SEL 0x0000003F
+#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
+#define GPIO_FUNC38_IN_SEL_V 0x3F
+#define GPIO_FUNC38_IN_SEL_S 0
+
+#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01cc)
+/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG39_IN_SEL (BIT(7))
+#define GPIO_SIG39_IN_SEL_M (BIT(7))
+#define GPIO_SIG39_IN_SEL_V 0x1
+#define GPIO_SIG39_IN_SEL_S 7
+/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC39_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_V 0x1
+#define GPIO_FUNC39_IN_INV_SEL_S 6
+/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC39_IN_SEL 0x0000003F
+#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
+#define GPIO_FUNC39_IN_SEL_V 0x3F
+#define GPIO_FUNC39_IN_SEL_S 0
+
+#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d0)
+/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG40_IN_SEL (BIT(7))
+#define GPIO_SIG40_IN_SEL_M (BIT(7))
+#define GPIO_SIG40_IN_SEL_V 0x1
+#define GPIO_SIG40_IN_SEL_S 7
+/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC40_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_V 0x1
+#define GPIO_FUNC40_IN_INV_SEL_S 6
+/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC40_IN_SEL 0x0000003F
+#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
+#define GPIO_FUNC40_IN_SEL_V 0x3F
+#define GPIO_FUNC40_IN_SEL_S 0
+
+#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d4)
+/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG41_IN_SEL (BIT(7))
+#define GPIO_SIG41_IN_SEL_M (BIT(7))
+#define GPIO_SIG41_IN_SEL_V 0x1
+#define GPIO_SIG41_IN_SEL_S 7
+/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC41_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_V 0x1
+#define GPIO_FUNC41_IN_INV_SEL_S 6
+/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC41_IN_SEL 0x0000003F
+#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
+#define GPIO_FUNC41_IN_SEL_V 0x3F
+#define GPIO_FUNC41_IN_SEL_S 0
+
+#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d8)
+/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG42_IN_SEL (BIT(7))
+#define GPIO_SIG42_IN_SEL_M (BIT(7))
+#define GPIO_SIG42_IN_SEL_V 0x1
+#define GPIO_SIG42_IN_SEL_S 7
+/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC42_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_V 0x1
+#define GPIO_FUNC42_IN_INV_SEL_S 6
+/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC42_IN_SEL 0x0000003F
+#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
+#define GPIO_FUNC42_IN_SEL_V 0x3F
+#define GPIO_FUNC42_IN_SEL_S 0
+
+#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01dc)
+/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG43_IN_SEL (BIT(7))
+#define GPIO_SIG43_IN_SEL_M (BIT(7))
+#define GPIO_SIG43_IN_SEL_V 0x1
+#define GPIO_SIG43_IN_SEL_S 7
+/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC43_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_V 0x1
+#define GPIO_FUNC43_IN_INV_SEL_S 6
+/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC43_IN_SEL 0x0000003F
+#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
+#define GPIO_FUNC43_IN_SEL_V 0x3F
+#define GPIO_FUNC43_IN_SEL_S 0
+
+#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e0)
+/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG44_IN_SEL (BIT(7))
+#define GPIO_SIG44_IN_SEL_M (BIT(7))
+#define GPIO_SIG44_IN_SEL_V 0x1
+#define GPIO_SIG44_IN_SEL_S 7
+/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC44_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_V 0x1
+#define GPIO_FUNC44_IN_INV_SEL_S 6
+/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC44_IN_SEL 0x0000003F
+#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
+#define GPIO_FUNC44_IN_SEL_V 0x3F
+#define GPIO_FUNC44_IN_SEL_S 0
+
+#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e4)
+/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG45_IN_SEL (BIT(7))
+#define GPIO_SIG45_IN_SEL_M (BIT(7))
+#define GPIO_SIG45_IN_SEL_V 0x1
+#define GPIO_SIG45_IN_SEL_S 7
+/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC45_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_V 0x1
+#define GPIO_FUNC45_IN_INV_SEL_S 6
+/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC45_IN_SEL 0x0000003F
+#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
+#define GPIO_FUNC45_IN_SEL_V 0x3F
+#define GPIO_FUNC45_IN_SEL_S 0
+
+#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e8)
+/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG46_IN_SEL (BIT(7))
+#define GPIO_SIG46_IN_SEL_M (BIT(7))
+#define GPIO_SIG46_IN_SEL_V 0x1
+#define GPIO_SIG46_IN_SEL_S 7
+/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC46_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC46_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC46_IN_INV_SEL_V 0x1
+#define GPIO_FUNC46_IN_INV_SEL_S 6
+/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC46_IN_SEL 0x0000003F
+#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
+#define GPIO_FUNC46_IN_SEL_V 0x3F
+#define GPIO_FUNC46_IN_SEL_S 0
+
+#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ec)
+/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG47_IN_SEL (BIT(7))
+#define GPIO_SIG47_IN_SEL_M (BIT(7))
+#define GPIO_SIG47_IN_SEL_V 0x1
+#define GPIO_SIG47_IN_SEL_S 7
+/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC47_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_V 0x1
+#define GPIO_FUNC47_IN_INV_SEL_S 6
+/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC47_IN_SEL 0x0000003F
+#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
+#define GPIO_FUNC47_IN_SEL_V 0x3F
+#define GPIO_FUNC47_IN_SEL_S 0
+
+#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f0)
+/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG48_IN_SEL (BIT(7))
+#define GPIO_SIG48_IN_SEL_M (BIT(7))
+#define GPIO_SIG48_IN_SEL_V 0x1
+#define GPIO_SIG48_IN_SEL_S 7
+/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC48_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_V 0x1
+#define GPIO_FUNC48_IN_INV_SEL_S 6
+/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC48_IN_SEL 0x0000003F
+#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
+#define GPIO_FUNC48_IN_SEL_V 0x3F
+#define GPIO_FUNC48_IN_SEL_S 0
+
+#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f4)
+/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG49_IN_SEL (BIT(7))
+#define GPIO_SIG49_IN_SEL_M (BIT(7))
+#define GPIO_SIG49_IN_SEL_V 0x1
+#define GPIO_SIG49_IN_SEL_S 7
+/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC49_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_V 0x1
+#define GPIO_FUNC49_IN_INV_SEL_S 6
+/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC49_IN_SEL 0x0000003F
+#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
+#define GPIO_FUNC49_IN_SEL_V 0x3F
+#define GPIO_FUNC49_IN_SEL_S 0
+
+#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f8)
+/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG50_IN_SEL (BIT(7))
+#define GPIO_SIG50_IN_SEL_M (BIT(7))
+#define GPIO_SIG50_IN_SEL_V 0x1
+#define GPIO_SIG50_IN_SEL_S 7
+/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC50_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_V 0x1
+#define GPIO_FUNC50_IN_INV_SEL_S 6
+/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC50_IN_SEL 0x0000003F
+#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
+#define GPIO_FUNC50_IN_SEL_V 0x3F
+#define GPIO_FUNC50_IN_SEL_S 0
+
+#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01fc)
+/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG51_IN_SEL (BIT(7))
+#define GPIO_SIG51_IN_SEL_M (BIT(7))
+#define GPIO_SIG51_IN_SEL_V 0x1
+#define GPIO_SIG51_IN_SEL_S 7
+/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC51_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_V 0x1
+#define GPIO_FUNC51_IN_INV_SEL_S 6
+/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC51_IN_SEL 0x0000003F
+#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
+#define GPIO_FUNC51_IN_SEL_V 0x3F
+#define GPIO_FUNC51_IN_SEL_S 0
+
+#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0200)
+/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG52_IN_SEL (BIT(7))
+#define GPIO_SIG52_IN_SEL_M (BIT(7))
+#define GPIO_SIG52_IN_SEL_V 0x1
+#define GPIO_SIG52_IN_SEL_S 7
+/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC52_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_V 0x1
+#define GPIO_FUNC52_IN_INV_SEL_S 6
+/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC52_IN_SEL 0x0000003F
+#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
+#define GPIO_FUNC52_IN_SEL_V 0x3F
+#define GPIO_FUNC52_IN_SEL_S 0
+
+#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0204)
+/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG53_IN_SEL (BIT(7))
+#define GPIO_SIG53_IN_SEL_M (BIT(7))
+#define GPIO_SIG53_IN_SEL_V 0x1
+#define GPIO_SIG53_IN_SEL_S 7
+/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC53_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_V 0x1
+#define GPIO_FUNC53_IN_INV_SEL_S 6
+/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC53_IN_SEL 0x0000003F
+#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
+#define GPIO_FUNC53_IN_SEL_V 0x3F
+#define GPIO_FUNC53_IN_SEL_S 0
+
+#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0208)
+/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG54_IN_SEL (BIT(7))
+#define GPIO_SIG54_IN_SEL_M (BIT(7))
+#define GPIO_SIG54_IN_SEL_V 0x1
+#define GPIO_SIG54_IN_SEL_S 7
+/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC54_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_V 0x1
+#define GPIO_FUNC54_IN_INV_SEL_S 6
+/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC54_IN_SEL 0x0000003F
+#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
+#define GPIO_FUNC54_IN_SEL_V 0x3F
+#define GPIO_FUNC54_IN_SEL_S 0
+
+#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x020c)
+/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG55_IN_SEL (BIT(7))
+#define GPIO_SIG55_IN_SEL_M (BIT(7))
+#define GPIO_SIG55_IN_SEL_V 0x1
+#define GPIO_SIG55_IN_SEL_S 7
+/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC55_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_V 0x1
+#define GPIO_FUNC55_IN_INV_SEL_S 6
+/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC55_IN_SEL 0x0000003F
+#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
+#define GPIO_FUNC55_IN_SEL_V 0x3F
+#define GPIO_FUNC55_IN_SEL_S 0
+
+#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0210)
+/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG56_IN_SEL (BIT(7))
+#define GPIO_SIG56_IN_SEL_M (BIT(7))
+#define GPIO_SIG56_IN_SEL_V 0x1
+#define GPIO_SIG56_IN_SEL_S 7
+/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC56_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_V 0x1
+#define GPIO_FUNC56_IN_INV_SEL_S 6
+/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC56_IN_SEL 0x0000003F
+#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
+#define GPIO_FUNC56_IN_SEL_V 0x3F
+#define GPIO_FUNC56_IN_SEL_S 0
+
+#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0214)
+/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG57_IN_SEL (BIT(7))
+#define GPIO_SIG57_IN_SEL_M (BIT(7))
+#define GPIO_SIG57_IN_SEL_V 0x1
+#define GPIO_SIG57_IN_SEL_S 7
+/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC57_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_V 0x1
+#define GPIO_FUNC57_IN_INV_SEL_S 6
+/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC57_IN_SEL 0x0000003F
+#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
+#define GPIO_FUNC57_IN_SEL_V 0x3F
+#define GPIO_FUNC57_IN_SEL_S 0
+
+#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0218)
+/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG58_IN_SEL (BIT(7))
+#define GPIO_SIG58_IN_SEL_M (BIT(7))
+#define GPIO_SIG58_IN_SEL_V 0x1
+#define GPIO_SIG58_IN_SEL_S 7
+/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC58_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_V 0x1
+#define GPIO_FUNC58_IN_INV_SEL_S 6
+/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC58_IN_SEL 0x0000003F
+#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
+#define GPIO_FUNC58_IN_SEL_V 0x3F
+#define GPIO_FUNC58_IN_SEL_S 0
+
+#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x021c)
+/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG59_IN_SEL (BIT(7))
+#define GPIO_SIG59_IN_SEL_M (BIT(7))
+#define GPIO_SIG59_IN_SEL_V 0x1
+#define GPIO_SIG59_IN_SEL_S 7
+/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC59_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_V 0x1
+#define GPIO_FUNC59_IN_INV_SEL_S 6
+/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC59_IN_SEL 0x0000003F
+#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
+#define GPIO_FUNC59_IN_SEL_V 0x3F
+#define GPIO_FUNC59_IN_SEL_S 0
+
+#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0220)
+/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG60_IN_SEL (BIT(7))
+#define GPIO_SIG60_IN_SEL_M (BIT(7))
+#define GPIO_SIG60_IN_SEL_V 0x1
+#define GPIO_SIG60_IN_SEL_S 7
+/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC60_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_V 0x1
+#define GPIO_FUNC60_IN_INV_SEL_S 6
+/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC60_IN_SEL 0x0000003F
+#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
+#define GPIO_FUNC60_IN_SEL_V 0x3F
+#define GPIO_FUNC60_IN_SEL_S 0
+
+#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0224)
+/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG61_IN_SEL (BIT(7))
+#define GPIO_SIG61_IN_SEL_M (BIT(7))
+#define GPIO_SIG61_IN_SEL_V 0x1
+#define GPIO_SIG61_IN_SEL_S 7
+/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC61_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_V 0x1
+#define GPIO_FUNC61_IN_INV_SEL_S 6
+/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC61_IN_SEL 0x0000003F
+#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
+#define GPIO_FUNC61_IN_SEL_V 0x3F
+#define GPIO_FUNC61_IN_SEL_S 0
+
+#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0228)
+/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG62_IN_SEL (BIT(7))
+#define GPIO_SIG62_IN_SEL_M (BIT(7))
+#define GPIO_SIG62_IN_SEL_V 0x1
+#define GPIO_SIG62_IN_SEL_S 7
+/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC62_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_V 0x1
+#define GPIO_FUNC62_IN_INV_SEL_S 6
+/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC62_IN_SEL 0x0000003F
+#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
+#define GPIO_FUNC62_IN_SEL_V 0x3F
+#define GPIO_FUNC62_IN_SEL_S 0
+
+#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x022c)
+/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG63_IN_SEL (BIT(7))
+#define GPIO_SIG63_IN_SEL_M (BIT(7))
+#define GPIO_SIG63_IN_SEL_V 0x1
+#define GPIO_SIG63_IN_SEL_S 7
+/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC63_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_V 0x1
+#define GPIO_FUNC63_IN_INV_SEL_S 6
+/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC63_IN_SEL 0x0000003F
+#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
+#define GPIO_FUNC63_IN_SEL_V 0x3F
+#define GPIO_FUNC63_IN_SEL_S 0
+
+#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0230)
+/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG64_IN_SEL (BIT(7))
+#define GPIO_SIG64_IN_SEL_M (BIT(7))
+#define GPIO_SIG64_IN_SEL_V 0x1
+#define GPIO_SIG64_IN_SEL_S 7
+/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC64_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_V 0x1
+#define GPIO_FUNC64_IN_INV_SEL_S 6
+/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC64_IN_SEL 0x0000003F
+#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
+#define GPIO_FUNC64_IN_SEL_V 0x3F
+#define GPIO_FUNC64_IN_SEL_S 0
+
+#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0234)
+/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG65_IN_SEL (BIT(7))
+#define GPIO_SIG65_IN_SEL_M (BIT(7))
+#define GPIO_SIG65_IN_SEL_V 0x1
+#define GPIO_SIG65_IN_SEL_S 7
+/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC65_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_V 0x1
+#define GPIO_FUNC65_IN_INV_SEL_S 6
+/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC65_IN_SEL 0x0000003F
+#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
+#define GPIO_FUNC65_IN_SEL_V 0x3F
+#define GPIO_FUNC65_IN_SEL_S 0
+
+#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0238)
+/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG66_IN_SEL (BIT(7))
+#define GPIO_SIG66_IN_SEL_M (BIT(7))
+#define GPIO_SIG66_IN_SEL_V 0x1
+#define GPIO_SIG66_IN_SEL_S 7
+/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC66_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_V 0x1
+#define GPIO_FUNC66_IN_INV_SEL_S 6
+/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC66_IN_SEL 0x0000003F
+#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
+#define GPIO_FUNC66_IN_SEL_V 0x3F
+#define GPIO_FUNC66_IN_SEL_S 0
+
+#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x023c)
+/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG67_IN_SEL (BIT(7))
+#define GPIO_SIG67_IN_SEL_M (BIT(7))
+#define GPIO_SIG67_IN_SEL_V 0x1
+#define GPIO_SIG67_IN_SEL_S 7
+/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC67_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC67_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC67_IN_INV_SEL_V 0x1
+#define GPIO_FUNC67_IN_INV_SEL_S 6
+/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC67_IN_SEL 0x0000003F
+#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
+#define GPIO_FUNC67_IN_SEL_V 0x3F
+#define GPIO_FUNC67_IN_SEL_S 0
+
+#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0240)
+/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG68_IN_SEL (BIT(7))
+#define GPIO_SIG68_IN_SEL_M (BIT(7))
+#define GPIO_SIG68_IN_SEL_V 0x1
+#define GPIO_SIG68_IN_SEL_S 7
+/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC68_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_V 0x1
+#define GPIO_FUNC68_IN_INV_SEL_S 6
+/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC68_IN_SEL 0x0000003F
+#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
+#define GPIO_FUNC68_IN_SEL_V 0x3F
+#define GPIO_FUNC68_IN_SEL_S 0
+
+#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0244)
+/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG69_IN_SEL (BIT(7))
+#define GPIO_SIG69_IN_SEL_M (BIT(7))
+#define GPIO_SIG69_IN_SEL_V 0x1
+#define GPIO_SIG69_IN_SEL_S 7
+/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC69_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_V 0x1
+#define GPIO_FUNC69_IN_INV_SEL_S 6
+/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC69_IN_SEL 0x0000003F
+#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
+#define GPIO_FUNC69_IN_SEL_V 0x3F
+#define GPIO_FUNC69_IN_SEL_S 0
+
+#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0248)
+/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG70_IN_SEL (BIT(7))
+#define GPIO_SIG70_IN_SEL_M (BIT(7))
+#define GPIO_SIG70_IN_SEL_V 0x1
+#define GPIO_SIG70_IN_SEL_S 7
+/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC70_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_V 0x1
+#define GPIO_FUNC70_IN_INV_SEL_S 6
+/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC70_IN_SEL 0x0000003F
+#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
+#define GPIO_FUNC70_IN_SEL_V 0x3F
+#define GPIO_FUNC70_IN_SEL_S 0
+
+#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x024c)
+/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG71_IN_SEL (BIT(7))
+#define GPIO_SIG71_IN_SEL_M (BIT(7))
+#define GPIO_SIG71_IN_SEL_V 0x1
+#define GPIO_SIG71_IN_SEL_S 7
+/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC71_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_V 0x1
+#define GPIO_FUNC71_IN_INV_SEL_S 6
+/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC71_IN_SEL 0x0000003F
+#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
+#define GPIO_FUNC71_IN_SEL_V 0x3F
+#define GPIO_FUNC71_IN_SEL_S 0
+
+#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0250)
+/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG72_IN_SEL (BIT(7))
+#define GPIO_SIG72_IN_SEL_M (BIT(7))
+#define GPIO_SIG72_IN_SEL_V 0x1
+#define GPIO_SIG72_IN_SEL_S 7
+/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC72_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC72_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC72_IN_INV_SEL_V 0x1
+#define GPIO_FUNC72_IN_INV_SEL_S 6
+/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC72_IN_SEL 0x0000003F
+#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
+#define GPIO_FUNC72_IN_SEL_V 0x3F
+#define GPIO_FUNC72_IN_SEL_S 0
+
+#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0254)
+/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG73_IN_SEL (BIT(7))
+#define GPIO_SIG73_IN_SEL_M (BIT(7))
+#define GPIO_SIG73_IN_SEL_V 0x1
+#define GPIO_SIG73_IN_SEL_S 7
+/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC73_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC73_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC73_IN_INV_SEL_V 0x1
+#define GPIO_FUNC73_IN_INV_SEL_S 6
+/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC73_IN_SEL 0x0000003F
+#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
+#define GPIO_FUNC73_IN_SEL_V 0x3F
+#define GPIO_FUNC73_IN_SEL_S 0
+
+#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0258)
+/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG74_IN_SEL (BIT(7))
+#define GPIO_SIG74_IN_SEL_M (BIT(7))
+#define GPIO_SIG74_IN_SEL_V 0x1
+#define GPIO_SIG74_IN_SEL_S 7
+/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC74_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_V 0x1
+#define GPIO_FUNC74_IN_INV_SEL_S 6
+/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC74_IN_SEL 0x0000003F
+#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
+#define GPIO_FUNC74_IN_SEL_V 0x3F
+#define GPIO_FUNC74_IN_SEL_S 0
+
+#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x025c)
+/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG75_IN_SEL (BIT(7))
+#define GPIO_SIG75_IN_SEL_M (BIT(7))
+#define GPIO_SIG75_IN_SEL_V 0x1
+#define GPIO_SIG75_IN_SEL_S 7
+/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC75_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_V 0x1
+#define GPIO_FUNC75_IN_INV_SEL_S 6
+/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC75_IN_SEL 0x0000003F
+#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
+#define GPIO_FUNC75_IN_SEL_V 0x3F
+#define GPIO_FUNC75_IN_SEL_S 0
+
+#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0260)
+/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG76_IN_SEL (BIT(7))
+#define GPIO_SIG76_IN_SEL_M (BIT(7))
+#define GPIO_SIG76_IN_SEL_V 0x1
+#define GPIO_SIG76_IN_SEL_S 7
+/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC76_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_V 0x1
+#define GPIO_FUNC76_IN_INV_SEL_S 6
+/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC76_IN_SEL 0x0000003F
+#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
+#define GPIO_FUNC76_IN_SEL_V 0x3F
+#define GPIO_FUNC76_IN_SEL_S 0
+
+#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0264)
+/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG77_IN_SEL (BIT(7))
+#define GPIO_SIG77_IN_SEL_M (BIT(7))
+#define GPIO_SIG77_IN_SEL_V 0x1
+#define GPIO_SIG77_IN_SEL_S 7
+/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC77_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_V 0x1
+#define GPIO_FUNC77_IN_INV_SEL_S 6
+/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC77_IN_SEL 0x0000003F
+#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
+#define GPIO_FUNC77_IN_SEL_V 0x3F
+#define GPIO_FUNC77_IN_SEL_S 0
+
+#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0268)
+/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG78_IN_SEL (BIT(7))
+#define GPIO_SIG78_IN_SEL_M (BIT(7))
+#define GPIO_SIG78_IN_SEL_V 0x1
+#define GPIO_SIG78_IN_SEL_S 7
+/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC78_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_V 0x1
+#define GPIO_FUNC78_IN_INV_SEL_S 6
+/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC78_IN_SEL 0x0000003F
+#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
+#define GPIO_FUNC78_IN_SEL_V 0x3F
+#define GPIO_FUNC78_IN_SEL_S 0
+
+#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x026c)
+/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG79_IN_SEL (BIT(7))
+#define GPIO_SIG79_IN_SEL_M (BIT(7))
+#define GPIO_SIG79_IN_SEL_V 0x1
+#define GPIO_SIG79_IN_SEL_S 7
+/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC79_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC79_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC79_IN_INV_SEL_V 0x1
+#define GPIO_FUNC79_IN_INV_SEL_S 6
+/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC79_IN_SEL 0x0000003F
+#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
+#define GPIO_FUNC79_IN_SEL_V 0x3F
+#define GPIO_FUNC79_IN_SEL_S 0
+
+#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0270)
+/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG80_IN_SEL (BIT(7))
+#define GPIO_SIG80_IN_SEL_M (BIT(7))
+#define GPIO_SIG80_IN_SEL_V 0x1
+#define GPIO_SIG80_IN_SEL_S 7
+/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC80_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_V 0x1
+#define GPIO_FUNC80_IN_INV_SEL_S 6
+/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC80_IN_SEL 0x0000003F
+#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
+#define GPIO_FUNC80_IN_SEL_V 0x3F
+#define GPIO_FUNC80_IN_SEL_S 0
+
+#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0274)
+/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG81_IN_SEL (BIT(7))
+#define GPIO_SIG81_IN_SEL_M (BIT(7))
+#define GPIO_SIG81_IN_SEL_V 0x1
+#define GPIO_SIG81_IN_SEL_S 7
+/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC81_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC81_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC81_IN_INV_SEL_V 0x1
+#define GPIO_FUNC81_IN_INV_SEL_S 6
+/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC81_IN_SEL 0x0000003F
+#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
+#define GPIO_FUNC81_IN_SEL_V 0x3F
+#define GPIO_FUNC81_IN_SEL_S 0
+
+#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0278)
+/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG82_IN_SEL (BIT(7))
+#define GPIO_SIG82_IN_SEL_M (BIT(7))
+#define GPIO_SIG82_IN_SEL_V 0x1
+#define GPIO_SIG82_IN_SEL_S 7
+/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC82_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC82_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC82_IN_INV_SEL_V 0x1
+#define GPIO_FUNC82_IN_INV_SEL_S 6
+/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC82_IN_SEL 0x0000003F
+#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
+#define GPIO_FUNC82_IN_SEL_V 0x3F
+#define GPIO_FUNC82_IN_SEL_S 0
+
+#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x027c)
+/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG83_IN_SEL (BIT(7))
+#define GPIO_SIG83_IN_SEL_M (BIT(7))
+#define GPIO_SIG83_IN_SEL_V 0x1
+#define GPIO_SIG83_IN_SEL_S 7
+/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC83_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_V 0x1
+#define GPIO_FUNC83_IN_INV_SEL_S 6
+/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC83_IN_SEL 0x0000003F
+#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
+#define GPIO_FUNC83_IN_SEL_V 0x3F
+#define GPIO_FUNC83_IN_SEL_S 0
+
+#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0280)
+/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG84_IN_SEL (BIT(7))
+#define GPIO_SIG84_IN_SEL_M (BIT(7))
+#define GPIO_SIG84_IN_SEL_V 0x1
+#define GPIO_SIG84_IN_SEL_S 7
+/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC84_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC84_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC84_IN_INV_SEL_V 0x1
+#define GPIO_FUNC84_IN_INV_SEL_S 6
+/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC84_IN_SEL 0x0000003F
+#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
+#define GPIO_FUNC84_IN_SEL_V 0x3F
+#define GPIO_FUNC84_IN_SEL_S 0
+
+#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0284)
+/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG85_IN_SEL (BIT(7))
+#define GPIO_SIG85_IN_SEL_M (BIT(7))
+#define GPIO_SIG85_IN_SEL_V 0x1
+#define GPIO_SIG85_IN_SEL_S 7
+/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC85_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC85_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC85_IN_INV_SEL_V 0x1
+#define GPIO_FUNC85_IN_INV_SEL_S 6
+/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC85_IN_SEL 0x0000003F
+#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
+#define GPIO_FUNC85_IN_SEL_V 0x3F
+#define GPIO_FUNC85_IN_SEL_S 0
+
+#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0288)
+/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG86_IN_SEL (BIT(7))
+#define GPIO_SIG86_IN_SEL_M (BIT(7))
+#define GPIO_SIG86_IN_SEL_V 0x1
+#define GPIO_SIG86_IN_SEL_S 7
+/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC86_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_V 0x1
+#define GPIO_FUNC86_IN_INV_SEL_S 6
+/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC86_IN_SEL 0x0000003F
+#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
+#define GPIO_FUNC86_IN_SEL_V 0x3F
+#define GPIO_FUNC86_IN_SEL_S 0
+
+#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x028c)
+/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG87_IN_SEL (BIT(7))
+#define GPIO_SIG87_IN_SEL_M (BIT(7))
+#define GPIO_SIG87_IN_SEL_V 0x1
+#define GPIO_SIG87_IN_SEL_S 7
+/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC87_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC87_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC87_IN_INV_SEL_V 0x1
+#define GPIO_FUNC87_IN_INV_SEL_S 6
+/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC87_IN_SEL 0x0000003F
+#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
+#define GPIO_FUNC87_IN_SEL_V 0x3F
+#define GPIO_FUNC87_IN_SEL_S 0
+
+#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0290)
+/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG88_IN_SEL (BIT(7))
+#define GPIO_SIG88_IN_SEL_M (BIT(7))
+#define GPIO_SIG88_IN_SEL_V 0x1
+#define GPIO_SIG88_IN_SEL_S 7
+/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC88_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC88_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC88_IN_INV_SEL_V 0x1
+#define GPIO_FUNC88_IN_INV_SEL_S 6
+/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC88_IN_SEL 0x0000003F
+#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
+#define GPIO_FUNC88_IN_SEL_V 0x3F
+#define GPIO_FUNC88_IN_SEL_S 0
+
+#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0294)
+/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG89_IN_SEL (BIT(7))
+#define GPIO_SIG89_IN_SEL_M (BIT(7))
+#define GPIO_SIG89_IN_SEL_V 0x1
+#define GPIO_SIG89_IN_SEL_S 7
+/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC89_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_V 0x1
+#define GPIO_FUNC89_IN_INV_SEL_S 6
+/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC89_IN_SEL 0x0000003F
+#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
+#define GPIO_FUNC89_IN_SEL_V 0x3F
+#define GPIO_FUNC89_IN_SEL_S 0
+
+#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0298)
+/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG90_IN_SEL (BIT(7))
+#define GPIO_SIG90_IN_SEL_M (BIT(7))
+#define GPIO_SIG90_IN_SEL_V 0x1
+#define GPIO_SIG90_IN_SEL_S 7
+/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC90_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_V 0x1
+#define GPIO_FUNC90_IN_INV_SEL_S 6
+/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC90_IN_SEL 0x0000003F
+#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
+#define GPIO_FUNC90_IN_SEL_V 0x3F
+#define GPIO_FUNC90_IN_SEL_S 0
+
+#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x029c)
+/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG91_IN_SEL (BIT(7))
+#define GPIO_SIG91_IN_SEL_M (BIT(7))
+#define GPIO_SIG91_IN_SEL_V 0x1
+#define GPIO_SIG91_IN_SEL_S 7
+/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC91_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_V 0x1
+#define GPIO_FUNC91_IN_INV_SEL_S 6
+/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC91_IN_SEL 0x0000003F
+#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
+#define GPIO_FUNC91_IN_SEL_V 0x3F
+#define GPIO_FUNC91_IN_SEL_S 0
+
+#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a0)
+/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG92_IN_SEL (BIT(7))
+#define GPIO_SIG92_IN_SEL_M (BIT(7))
+#define GPIO_SIG92_IN_SEL_V 0x1
+#define GPIO_SIG92_IN_SEL_S 7
+/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC92_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_V 0x1
+#define GPIO_FUNC92_IN_INV_SEL_S 6
+/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC92_IN_SEL 0x0000003F
+#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
+#define GPIO_FUNC92_IN_SEL_V 0x3F
+#define GPIO_FUNC92_IN_SEL_S 0
+
+#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a4)
+/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG93_IN_SEL (BIT(7))
+#define GPIO_SIG93_IN_SEL_M (BIT(7))
+#define GPIO_SIG93_IN_SEL_V 0x1
+#define GPIO_SIG93_IN_SEL_S 7
+/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC93_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_V 0x1
+#define GPIO_FUNC93_IN_INV_SEL_S 6
+/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC93_IN_SEL 0x0000003F
+#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
+#define GPIO_FUNC93_IN_SEL_V 0x3F
+#define GPIO_FUNC93_IN_SEL_S 0
+
+#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a8)
+/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG94_IN_SEL (BIT(7))
+#define GPIO_SIG94_IN_SEL_M (BIT(7))
+#define GPIO_SIG94_IN_SEL_V 0x1
+#define GPIO_SIG94_IN_SEL_S 7
+/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC94_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_V 0x1
+#define GPIO_FUNC94_IN_INV_SEL_S 6
+/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC94_IN_SEL 0x0000003F
+#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
+#define GPIO_FUNC94_IN_SEL_V 0x3F
+#define GPIO_FUNC94_IN_SEL_S 0
+
+#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ac)
+/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG95_IN_SEL (BIT(7))
+#define GPIO_SIG95_IN_SEL_M (BIT(7))
+#define GPIO_SIG95_IN_SEL_V 0x1
+#define GPIO_SIG95_IN_SEL_S 7
+/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC95_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_V 0x1
+#define GPIO_FUNC95_IN_INV_SEL_S 6
+/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC95_IN_SEL 0x0000003F
+#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
+#define GPIO_FUNC95_IN_SEL_V 0x3F
+#define GPIO_FUNC95_IN_SEL_S 0
+
+#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b0)
+/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG96_IN_SEL (BIT(7))
+#define GPIO_SIG96_IN_SEL_M (BIT(7))
+#define GPIO_SIG96_IN_SEL_V 0x1
+#define GPIO_SIG96_IN_SEL_S 7
+/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC96_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_V 0x1
+#define GPIO_FUNC96_IN_INV_SEL_S 6
+/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC96_IN_SEL 0x0000003F
+#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
+#define GPIO_FUNC96_IN_SEL_V 0x3F
+#define GPIO_FUNC96_IN_SEL_S 0
+
+#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b4)
+/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG97_IN_SEL (BIT(7))
+#define GPIO_SIG97_IN_SEL_M (BIT(7))
+#define GPIO_SIG97_IN_SEL_V 0x1
+#define GPIO_SIG97_IN_SEL_S 7
+/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC97_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_V 0x1
+#define GPIO_FUNC97_IN_INV_SEL_S 6
+/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC97_IN_SEL 0x0000003F
+#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
+#define GPIO_FUNC97_IN_SEL_V 0x3F
+#define GPIO_FUNC97_IN_SEL_S 0
+
+#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b8)
+/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG98_IN_SEL (BIT(7))
+#define GPIO_SIG98_IN_SEL_M (BIT(7))
+#define GPIO_SIG98_IN_SEL_V 0x1
+#define GPIO_SIG98_IN_SEL_S 7
+/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC98_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_V 0x1
+#define GPIO_FUNC98_IN_INV_SEL_S 6
+/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC98_IN_SEL 0x0000003F
+#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
+#define GPIO_FUNC98_IN_SEL_V 0x3F
+#define GPIO_FUNC98_IN_SEL_S 0
+
+#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02bc)
+/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG99_IN_SEL (BIT(7))
+#define GPIO_SIG99_IN_SEL_M (BIT(7))
+#define GPIO_SIG99_IN_SEL_V 0x1
+#define GPIO_SIG99_IN_SEL_S 7
+/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC99_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_V 0x1
+#define GPIO_FUNC99_IN_INV_SEL_S 6
+/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC99_IN_SEL 0x0000003F
+#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
+#define GPIO_FUNC99_IN_SEL_V 0x3F
+#define GPIO_FUNC99_IN_SEL_S 0
+
+#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c0)
+/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG100_IN_SEL (BIT(7))
+#define GPIO_SIG100_IN_SEL_M (BIT(7))
+#define GPIO_SIG100_IN_SEL_V 0x1
+#define GPIO_SIG100_IN_SEL_S 7
+/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC100_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_V 0x1
+#define GPIO_FUNC100_IN_INV_SEL_S 6
+/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC100_IN_SEL 0x0000003F
+#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
+#define GPIO_FUNC100_IN_SEL_V 0x3F
+#define GPIO_FUNC100_IN_SEL_S 0
+
+#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c4)
+/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG101_IN_SEL (BIT(7))
+#define GPIO_SIG101_IN_SEL_M (BIT(7))
+#define GPIO_SIG101_IN_SEL_V 0x1
+#define GPIO_SIG101_IN_SEL_S 7
+/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC101_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_V 0x1
+#define GPIO_FUNC101_IN_INV_SEL_S 6
+/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC101_IN_SEL 0x0000003F
+#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
+#define GPIO_FUNC101_IN_SEL_V 0x3F
+#define GPIO_FUNC101_IN_SEL_S 0
+
+#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c8)
+/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG102_IN_SEL (BIT(7))
+#define GPIO_SIG102_IN_SEL_M (BIT(7))
+#define GPIO_SIG102_IN_SEL_V 0x1
+#define GPIO_SIG102_IN_SEL_S 7
+/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC102_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_V 0x1
+#define GPIO_FUNC102_IN_INV_SEL_S 6
+/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC102_IN_SEL 0x0000003F
+#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
+#define GPIO_FUNC102_IN_SEL_V 0x3F
+#define GPIO_FUNC102_IN_SEL_S 0
+
+#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02cc)
+/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG103_IN_SEL (BIT(7))
+#define GPIO_SIG103_IN_SEL_M (BIT(7))
+#define GPIO_SIG103_IN_SEL_V 0x1
+#define GPIO_SIG103_IN_SEL_S 7
+/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC103_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_V 0x1
+#define GPIO_FUNC103_IN_INV_SEL_S 6
+/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC103_IN_SEL 0x0000003F
+#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
+#define GPIO_FUNC103_IN_SEL_V 0x3F
+#define GPIO_FUNC103_IN_SEL_S 0
+
+#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d0)
+/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG104_IN_SEL (BIT(7))
+#define GPIO_SIG104_IN_SEL_M (BIT(7))
+#define GPIO_SIG104_IN_SEL_V 0x1
+#define GPIO_SIG104_IN_SEL_S 7
+/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC104_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_V 0x1
+#define GPIO_FUNC104_IN_INV_SEL_S 6
+/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC104_IN_SEL 0x0000003F
+#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
+#define GPIO_FUNC104_IN_SEL_V 0x3F
+#define GPIO_FUNC104_IN_SEL_S 0
+
+#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d4)
+/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG105_IN_SEL (BIT(7))
+#define GPIO_SIG105_IN_SEL_M (BIT(7))
+#define GPIO_SIG105_IN_SEL_V 0x1
+#define GPIO_SIG105_IN_SEL_S 7
+/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC105_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_V 0x1
+#define GPIO_FUNC105_IN_INV_SEL_S 6
+/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC105_IN_SEL 0x0000003F
+#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
+#define GPIO_FUNC105_IN_SEL_V 0x3F
+#define GPIO_FUNC105_IN_SEL_S 0
+
+#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d8)
+/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG106_IN_SEL (BIT(7))
+#define GPIO_SIG106_IN_SEL_M (BIT(7))
+#define GPIO_SIG106_IN_SEL_V 0x1
+#define GPIO_SIG106_IN_SEL_S 7
+/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC106_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_V 0x1
+#define GPIO_FUNC106_IN_INV_SEL_S 6
+/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC106_IN_SEL 0x0000003F
+#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
+#define GPIO_FUNC106_IN_SEL_V 0x3F
+#define GPIO_FUNC106_IN_SEL_S 0
+
+#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02dc)
+/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG107_IN_SEL (BIT(7))
+#define GPIO_SIG107_IN_SEL_M (BIT(7))
+#define GPIO_SIG107_IN_SEL_V 0x1
+#define GPIO_SIG107_IN_SEL_S 7
+/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC107_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_V 0x1
+#define GPIO_FUNC107_IN_INV_SEL_S 6
+/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC107_IN_SEL 0x0000003F
+#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
+#define GPIO_FUNC107_IN_SEL_V 0x3F
+#define GPIO_FUNC107_IN_SEL_S 0
+
+#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e0)
+/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG108_IN_SEL (BIT(7))
+#define GPIO_SIG108_IN_SEL_M (BIT(7))
+#define GPIO_SIG108_IN_SEL_V 0x1
+#define GPIO_SIG108_IN_SEL_S 7
+/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC108_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_V 0x1
+#define GPIO_FUNC108_IN_INV_SEL_S 6
+/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC108_IN_SEL 0x0000003F
+#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
+#define GPIO_FUNC108_IN_SEL_V 0x3F
+#define GPIO_FUNC108_IN_SEL_S 0
+
+#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e4)
+/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG109_IN_SEL (BIT(7))
+#define GPIO_SIG109_IN_SEL_M (BIT(7))
+#define GPIO_SIG109_IN_SEL_V 0x1
+#define GPIO_SIG109_IN_SEL_S 7
+/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC109_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_V 0x1
+#define GPIO_FUNC109_IN_INV_SEL_S 6
+/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC109_IN_SEL 0x0000003F
+#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
+#define GPIO_FUNC109_IN_SEL_V 0x3F
+#define GPIO_FUNC109_IN_SEL_S 0
+
+#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e8)
+/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG110_IN_SEL (BIT(7))
+#define GPIO_SIG110_IN_SEL_M (BIT(7))
+#define GPIO_SIG110_IN_SEL_V 0x1
+#define GPIO_SIG110_IN_SEL_S 7
+/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC110_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_V 0x1
+#define GPIO_FUNC110_IN_INV_SEL_S 6
+/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC110_IN_SEL 0x0000003F
+#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
+#define GPIO_FUNC110_IN_SEL_V 0x3F
+#define GPIO_FUNC110_IN_SEL_S 0
+
+#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ec)
+/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG111_IN_SEL (BIT(7))
+#define GPIO_SIG111_IN_SEL_M (BIT(7))
+#define GPIO_SIG111_IN_SEL_V 0x1
+#define GPIO_SIG111_IN_SEL_S 7
+/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC111_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_V 0x1
+#define GPIO_FUNC111_IN_INV_SEL_S 6
+/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC111_IN_SEL 0x0000003F
+#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
+#define GPIO_FUNC111_IN_SEL_V 0x3F
+#define GPIO_FUNC111_IN_SEL_S 0
+
+#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f0)
+/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG112_IN_SEL (BIT(7))
+#define GPIO_SIG112_IN_SEL_M (BIT(7))
+#define GPIO_SIG112_IN_SEL_V 0x1
+#define GPIO_SIG112_IN_SEL_S 7
+/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC112_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_V 0x1
+#define GPIO_FUNC112_IN_INV_SEL_S 6
+/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC112_IN_SEL 0x0000003F
+#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
+#define GPIO_FUNC112_IN_SEL_V 0x3F
+#define GPIO_FUNC112_IN_SEL_S 0
+
+#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f4)
+/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG113_IN_SEL (BIT(7))
+#define GPIO_SIG113_IN_SEL_M (BIT(7))
+#define GPIO_SIG113_IN_SEL_V 0x1
+#define GPIO_SIG113_IN_SEL_S 7
+/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC113_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_V 0x1
+#define GPIO_FUNC113_IN_INV_SEL_S 6
+/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC113_IN_SEL 0x0000003F
+#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
+#define GPIO_FUNC113_IN_SEL_V 0x3F
+#define GPIO_FUNC113_IN_SEL_S 0
+
+#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f8)
+/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG114_IN_SEL (BIT(7))
+#define GPIO_SIG114_IN_SEL_M (BIT(7))
+#define GPIO_SIG114_IN_SEL_V 0x1
+#define GPIO_SIG114_IN_SEL_S 7
+/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC114_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_V 0x1
+#define GPIO_FUNC114_IN_INV_SEL_S 6
+/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC114_IN_SEL 0x0000003F
+#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
+#define GPIO_FUNC114_IN_SEL_V 0x3F
+#define GPIO_FUNC114_IN_SEL_S 0
+
+#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02fc)
+/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG115_IN_SEL (BIT(7))
+#define GPIO_SIG115_IN_SEL_M (BIT(7))
+#define GPIO_SIG115_IN_SEL_V 0x1
+#define GPIO_SIG115_IN_SEL_S 7
+/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC115_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC115_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC115_IN_INV_SEL_V 0x1
+#define GPIO_FUNC115_IN_INV_SEL_S 6
+/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC115_IN_SEL 0x0000003F
+#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
+#define GPIO_FUNC115_IN_SEL_V 0x3F
+#define GPIO_FUNC115_IN_SEL_S 0
+
+#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0300)
+/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG116_IN_SEL (BIT(7))
+#define GPIO_SIG116_IN_SEL_M (BIT(7))
+#define GPIO_SIG116_IN_SEL_V 0x1
+#define GPIO_SIG116_IN_SEL_S 7
+/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC116_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC116_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC116_IN_INV_SEL_V 0x1
+#define GPIO_FUNC116_IN_INV_SEL_S 6
+/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC116_IN_SEL 0x0000003F
+#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
+#define GPIO_FUNC116_IN_SEL_V 0x3F
+#define GPIO_FUNC116_IN_SEL_S 0
+
+#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0304)
+/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG117_IN_SEL (BIT(7))
+#define GPIO_SIG117_IN_SEL_M (BIT(7))
+#define GPIO_SIG117_IN_SEL_V 0x1
+#define GPIO_SIG117_IN_SEL_S 7
+/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC117_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_V 0x1
+#define GPIO_FUNC117_IN_INV_SEL_S 6
+/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC117_IN_SEL 0x0000003F
+#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
+#define GPIO_FUNC117_IN_SEL_V 0x3F
+#define GPIO_FUNC117_IN_SEL_S 0
+
+#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0308)
+/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG118_IN_SEL (BIT(7))
+#define GPIO_SIG118_IN_SEL_M (BIT(7))
+#define GPIO_SIG118_IN_SEL_V 0x1
+#define GPIO_SIG118_IN_SEL_S 7
+/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC118_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_V 0x1
+#define GPIO_FUNC118_IN_INV_SEL_S 6
+/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC118_IN_SEL 0x0000003F
+#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
+#define GPIO_FUNC118_IN_SEL_V 0x3F
+#define GPIO_FUNC118_IN_SEL_S 0
+
+#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x030c)
+/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG119_IN_SEL (BIT(7))
+#define GPIO_SIG119_IN_SEL_M (BIT(7))
+#define GPIO_SIG119_IN_SEL_V 0x1
+#define GPIO_SIG119_IN_SEL_S 7
+/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC119_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC119_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC119_IN_INV_SEL_V 0x1
+#define GPIO_FUNC119_IN_INV_SEL_S 6
+/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC119_IN_SEL 0x0000003F
+#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
+#define GPIO_FUNC119_IN_SEL_V 0x3F
+#define GPIO_FUNC119_IN_SEL_S 0
+
+#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0310)
+/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG120_IN_SEL (BIT(7))
+#define GPIO_SIG120_IN_SEL_M (BIT(7))
+#define GPIO_SIG120_IN_SEL_V 0x1
+#define GPIO_SIG120_IN_SEL_S 7
+/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC120_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC120_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC120_IN_INV_SEL_V 0x1
+#define GPIO_FUNC120_IN_INV_SEL_S 6
+/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC120_IN_SEL 0x0000003F
+#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
+#define GPIO_FUNC120_IN_SEL_V 0x3F
+#define GPIO_FUNC120_IN_SEL_S 0
+
+#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0314)
+/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG121_IN_SEL (BIT(7))
+#define GPIO_SIG121_IN_SEL_M (BIT(7))
+#define GPIO_SIG121_IN_SEL_V 0x1
+#define GPIO_SIG121_IN_SEL_S 7
+/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC121_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC121_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC121_IN_INV_SEL_V 0x1
+#define GPIO_FUNC121_IN_INV_SEL_S 6
+/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC121_IN_SEL 0x0000003F
+#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
+#define GPIO_FUNC121_IN_SEL_V 0x3F
+#define GPIO_FUNC121_IN_SEL_S 0
+
+#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0318)
+/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG122_IN_SEL (BIT(7))
+#define GPIO_SIG122_IN_SEL_M (BIT(7))
+#define GPIO_SIG122_IN_SEL_V 0x1
+#define GPIO_SIG122_IN_SEL_S 7
+/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC122_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC122_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC122_IN_INV_SEL_V 0x1
+#define GPIO_FUNC122_IN_INV_SEL_S 6
+/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC122_IN_SEL 0x0000003F
+#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
+#define GPIO_FUNC122_IN_SEL_V 0x3F
+#define GPIO_FUNC122_IN_SEL_S 0
+
+#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x031c)
+/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG123_IN_SEL (BIT(7))
+#define GPIO_SIG123_IN_SEL_M (BIT(7))
+#define GPIO_SIG123_IN_SEL_V 0x1
+#define GPIO_SIG123_IN_SEL_S 7
+/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC123_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC123_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC123_IN_INV_SEL_V 0x1
+#define GPIO_FUNC123_IN_INV_SEL_S 6
+/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC123_IN_SEL 0x0000003F
+#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
+#define GPIO_FUNC123_IN_SEL_V 0x3F
+#define GPIO_FUNC123_IN_SEL_S 0
+
+#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0320)
+/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG124_IN_SEL (BIT(7))
+#define GPIO_SIG124_IN_SEL_M (BIT(7))
+#define GPIO_SIG124_IN_SEL_V 0x1
+#define GPIO_SIG124_IN_SEL_S 7
+/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC124_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC124_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC124_IN_INV_SEL_V 0x1
+#define GPIO_FUNC124_IN_INV_SEL_S 6
+/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC124_IN_SEL 0x0000003F
+#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
+#define GPIO_FUNC124_IN_SEL_V 0x3F
+#define GPIO_FUNC124_IN_SEL_S 0
+
+#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0324)
+/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG125_IN_SEL (BIT(7))
+#define GPIO_SIG125_IN_SEL_M (BIT(7))
+#define GPIO_SIG125_IN_SEL_V 0x1
+#define GPIO_SIG125_IN_SEL_S 7
+/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC125_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC125_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC125_IN_INV_SEL_V 0x1
+#define GPIO_FUNC125_IN_INV_SEL_S 6
+/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC125_IN_SEL 0x0000003F
+#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
+#define GPIO_FUNC125_IN_SEL_V 0x3F
+#define GPIO_FUNC125_IN_SEL_S 0
+
+#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0328)
+/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG126_IN_SEL (BIT(7))
+#define GPIO_SIG126_IN_SEL_M (BIT(7))
+#define GPIO_SIG126_IN_SEL_V 0x1
+#define GPIO_SIG126_IN_SEL_S 7
+/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC126_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_V 0x1
+#define GPIO_FUNC126_IN_INV_SEL_S 6
+/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC126_IN_SEL 0x0000003F
+#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
+#define GPIO_FUNC126_IN_SEL_V 0x3F
+#define GPIO_FUNC126_IN_SEL_S 0
+
+#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x032c)
+/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG127_IN_SEL (BIT(7))
+#define GPIO_SIG127_IN_SEL_M (BIT(7))
+#define GPIO_SIG127_IN_SEL_V 0x1
+#define GPIO_SIG127_IN_SEL_S 7
+/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC127_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_V 0x1
+#define GPIO_FUNC127_IN_INV_SEL_S 6
+/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC127_IN_SEL 0x0000003F
+#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
+#define GPIO_FUNC127_IN_SEL_V 0x3F
+#define GPIO_FUNC127_IN_SEL_S 0
+
+#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0330)
+/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG128_IN_SEL (BIT(7))
+#define GPIO_SIG128_IN_SEL_M (BIT(7))
+#define GPIO_SIG128_IN_SEL_V 0x1
+#define GPIO_SIG128_IN_SEL_S 7
+/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC128_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_V 0x1
+#define GPIO_FUNC128_IN_INV_SEL_S 6
+/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC128_IN_SEL 0x0000003F
+#define GPIO_FUNC128_IN_SEL_M ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S))
+#define GPIO_FUNC128_IN_SEL_V 0x3F
+#define GPIO_FUNC128_IN_SEL_S 0
+
+#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0334)
+/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG129_IN_SEL (BIT(7))
+#define GPIO_SIG129_IN_SEL_M (BIT(7))
+#define GPIO_SIG129_IN_SEL_V 0x1
+#define GPIO_SIG129_IN_SEL_S 7
+/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC129_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_V 0x1
+#define GPIO_FUNC129_IN_INV_SEL_S 6
+/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC129_IN_SEL 0x0000003F
+#define GPIO_FUNC129_IN_SEL_M ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S))
+#define GPIO_FUNC129_IN_SEL_V 0x3F
+#define GPIO_FUNC129_IN_SEL_S 0
+
+#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0338)
+/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG130_IN_SEL (BIT(7))
+#define GPIO_SIG130_IN_SEL_M (BIT(7))
+#define GPIO_SIG130_IN_SEL_V 0x1
+#define GPIO_SIG130_IN_SEL_S 7
+/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC130_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_V 0x1
+#define GPIO_FUNC130_IN_INV_SEL_S 6
+/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC130_IN_SEL 0x0000003F
+#define GPIO_FUNC130_IN_SEL_M ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S))
+#define GPIO_FUNC130_IN_SEL_V 0x3F
+#define GPIO_FUNC130_IN_SEL_S 0
+
+#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x033c)
+/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG131_IN_SEL (BIT(7))
+#define GPIO_SIG131_IN_SEL_M (BIT(7))
+#define GPIO_SIG131_IN_SEL_V 0x1
+#define GPIO_SIG131_IN_SEL_S 7
+/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC131_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_V 0x1
+#define GPIO_FUNC131_IN_INV_SEL_S 6
+/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC131_IN_SEL 0x0000003F
+#define GPIO_FUNC131_IN_SEL_M ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S))
+#define GPIO_FUNC131_IN_SEL_V 0x3F
+#define GPIO_FUNC131_IN_SEL_S 0
+
+#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0340)
+/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG132_IN_SEL (BIT(7))
+#define GPIO_SIG132_IN_SEL_M (BIT(7))
+#define GPIO_SIG132_IN_SEL_V 0x1
+#define GPIO_SIG132_IN_SEL_S 7
+/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC132_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_V 0x1
+#define GPIO_FUNC132_IN_INV_SEL_S 6
+/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC132_IN_SEL 0x0000003F
+#define GPIO_FUNC132_IN_SEL_M ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S))
+#define GPIO_FUNC132_IN_SEL_V 0x3F
+#define GPIO_FUNC132_IN_SEL_S 0
+
+#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0344)
+/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG133_IN_SEL (BIT(7))
+#define GPIO_SIG133_IN_SEL_M (BIT(7))
+#define GPIO_SIG133_IN_SEL_V 0x1
+#define GPIO_SIG133_IN_SEL_S 7
+/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC133_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_V 0x1
+#define GPIO_FUNC133_IN_INV_SEL_S 6
+/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC133_IN_SEL 0x0000003F
+#define GPIO_FUNC133_IN_SEL_M ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S))
+#define GPIO_FUNC133_IN_SEL_V 0x3F
+#define GPIO_FUNC133_IN_SEL_S 0
+
+#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0348)
+/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG134_IN_SEL (BIT(7))
+#define GPIO_SIG134_IN_SEL_M (BIT(7))
+#define GPIO_SIG134_IN_SEL_V 0x1
+#define GPIO_SIG134_IN_SEL_S 7
+/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC134_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_V 0x1
+#define GPIO_FUNC134_IN_INV_SEL_S 6
+/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC134_IN_SEL 0x0000003F
+#define GPIO_FUNC134_IN_SEL_M ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S))
+#define GPIO_FUNC134_IN_SEL_V 0x3F
+#define GPIO_FUNC134_IN_SEL_S 0
+
+#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x034c)
+/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG135_IN_SEL (BIT(7))
+#define GPIO_SIG135_IN_SEL_M (BIT(7))
+#define GPIO_SIG135_IN_SEL_V 0x1
+#define GPIO_SIG135_IN_SEL_S 7
+/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC135_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_V 0x1
+#define GPIO_FUNC135_IN_INV_SEL_S 6
+/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC135_IN_SEL 0x0000003F
+#define GPIO_FUNC135_IN_SEL_M ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S))
+#define GPIO_FUNC135_IN_SEL_V 0x3F
+#define GPIO_FUNC135_IN_SEL_S 0
+
+#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0350)
+/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG136_IN_SEL (BIT(7))
+#define GPIO_SIG136_IN_SEL_M (BIT(7))
+#define GPIO_SIG136_IN_SEL_V 0x1
+#define GPIO_SIG136_IN_SEL_S 7
+/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC136_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_V 0x1
+#define GPIO_FUNC136_IN_INV_SEL_S 6
+/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC136_IN_SEL 0x0000003F
+#define GPIO_FUNC136_IN_SEL_M ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S))
+#define GPIO_FUNC136_IN_SEL_V 0x3F
+#define GPIO_FUNC136_IN_SEL_S 0
+
+#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0354)
+/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG137_IN_SEL (BIT(7))
+#define GPIO_SIG137_IN_SEL_M (BIT(7))
+#define GPIO_SIG137_IN_SEL_V 0x1
+#define GPIO_SIG137_IN_SEL_S 7
+/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC137_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_V 0x1
+#define GPIO_FUNC137_IN_INV_SEL_S 6
+/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC137_IN_SEL 0x0000003F
+#define GPIO_FUNC137_IN_SEL_M ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S))
+#define GPIO_FUNC137_IN_SEL_V 0x3F
+#define GPIO_FUNC137_IN_SEL_S 0
+
+#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0358)
+/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG138_IN_SEL (BIT(7))
+#define GPIO_SIG138_IN_SEL_M (BIT(7))
+#define GPIO_SIG138_IN_SEL_V 0x1
+#define GPIO_SIG138_IN_SEL_S 7
+/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC138_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC138_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC138_IN_INV_SEL_V 0x1
+#define GPIO_FUNC138_IN_INV_SEL_S 6
+/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC138_IN_SEL 0x0000003F
+#define GPIO_FUNC138_IN_SEL_M ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S))
+#define GPIO_FUNC138_IN_SEL_V 0x3F
+#define GPIO_FUNC138_IN_SEL_S 0
+
+#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x035c)
+/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG139_IN_SEL (BIT(7))
+#define GPIO_SIG139_IN_SEL_M (BIT(7))
+#define GPIO_SIG139_IN_SEL_V 0x1
+#define GPIO_SIG139_IN_SEL_S 7
+/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC139_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC139_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC139_IN_INV_SEL_V 0x1
+#define GPIO_FUNC139_IN_INV_SEL_S 6
+/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC139_IN_SEL 0x0000003F
+#define GPIO_FUNC139_IN_SEL_M ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S))
+#define GPIO_FUNC139_IN_SEL_V 0x3F
+#define GPIO_FUNC139_IN_SEL_S 0
+
+#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0360)
+/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG140_IN_SEL (BIT(7))
+#define GPIO_SIG140_IN_SEL_M (BIT(7))
+#define GPIO_SIG140_IN_SEL_V 0x1
+#define GPIO_SIG140_IN_SEL_S 7
+/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC140_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_V 0x1
+#define GPIO_FUNC140_IN_INV_SEL_S 6
+/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC140_IN_SEL 0x0000003F
+#define GPIO_FUNC140_IN_SEL_M ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S))
+#define GPIO_FUNC140_IN_SEL_V 0x3F
+#define GPIO_FUNC140_IN_SEL_S 0
+
+#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0364)
+/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG141_IN_SEL (BIT(7))
+#define GPIO_SIG141_IN_SEL_M (BIT(7))
+#define GPIO_SIG141_IN_SEL_V 0x1
+#define GPIO_SIG141_IN_SEL_S 7
+/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC141_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_V 0x1
+#define GPIO_FUNC141_IN_INV_SEL_S 6
+/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC141_IN_SEL 0x0000003F
+#define GPIO_FUNC141_IN_SEL_M ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S))
+#define GPIO_FUNC141_IN_SEL_V 0x3F
+#define GPIO_FUNC141_IN_SEL_S 0
+
+#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0368)
+/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG142_IN_SEL (BIT(7))
+#define GPIO_SIG142_IN_SEL_M (BIT(7))
+#define GPIO_SIG142_IN_SEL_V 0x1
+#define GPIO_SIG142_IN_SEL_S 7
+/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC142_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_V 0x1
+#define GPIO_FUNC142_IN_INV_SEL_S 6
+/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC142_IN_SEL 0x0000003F
+#define GPIO_FUNC142_IN_SEL_M ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S))
+#define GPIO_FUNC142_IN_SEL_V 0x3F
+#define GPIO_FUNC142_IN_SEL_S 0
+
+#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x036c)
+/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG143_IN_SEL (BIT(7))
+#define GPIO_SIG143_IN_SEL_M (BIT(7))
+#define GPIO_SIG143_IN_SEL_V 0x1
+#define GPIO_SIG143_IN_SEL_S 7
+/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC143_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_V 0x1
+#define GPIO_FUNC143_IN_INV_SEL_S 6
+/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC143_IN_SEL 0x0000003F
+#define GPIO_FUNC143_IN_SEL_M ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S))
+#define GPIO_FUNC143_IN_SEL_V 0x3F
+#define GPIO_FUNC143_IN_SEL_S 0
+
+#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0370)
+/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG144_IN_SEL (BIT(7))
+#define GPIO_SIG144_IN_SEL_M (BIT(7))
+#define GPIO_SIG144_IN_SEL_V 0x1
+#define GPIO_SIG144_IN_SEL_S 7
+/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC144_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_V 0x1
+#define GPIO_FUNC144_IN_INV_SEL_S 6
+/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC144_IN_SEL 0x0000003F
+#define GPIO_FUNC144_IN_SEL_M ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S))
+#define GPIO_FUNC144_IN_SEL_V 0x3F
+#define GPIO_FUNC144_IN_SEL_S 0
+
+#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0374)
+/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG145_IN_SEL (BIT(7))
+#define GPIO_SIG145_IN_SEL_M (BIT(7))
+#define GPIO_SIG145_IN_SEL_V 0x1
+#define GPIO_SIG145_IN_SEL_S 7
+/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC145_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_V 0x1
+#define GPIO_FUNC145_IN_INV_SEL_S 6
+/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC145_IN_SEL 0x0000003F
+#define GPIO_FUNC145_IN_SEL_M ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S))
+#define GPIO_FUNC145_IN_SEL_V 0x3F
+#define GPIO_FUNC145_IN_SEL_S 0
+
+#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0378)
+/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG146_IN_SEL (BIT(7))
+#define GPIO_SIG146_IN_SEL_M (BIT(7))
+#define GPIO_SIG146_IN_SEL_V 0x1
+#define GPIO_SIG146_IN_SEL_S 7
+/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC146_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_V 0x1
+#define GPIO_FUNC146_IN_INV_SEL_S 6
+/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC146_IN_SEL 0x0000003F
+#define GPIO_FUNC146_IN_SEL_M ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S))
+#define GPIO_FUNC146_IN_SEL_V 0x3F
+#define GPIO_FUNC146_IN_SEL_S 0
+
+#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x037c)
+/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG147_IN_SEL (BIT(7))
+#define GPIO_SIG147_IN_SEL_M (BIT(7))
+#define GPIO_SIG147_IN_SEL_V 0x1
+#define GPIO_SIG147_IN_SEL_S 7
+/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC147_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_V 0x1
+#define GPIO_FUNC147_IN_INV_SEL_S 6
+/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC147_IN_SEL 0x0000003F
+#define GPIO_FUNC147_IN_SEL_M ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S))
+#define GPIO_FUNC147_IN_SEL_V 0x3F
+#define GPIO_FUNC147_IN_SEL_S 0
+
+#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0380)
+/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG148_IN_SEL (BIT(7))
+#define GPIO_SIG148_IN_SEL_M (BIT(7))
+#define GPIO_SIG148_IN_SEL_V 0x1
+#define GPIO_SIG148_IN_SEL_S 7
+/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC148_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_V 0x1
+#define GPIO_FUNC148_IN_INV_SEL_S 6
+/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC148_IN_SEL 0x0000003F
+#define GPIO_FUNC148_IN_SEL_M ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S))
+#define GPIO_FUNC148_IN_SEL_V 0x3F
+#define GPIO_FUNC148_IN_SEL_S 0
+
+#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0384)
+/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG149_IN_SEL (BIT(7))
+#define GPIO_SIG149_IN_SEL_M (BIT(7))
+#define GPIO_SIG149_IN_SEL_V 0x1
+#define GPIO_SIG149_IN_SEL_S 7
+/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC149_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_V 0x1
+#define GPIO_FUNC149_IN_INV_SEL_S 6
+/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC149_IN_SEL 0x0000003F
+#define GPIO_FUNC149_IN_SEL_M ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S))
+#define GPIO_FUNC149_IN_SEL_V 0x3F
+#define GPIO_FUNC149_IN_SEL_S 0
+
+#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0388)
+/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG150_IN_SEL (BIT(7))
+#define GPIO_SIG150_IN_SEL_M (BIT(7))
+#define GPIO_SIG150_IN_SEL_V 0x1
+#define GPIO_SIG150_IN_SEL_S 7
+/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC150_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_V 0x1
+#define GPIO_FUNC150_IN_INV_SEL_S 6
+/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC150_IN_SEL 0x0000003F
+#define GPIO_FUNC150_IN_SEL_M ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S))
+#define GPIO_FUNC150_IN_SEL_V 0x3F
+#define GPIO_FUNC150_IN_SEL_S 0
+
+#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x038c)
+/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG151_IN_SEL (BIT(7))
+#define GPIO_SIG151_IN_SEL_M (BIT(7))
+#define GPIO_SIG151_IN_SEL_V 0x1
+#define GPIO_SIG151_IN_SEL_S 7
+/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC151_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_V 0x1
+#define GPIO_FUNC151_IN_INV_SEL_S 6
+/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC151_IN_SEL 0x0000003F
+#define GPIO_FUNC151_IN_SEL_M ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S))
+#define GPIO_FUNC151_IN_SEL_V 0x3F
+#define GPIO_FUNC151_IN_SEL_S 0
+
+#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0390)
+/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG152_IN_SEL (BIT(7))
+#define GPIO_SIG152_IN_SEL_M (BIT(7))
+#define GPIO_SIG152_IN_SEL_V 0x1
+#define GPIO_SIG152_IN_SEL_S 7
+/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC152_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_V 0x1
+#define GPIO_FUNC152_IN_INV_SEL_S 6
+/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC152_IN_SEL 0x0000003F
+#define GPIO_FUNC152_IN_SEL_M ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S))
+#define GPIO_FUNC152_IN_SEL_V 0x3F
+#define GPIO_FUNC152_IN_SEL_S 0
+
+#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0394)
+/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG153_IN_SEL (BIT(7))
+#define GPIO_SIG153_IN_SEL_M (BIT(7))
+#define GPIO_SIG153_IN_SEL_V 0x1
+#define GPIO_SIG153_IN_SEL_S 7
+/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC153_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_V 0x1
+#define GPIO_FUNC153_IN_INV_SEL_S 6
+/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC153_IN_SEL 0x0000003F
+#define GPIO_FUNC153_IN_SEL_M ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S))
+#define GPIO_FUNC153_IN_SEL_V 0x3F
+#define GPIO_FUNC153_IN_SEL_S 0
+
+#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0398)
+/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG154_IN_SEL (BIT(7))
+#define GPIO_SIG154_IN_SEL_M (BIT(7))
+#define GPIO_SIG154_IN_SEL_V 0x1
+#define GPIO_SIG154_IN_SEL_S 7
+/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC154_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_V 0x1
+#define GPIO_FUNC154_IN_INV_SEL_S 6
+/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC154_IN_SEL 0x0000003F
+#define GPIO_FUNC154_IN_SEL_M ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S))
+#define GPIO_FUNC154_IN_SEL_V 0x3F
+#define GPIO_FUNC154_IN_SEL_S 0
+
+#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x039c)
+/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG155_IN_SEL (BIT(7))
+#define GPIO_SIG155_IN_SEL_M (BIT(7))
+#define GPIO_SIG155_IN_SEL_V 0x1
+#define GPIO_SIG155_IN_SEL_S 7
+/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC155_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_V 0x1
+#define GPIO_FUNC155_IN_INV_SEL_S 6
+/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC155_IN_SEL 0x0000003F
+#define GPIO_FUNC155_IN_SEL_M ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S))
+#define GPIO_FUNC155_IN_SEL_V 0x3F
+#define GPIO_FUNC155_IN_SEL_S 0
+
+#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a0)
+/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG156_IN_SEL (BIT(7))
+#define GPIO_SIG156_IN_SEL_M (BIT(7))
+#define GPIO_SIG156_IN_SEL_V 0x1
+#define GPIO_SIG156_IN_SEL_S 7
+/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC156_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_V 0x1
+#define GPIO_FUNC156_IN_INV_SEL_S 6
+/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC156_IN_SEL 0x0000003F
+#define GPIO_FUNC156_IN_SEL_M ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S))
+#define GPIO_FUNC156_IN_SEL_V 0x3F
+#define GPIO_FUNC156_IN_SEL_S 0
+
+#define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a4)
+/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG157_IN_SEL (BIT(7))
+#define GPIO_SIG157_IN_SEL_M (BIT(7))
+#define GPIO_SIG157_IN_SEL_V 0x1
+#define GPIO_SIG157_IN_SEL_S 7
+/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC157_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC157_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC157_IN_INV_SEL_V 0x1
+#define GPIO_FUNC157_IN_INV_SEL_S 6
+/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC157_IN_SEL 0x0000003F
+#define GPIO_FUNC157_IN_SEL_M ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S))
+#define GPIO_FUNC157_IN_SEL_V 0x3F
+#define GPIO_FUNC157_IN_SEL_S 0
+
+#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a8)
+/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG158_IN_SEL (BIT(7))
+#define GPIO_SIG158_IN_SEL_M (BIT(7))
+#define GPIO_SIG158_IN_SEL_V 0x1
+#define GPIO_SIG158_IN_SEL_S 7
+/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC158_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_V 0x1
+#define GPIO_FUNC158_IN_INV_SEL_S 6
+/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC158_IN_SEL 0x0000003F
+#define GPIO_FUNC158_IN_SEL_M ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S))
+#define GPIO_FUNC158_IN_SEL_V 0x3F
+#define GPIO_FUNC158_IN_SEL_S 0
+
+#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ac)
+/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG159_IN_SEL (BIT(7))
+#define GPIO_SIG159_IN_SEL_M (BIT(7))
+#define GPIO_SIG159_IN_SEL_V 0x1
+#define GPIO_SIG159_IN_SEL_S 7
+/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC159_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_V 0x1
+#define GPIO_FUNC159_IN_INV_SEL_S 6
+/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC159_IN_SEL 0x0000003F
+#define GPIO_FUNC159_IN_SEL_M ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S))
+#define GPIO_FUNC159_IN_SEL_V 0x3F
+#define GPIO_FUNC159_IN_SEL_S 0
+
+#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b0)
+/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG160_IN_SEL (BIT(7))
+#define GPIO_SIG160_IN_SEL_M (BIT(7))
+#define GPIO_SIG160_IN_SEL_V 0x1
+#define GPIO_SIG160_IN_SEL_S 7
+/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC160_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_V 0x1
+#define GPIO_FUNC160_IN_INV_SEL_S 6
+/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC160_IN_SEL 0x0000003F
+#define GPIO_FUNC160_IN_SEL_M ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S))
+#define GPIO_FUNC160_IN_SEL_V 0x3F
+#define GPIO_FUNC160_IN_SEL_S 0
+
+#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b4)
+/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG161_IN_SEL (BIT(7))
+#define GPIO_SIG161_IN_SEL_M (BIT(7))
+#define GPIO_SIG161_IN_SEL_V 0x1
+#define GPIO_SIG161_IN_SEL_S 7
+/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC161_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_V 0x1
+#define GPIO_FUNC161_IN_INV_SEL_S 6
+/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC161_IN_SEL 0x0000003F
+#define GPIO_FUNC161_IN_SEL_M ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S))
+#define GPIO_FUNC161_IN_SEL_V 0x3F
+#define GPIO_FUNC161_IN_SEL_S 0
+
+#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b8)
+/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG162_IN_SEL (BIT(7))
+#define GPIO_SIG162_IN_SEL_M (BIT(7))
+#define GPIO_SIG162_IN_SEL_V 0x1
+#define GPIO_SIG162_IN_SEL_S 7
+/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC162_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_V 0x1
+#define GPIO_FUNC162_IN_INV_SEL_S 6
+/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC162_IN_SEL 0x0000003F
+#define GPIO_FUNC162_IN_SEL_M ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S))
+#define GPIO_FUNC162_IN_SEL_V 0x3F
+#define GPIO_FUNC162_IN_SEL_S 0
+
+#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03bc)
+/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG163_IN_SEL (BIT(7))
+#define GPIO_SIG163_IN_SEL_M (BIT(7))
+#define GPIO_SIG163_IN_SEL_V 0x1
+#define GPIO_SIG163_IN_SEL_S 7
+/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC163_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_V 0x1
+#define GPIO_FUNC163_IN_INV_SEL_S 6
+/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC163_IN_SEL 0x0000003F
+#define GPIO_FUNC163_IN_SEL_M ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S))
+#define GPIO_FUNC163_IN_SEL_V 0x3F
+#define GPIO_FUNC163_IN_SEL_S 0
+
+#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c0)
+/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG164_IN_SEL (BIT(7))
+#define GPIO_SIG164_IN_SEL_M (BIT(7))
+#define GPIO_SIG164_IN_SEL_V 0x1
+#define GPIO_SIG164_IN_SEL_S 7
+/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC164_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_V 0x1
+#define GPIO_FUNC164_IN_INV_SEL_S 6
+/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC164_IN_SEL 0x0000003F
+#define GPIO_FUNC164_IN_SEL_M ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S))
+#define GPIO_FUNC164_IN_SEL_V 0x3F
+#define GPIO_FUNC164_IN_SEL_S 0
+
+#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c4)
+/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG165_IN_SEL (BIT(7))
+#define GPIO_SIG165_IN_SEL_M (BIT(7))
+#define GPIO_SIG165_IN_SEL_V 0x1
+#define GPIO_SIG165_IN_SEL_S 7
+/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC165_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_V 0x1
+#define GPIO_FUNC165_IN_INV_SEL_S 6
+/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC165_IN_SEL 0x0000003F
+#define GPIO_FUNC165_IN_SEL_M ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S))
+#define GPIO_FUNC165_IN_SEL_V 0x3F
+#define GPIO_FUNC165_IN_SEL_S 0
+
+#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c8)
+/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG166_IN_SEL (BIT(7))
+#define GPIO_SIG166_IN_SEL_M (BIT(7))
+#define GPIO_SIG166_IN_SEL_V 0x1
+#define GPIO_SIG166_IN_SEL_S 7
+/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC166_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_V 0x1
+#define GPIO_FUNC166_IN_INV_SEL_S 6
+/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC166_IN_SEL 0x0000003F
+#define GPIO_FUNC166_IN_SEL_M ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S))
+#define GPIO_FUNC166_IN_SEL_V 0x3F
+#define GPIO_FUNC166_IN_SEL_S 0
+
+#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03cc)
+/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG167_IN_SEL (BIT(7))
+#define GPIO_SIG167_IN_SEL_M (BIT(7))
+#define GPIO_SIG167_IN_SEL_V 0x1
+#define GPIO_SIG167_IN_SEL_S 7
+/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC167_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_V 0x1
+#define GPIO_FUNC167_IN_INV_SEL_S 6
+/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC167_IN_SEL 0x0000003F
+#define GPIO_FUNC167_IN_SEL_M ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S))
+#define GPIO_FUNC167_IN_SEL_V 0x3F
+#define GPIO_FUNC167_IN_SEL_S 0
+
+#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d0)
+/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG168_IN_SEL (BIT(7))
+#define GPIO_SIG168_IN_SEL_M (BIT(7))
+#define GPIO_SIG168_IN_SEL_V 0x1
+#define GPIO_SIG168_IN_SEL_S 7
+/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC168_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_V 0x1
+#define GPIO_FUNC168_IN_INV_SEL_S 6
+/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC168_IN_SEL 0x0000003F
+#define GPIO_FUNC168_IN_SEL_M ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S))
+#define GPIO_FUNC168_IN_SEL_V 0x3F
+#define GPIO_FUNC168_IN_SEL_S 0
+
+#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d4)
+/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG169_IN_SEL (BIT(7))
+#define GPIO_SIG169_IN_SEL_M (BIT(7))
+#define GPIO_SIG169_IN_SEL_V 0x1
+#define GPIO_SIG169_IN_SEL_S 7
+/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC169_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_V 0x1
+#define GPIO_FUNC169_IN_INV_SEL_S 6
+/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC169_IN_SEL 0x0000003F
+#define GPIO_FUNC169_IN_SEL_M ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S))
+#define GPIO_FUNC169_IN_SEL_V 0x3F
+#define GPIO_FUNC169_IN_SEL_S 0
+
+#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d8)
+/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG170_IN_SEL (BIT(7))
+#define GPIO_SIG170_IN_SEL_M (BIT(7))
+#define GPIO_SIG170_IN_SEL_V 0x1
+#define GPIO_SIG170_IN_SEL_S 7
+/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC170_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_V 0x1
+#define GPIO_FUNC170_IN_INV_SEL_S 6
+/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC170_IN_SEL 0x0000003F
+#define GPIO_FUNC170_IN_SEL_M ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S))
+#define GPIO_FUNC170_IN_SEL_V 0x3F
+#define GPIO_FUNC170_IN_SEL_S 0
+
+#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03dc)
+/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG171_IN_SEL (BIT(7))
+#define GPIO_SIG171_IN_SEL_M (BIT(7))
+#define GPIO_SIG171_IN_SEL_V 0x1
+#define GPIO_SIG171_IN_SEL_S 7
+/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC171_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_V 0x1
+#define GPIO_FUNC171_IN_INV_SEL_S 6
+/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC171_IN_SEL 0x0000003F
+#define GPIO_FUNC171_IN_SEL_M ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S))
+#define GPIO_FUNC171_IN_SEL_V 0x3F
+#define GPIO_FUNC171_IN_SEL_S 0
+
+#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e0)
+/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG172_IN_SEL (BIT(7))
+#define GPIO_SIG172_IN_SEL_M (BIT(7))
+#define GPIO_SIG172_IN_SEL_V 0x1
+#define GPIO_SIG172_IN_SEL_S 7
+/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC172_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_V 0x1
+#define GPIO_FUNC172_IN_INV_SEL_S 6
+/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC172_IN_SEL 0x0000003F
+#define GPIO_FUNC172_IN_SEL_M ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S))
+#define GPIO_FUNC172_IN_SEL_V 0x3F
+#define GPIO_FUNC172_IN_SEL_S 0
+
+#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e4)
+/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG173_IN_SEL (BIT(7))
+#define GPIO_SIG173_IN_SEL_M (BIT(7))
+#define GPIO_SIG173_IN_SEL_V 0x1
+#define GPIO_SIG173_IN_SEL_S 7
+/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC173_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_V 0x1
+#define GPIO_FUNC173_IN_INV_SEL_S 6
+/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC173_IN_SEL 0x0000003F
+#define GPIO_FUNC173_IN_SEL_M ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S))
+#define GPIO_FUNC173_IN_SEL_V 0x3F
+#define GPIO_FUNC173_IN_SEL_S 0
+
+#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e8)
+/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG174_IN_SEL (BIT(7))
+#define GPIO_SIG174_IN_SEL_M (BIT(7))
+#define GPIO_SIG174_IN_SEL_V 0x1
+#define GPIO_SIG174_IN_SEL_S 7
+/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC174_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_V 0x1
+#define GPIO_FUNC174_IN_INV_SEL_S 6
+/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC174_IN_SEL 0x0000003F
+#define GPIO_FUNC174_IN_SEL_M ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S))
+#define GPIO_FUNC174_IN_SEL_V 0x3F
+#define GPIO_FUNC174_IN_SEL_S 0
+
+#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ec)
+/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG175_IN_SEL (BIT(7))
+#define GPIO_SIG175_IN_SEL_M (BIT(7))
+#define GPIO_SIG175_IN_SEL_V 0x1
+#define GPIO_SIG175_IN_SEL_S 7
+/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC175_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_V 0x1
+#define GPIO_FUNC175_IN_INV_SEL_S 6
+/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC175_IN_SEL 0x0000003F
+#define GPIO_FUNC175_IN_SEL_M ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S))
+#define GPIO_FUNC175_IN_SEL_V 0x3F
+#define GPIO_FUNC175_IN_SEL_S 0
+
+#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f0)
+/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG176_IN_SEL (BIT(7))
+#define GPIO_SIG176_IN_SEL_M (BIT(7))
+#define GPIO_SIG176_IN_SEL_V 0x1
+#define GPIO_SIG176_IN_SEL_S 7
+/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC176_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_V 0x1
+#define GPIO_FUNC176_IN_INV_SEL_S 6
+/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC176_IN_SEL 0x0000003F
+#define GPIO_FUNC176_IN_SEL_M ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S))
+#define GPIO_FUNC176_IN_SEL_V 0x3F
+#define GPIO_FUNC176_IN_SEL_S 0
+
+#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f4)
+/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG177_IN_SEL (BIT(7))
+#define GPIO_SIG177_IN_SEL_M (BIT(7))
+#define GPIO_SIG177_IN_SEL_V 0x1
+#define GPIO_SIG177_IN_SEL_S 7
+/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC177_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_V 0x1
+#define GPIO_FUNC177_IN_INV_SEL_S 6
+/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC177_IN_SEL 0x0000003F
+#define GPIO_FUNC177_IN_SEL_M ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S))
+#define GPIO_FUNC177_IN_SEL_V 0x3F
+#define GPIO_FUNC177_IN_SEL_S 0
+
+#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f8)
+/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG178_IN_SEL (BIT(7))
+#define GPIO_SIG178_IN_SEL_M (BIT(7))
+#define GPIO_SIG178_IN_SEL_V 0x1
+#define GPIO_SIG178_IN_SEL_S 7
+/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC178_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_V 0x1
+#define GPIO_FUNC178_IN_INV_SEL_S 6
+/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC178_IN_SEL 0x0000003F
+#define GPIO_FUNC178_IN_SEL_M ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S))
+#define GPIO_FUNC178_IN_SEL_V 0x3F
+#define GPIO_FUNC178_IN_SEL_S 0
+
+#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03fc)
+/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG179_IN_SEL (BIT(7))
+#define GPIO_SIG179_IN_SEL_M (BIT(7))
+#define GPIO_SIG179_IN_SEL_V 0x1
+#define GPIO_SIG179_IN_SEL_S 7
+/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC179_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_V 0x1
+#define GPIO_FUNC179_IN_INV_SEL_S 6
+/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC179_IN_SEL 0x0000003F
+#define GPIO_FUNC179_IN_SEL_M ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S))
+#define GPIO_FUNC179_IN_SEL_V 0x3F
+#define GPIO_FUNC179_IN_SEL_S 0
+
+#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0400)
+/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG180_IN_SEL (BIT(7))
+#define GPIO_SIG180_IN_SEL_M (BIT(7))
+#define GPIO_SIG180_IN_SEL_V 0x1
+#define GPIO_SIG180_IN_SEL_S 7
+/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC180_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_V 0x1
+#define GPIO_FUNC180_IN_INV_SEL_S 6
+/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC180_IN_SEL 0x0000003F
+#define GPIO_FUNC180_IN_SEL_M ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S))
+#define GPIO_FUNC180_IN_SEL_V 0x3F
+#define GPIO_FUNC180_IN_SEL_S 0
+
+#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0404)
+/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG181_IN_SEL (BIT(7))
+#define GPIO_SIG181_IN_SEL_M (BIT(7))
+#define GPIO_SIG181_IN_SEL_V 0x1
+#define GPIO_SIG181_IN_SEL_S 7
+/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC181_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_V 0x1
+#define GPIO_FUNC181_IN_INV_SEL_S 6
+/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC181_IN_SEL 0x0000003F
+#define GPIO_FUNC181_IN_SEL_M ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S))
+#define GPIO_FUNC181_IN_SEL_V 0x3F
+#define GPIO_FUNC181_IN_SEL_S 0
+
+#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0408)
+/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG182_IN_SEL (BIT(7))
+#define GPIO_SIG182_IN_SEL_M (BIT(7))
+#define GPIO_SIG182_IN_SEL_V 0x1
+#define GPIO_SIG182_IN_SEL_S 7
+/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC182_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_V 0x1
+#define GPIO_FUNC182_IN_INV_SEL_S 6
+/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC182_IN_SEL 0x0000003F
+#define GPIO_FUNC182_IN_SEL_M ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S))
+#define GPIO_FUNC182_IN_SEL_V 0x3F
+#define GPIO_FUNC182_IN_SEL_S 0
+
+#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x040c)
+/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG183_IN_SEL (BIT(7))
+#define GPIO_SIG183_IN_SEL_M (BIT(7))
+#define GPIO_SIG183_IN_SEL_V 0x1
+#define GPIO_SIG183_IN_SEL_S 7
+/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC183_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_V 0x1
+#define GPIO_FUNC183_IN_INV_SEL_S 6
+/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC183_IN_SEL 0x0000003F
+#define GPIO_FUNC183_IN_SEL_M ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S))
+#define GPIO_FUNC183_IN_SEL_V 0x3F
+#define GPIO_FUNC183_IN_SEL_S 0
+
+#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0410)
+/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG184_IN_SEL (BIT(7))
+#define GPIO_SIG184_IN_SEL_M (BIT(7))
+#define GPIO_SIG184_IN_SEL_V 0x1
+#define GPIO_SIG184_IN_SEL_S 7
+/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC184_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_V 0x1
+#define GPIO_FUNC184_IN_INV_SEL_S 6
+/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC184_IN_SEL 0x0000003F
+#define GPIO_FUNC184_IN_SEL_M ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S))
+#define GPIO_FUNC184_IN_SEL_V 0x3F
+#define GPIO_FUNC184_IN_SEL_S 0
+
+#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0414)
+/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG185_IN_SEL (BIT(7))
+#define GPIO_SIG185_IN_SEL_M (BIT(7))
+#define GPIO_SIG185_IN_SEL_V 0x1
+#define GPIO_SIG185_IN_SEL_S 7
+/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC185_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_V 0x1
+#define GPIO_FUNC185_IN_INV_SEL_S 6
+/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC185_IN_SEL 0x0000003F
+#define GPIO_FUNC185_IN_SEL_M ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S))
+#define GPIO_FUNC185_IN_SEL_V 0x3F
+#define GPIO_FUNC185_IN_SEL_S 0
+
+#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0418)
+/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG186_IN_SEL (BIT(7))
+#define GPIO_SIG186_IN_SEL_M (BIT(7))
+#define GPIO_SIG186_IN_SEL_V 0x1
+#define GPIO_SIG186_IN_SEL_S 7
+/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC186_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_V 0x1
+#define GPIO_FUNC186_IN_INV_SEL_S 6
+/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC186_IN_SEL 0x0000003F
+#define GPIO_FUNC186_IN_SEL_M ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S))
+#define GPIO_FUNC186_IN_SEL_V 0x3F
+#define GPIO_FUNC186_IN_SEL_S 0
+
+#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x041c)
+/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG187_IN_SEL (BIT(7))
+#define GPIO_SIG187_IN_SEL_M (BIT(7))
+#define GPIO_SIG187_IN_SEL_V 0x1
+#define GPIO_SIG187_IN_SEL_S 7
+/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC187_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_V 0x1
+#define GPIO_FUNC187_IN_INV_SEL_S 6
+/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC187_IN_SEL 0x0000003F
+#define GPIO_FUNC187_IN_SEL_M ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S))
+#define GPIO_FUNC187_IN_SEL_V 0x3F
+#define GPIO_FUNC187_IN_SEL_S 0
+
+#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0420)
+/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG188_IN_SEL (BIT(7))
+#define GPIO_SIG188_IN_SEL_M (BIT(7))
+#define GPIO_SIG188_IN_SEL_V 0x1
+#define GPIO_SIG188_IN_SEL_S 7
+/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC188_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_V 0x1
+#define GPIO_FUNC188_IN_INV_SEL_S 6
+/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC188_IN_SEL 0x0000003F
+#define GPIO_FUNC188_IN_SEL_M ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S))
+#define GPIO_FUNC188_IN_SEL_V 0x3F
+#define GPIO_FUNC188_IN_SEL_S 0
+
+#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0424)
+/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG189_IN_SEL (BIT(7))
+#define GPIO_SIG189_IN_SEL_M (BIT(7))
+#define GPIO_SIG189_IN_SEL_V 0x1
+#define GPIO_SIG189_IN_SEL_S 7
+/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC189_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_V 0x1
+#define GPIO_FUNC189_IN_INV_SEL_S 6
+/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC189_IN_SEL 0x0000003F
+#define GPIO_FUNC189_IN_SEL_M ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S))
+#define GPIO_FUNC189_IN_SEL_V 0x3F
+#define GPIO_FUNC189_IN_SEL_S 0
+
+#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0428)
+/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG190_IN_SEL (BIT(7))
+#define GPIO_SIG190_IN_SEL_M (BIT(7))
+#define GPIO_SIG190_IN_SEL_V 0x1
+#define GPIO_SIG190_IN_SEL_S 7
+/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC190_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_V 0x1
+#define GPIO_FUNC190_IN_INV_SEL_S 6
+/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC190_IN_SEL 0x0000003F
+#define GPIO_FUNC190_IN_SEL_M ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S))
+#define GPIO_FUNC190_IN_SEL_V 0x3F
+#define GPIO_FUNC190_IN_SEL_S 0
+
+#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x042c)
+/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG191_IN_SEL (BIT(7))
+#define GPIO_SIG191_IN_SEL_M (BIT(7))
+#define GPIO_SIG191_IN_SEL_V 0x1
+#define GPIO_SIG191_IN_SEL_S 7
+/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC191_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_V 0x1
+#define GPIO_FUNC191_IN_INV_SEL_S 6
+/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC191_IN_SEL 0x0000003F
+#define GPIO_FUNC191_IN_SEL_M ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S))
+#define GPIO_FUNC191_IN_SEL_V 0x3F
+#define GPIO_FUNC191_IN_SEL_S 0
+
+#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0430)
+/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG192_IN_SEL (BIT(7))
+#define GPIO_SIG192_IN_SEL_M (BIT(7))
+#define GPIO_SIG192_IN_SEL_V 0x1
+#define GPIO_SIG192_IN_SEL_S 7
+/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC192_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_V 0x1
+#define GPIO_FUNC192_IN_INV_SEL_S 6
+/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC192_IN_SEL 0x0000003F
+#define GPIO_FUNC192_IN_SEL_M ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S))
+#define GPIO_FUNC192_IN_SEL_V 0x3F
+#define GPIO_FUNC192_IN_SEL_S 0
+
+#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0434)
+/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG193_IN_SEL (BIT(7))
+#define GPIO_SIG193_IN_SEL_M (BIT(7))
+#define GPIO_SIG193_IN_SEL_V 0x1
+#define GPIO_SIG193_IN_SEL_S 7
+/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC193_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_V 0x1
+#define GPIO_FUNC193_IN_INV_SEL_S 6
+/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC193_IN_SEL 0x0000003F
+#define GPIO_FUNC193_IN_SEL_M ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S))
+#define GPIO_FUNC193_IN_SEL_V 0x3F
+#define GPIO_FUNC193_IN_SEL_S 0
+
+#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0438)
+/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG194_IN_SEL (BIT(7))
+#define GPIO_SIG194_IN_SEL_M (BIT(7))
+#define GPIO_SIG194_IN_SEL_V 0x1
+#define GPIO_SIG194_IN_SEL_S 7
+/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC194_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_V 0x1
+#define GPIO_FUNC194_IN_INV_SEL_S 6
+/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC194_IN_SEL 0x0000003F
+#define GPIO_FUNC194_IN_SEL_M ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S))
+#define GPIO_FUNC194_IN_SEL_V 0x3F
+#define GPIO_FUNC194_IN_SEL_S 0
+
+#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x043c)
+/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG195_IN_SEL (BIT(7))
+#define GPIO_SIG195_IN_SEL_M (BIT(7))
+#define GPIO_SIG195_IN_SEL_V 0x1
+#define GPIO_SIG195_IN_SEL_S 7
+/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC195_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_V 0x1
+#define GPIO_FUNC195_IN_INV_SEL_S 6
+/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC195_IN_SEL 0x0000003F
+#define GPIO_FUNC195_IN_SEL_M ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S))
+#define GPIO_FUNC195_IN_SEL_V 0x3F
+#define GPIO_FUNC195_IN_SEL_S 0
+
+#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0440)
+/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG196_IN_SEL (BIT(7))
+#define GPIO_SIG196_IN_SEL_M (BIT(7))
+#define GPIO_SIG196_IN_SEL_V 0x1
+#define GPIO_SIG196_IN_SEL_S 7
+/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC196_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_V 0x1
+#define GPIO_FUNC196_IN_INV_SEL_S 6
+/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC196_IN_SEL 0x0000003F
+#define GPIO_FUNC196_IN_SEL_M ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S))
+#define GPIO_FUNC196_IN_SEL_V 0x3F
+#define GPIO_FUNC196_IN_SEL_S 0
+
+#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0444)
+/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG197_IN_SEL (BIT(7))
+#define GPIO_SIG197_IN_SEL_M (BIT(7))
+#define GPIO_SIG197_IN_SEL_V 0x1
+#define GPIO_SIG197_IN_SEL_S 7
+/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC197_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_V 0x1
+#define GPIO_FUNC197_IN_INV_SEL_S 6
+/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC197_IN_SEL 0x0000003F
+#define GPIO_FUNC197_IN_SEL_M ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S))
+#define GPIO_FUNC197_IN_SEL_V 0x3F
+#define GPIO_FUNC197_IN_SEL_S 0
+
+#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0448)
+/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG198_IN_SEL (BIT(7))
+#define GPIO_SIG198_IN_SEL_M (BIT(7))
+#define GPIO_SIG198_IN_SEL_V 0x1
+#define GPIO_SIG198_IN_SEL_S 7
+/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC198_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_V 0x1
+#define GPIO_FUNC198_IN_INV_SEL_S 6
+/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC198_IN_SEL 0x0000003F
+#define GPIO_FUNC198_IN_SEL_M ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S))
+#define GPIO_FUNC198_IN_SEL_V 0x3F
+#define GPIO_FUNC198_IN_SEL_S 0
+
+#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x044c)
+/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG199_IN_SEL (BIT(7))
+#define GPIO_SIG199_IN_SEL_M (BIT(7))
+#define GPIO_SIG199_IN_SEL_V 0x1
+#define GPIO_SIG199_IN_SEL_S 7
+/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC199_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_V 0x1
+#define GPIO_FUNC199_IN_INV_SEL_S 6
+/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC199_IN_SEL 0x0000003F
+#define GPIO_FUNC199_IN_SEL_M ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S))
+#define GPIO_FUNC199_IN_SEL_V 0x3F
+#define GPIO_FUNC199_IN_SEL_S 0
+
+#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0450)
+/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG200_IN_SEL (BIT(7))
+#define GPIO_SIG200_IN_SEL_M (BIT(7))
+#define GPIO_SIG200_IN_SEL_V 0x1
+#define GPIO_SIG200_IN_SEL_S 7
+/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC200_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_V 0x1
+#define GPIO_FUNC200_IN_INV_SEL_S 6
+/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC200_IN_SEL 0x0000003F
+#define GPIO_FUNC200_IN_SEL_M ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S))
+#define GPIO_FUNC200_IN_SEL_V 0x3F
+#define GPIO_FUNC200_IN_SEL_S 0
+
+#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0454)
+/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG201_IN_SEL (BIT(7))
+#define GPIO_SIG201_IN_SEL_M (BIT(7))
+#define GPIO_SIG201_IN_SEL_V 0x1
+#define GPIO_SIG201_IN_SEL_S 7
+/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC201_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_V 0x1
+#define GPIO_FUNC201_IN_INV_SEL_S 6
+/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC201_IN_SEL 0x0000003F
+#define GPIO_FUNC201_IN_SEL_M ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S))
+#define GPIO_FUNC201_IN_SEL_V 0x3F
+#define GPIO_FUNC201_IN_SEL_S 0
+
+#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0458)
+/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG202_IN_SEL (BIT(7))
+#define GPIO_SIG202_IN_SEL_M (BIT(7))
+#define GPIO_SIG202_IN_SEL_V 0x1
+#define GPIO_SIG202_IN_SEL_S 7
+/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC202_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_V 0x1
+#define GPIO_FUNC202_IN_INV_SEL_S 6
+/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC202_IN_SEL 0x0000003F
+#define GPIO_FUNC202_IN_SEL_M ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S))
+#define GPIO_FUNC202_IN_SEL_V 0x3F
+#define GPIO_FUNC202_IN_SEL_S 0
+
+#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x045c)
+/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG203_IN_SEL (BIT(7))
+#define GPIO_SIG203_IN_SEL_M (BIT(7))
+#define GPIO_SIG203_IN_SEL_V 0x1
+#define GPIO_SIG203_IN_SEL_S 7
+/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC203_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_V 0x1
+#define GPIO_FUNC203_IN_INV_SEL_S 6
+/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC203_IN_SEL 0x0000003F
+#define GPIO_FUNC203_IN_SEL_M ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S))
+#define GPIO_FUNC203_IN_SEL_V 0x3F
+#define GPIO_FUNC203_IN_SEL_S 0
+
+#define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0460)
+/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG204_IN_SEL (BIT(7))
+#define GPIO_SIG204_IN_SEL_M (BIT(7))
+#define GPIO_SIG204_IN_SEL_V 0x1
+#define GPIO_SIG204_IN_SEL_S 7
+/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC204_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC204_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC204_IN_INV_SEL_V 0x1
+#define GPIO_FUNC204_IN_INV_SEL_S 6
+/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC204_IN_SEL 0x0000003F
+#define GPIO_FUNC204_IN_SEL_M ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S))
+#define GPIO_FUNC204_IN_SEL_V 0x3F
+#define GPIO_FUNC204_IN_SEL_S 0
+
+#define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0464)
+/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG205_IN_SEL (BIT(7))
+#define GPIO_SIG205_IN_SEL_M (BIT(7))
+#define GPIO_SIG205_IN_SEL_V 0x1
+#define GPIO_SIG205_IN_SEL_S 7
+/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC205_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC205_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC205_IN_INV_SEL_V 0x1
+#define GPIO_FUNC205_IN_INV_SEL_S 6
+/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC205_IN_SEL 0x0000003F
+#define GPIO_FUNC205_IN_SEL_M ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S))
+#define GPIO_FUNC205_IN_SEL_V 0x3F
+#define GPIO_FUNC205_IN_SEL_S 0
+
+#define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0468)
+/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG206_IN_SEL (BIT(7))
+#define GPIO_SIG206_IN_SEL_M (BIT(7))
+#define GPIO_SIG206_IN_SEL_V 0x1
+#define GPIO_SIG206_IN_SEL_S 7
+/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC206_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC206_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC206_IN_INV_SEL_V 0x1
+#define GPIO_FUNC206_IN_INV_SEL_S 6
+/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC206_IN_SEL 0x0000003F
+#define GPIO_FUNC206_IN_SEL_M ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S))
+#define GPIO_FUNC206_IN_SEL_V 0x3F
+#define GPIO_FUNC206_IN_SEL_S 0
+
+#define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x046c)
+/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG207_IN_SEL (BIT(7))
+#define GPIO_SIG207_IN_SEL_M (BIT(7))
+#define GPIO_SIG207_IN_SEL_V 0x1
+#define GPIO_SIG207_IN_SEL_S 7
+/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC207_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC207_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC207_IN_INV_SEL_V 0x1
+#define GPIO_FUNC207_IN_INV_SEL_S 6
+/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC207_IN_SEL 0x0000003F
+#define GPIO_FUNC207_IN_SEL_M ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S))
+#define GPIO_FUNC207_IN_SEL_V 0x3F
+#define GPIO_FUNC207_IN_SEL_S 0
+
+#define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0470)
+/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG208_IN_SEL (BIT(7))
+#define GPIO_SIG208_IN_SEL_M (BIT(7))
+#define GPIO_SIG208_IN_SEL_V 0x1
+#define GPIO_SIG208_IN_SEL_S 7
+/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC208_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC208_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC208_IN_INV_SEL_V 0x1
+#define GPIO_FUNC208_IN_INV_SEL_S 6
+/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC208_IN_SEL 0x0000003F
+#define GPIO_FUNC208_IN_SEL_M ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S))
+#define GPIO_FUNC208_IN_SEL_V 0x3F
+#define GPIO_FUNC208_IN_SEL_S 0
+
+#define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0474)
+/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG209_IN_SEL (BIT(7))
+#define GPIO_SIG209_IN_SEL_M (BIT(7))
+#define GPIO_SIG209_IN_SEL_V 0x1
+#define GPIO_SIG209_IN_SEL_S 7
+/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC209_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC209_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC209_IN_INV_SEL_V 0x1
+#define GPIO_FUNC209_IN_INV_SEL_S 6
+/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC209_IN_SEL 0x0000003F
+#define GPIO_FUNC209_IN_SEL_M ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S))
+#define GPIO_FUNC209_IN_SEL_V 0x3F
+#define GPIO_FUNC209_IN_SEL_S 0
+
+#define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0478)
+/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG210_IN_SEL (BIT(7))
+#define GPIO_SIG210_IN_SEL_M (BIT(7))
+#define GPIO_SIG210_IN_SEL_V 0x1
+#define GPIO_SIG210_IN_SEL_S 7
+/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC210_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC210_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC210_IN_INV_SEL_V 0x1
+#define GPIO_FUNC210_IN_INV_SEL_S 6
+/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC210_IN_SEL 0x0000003F
+#define GPIO_FUNC210_IN_SEL_M ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S))
+#define GPIO_FUNC210_IN_SEL_V 0x3F
+#define GPIO_FUNC210_IN_SEL_S 0
+
+#define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x047c)
+/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG211_IN_SEL (BIT(7))
+#define GPIO_SIG211_IN_SEL_M (BIT(7))
+#define GPIO_SIG211_IN_SEL_V 0x1
+#define GPIO_SIG211_IN_SEL_S 7
+/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC211_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC211_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC211_IN_INV_SEL_V 0x1
+#define GPIO_FUNC211_IN_INV_SEL_S 6
+/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC211_IN_SEL 0x0000003F
+#define GPIO_FUNC211_IN_SEL_M ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S))
+#define GPIO_FUNC211_IN_SEL_V 0x3F
+#define GPIO_FUNC211_IN_SEL_S 0
+
+#define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0480)
+/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG212_IN_SEL (BIT(7))
+#define GPIO_SIG212_IN_SEL_M (BIT(7))
+#define GPIO_SIG212_IN_SEL_V 0x1
+#define GPIO_SIG212_IN_SEL_S 7
+/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC212_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC212_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC212_IN_INV_SEL_V 0x1
+#define GPIO_FUNC212_IN_INV_SEL_S 6
+/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC212_IN_SEL 0x0000003F
+#define GPIO_FUNC212_IN_SEL_M ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S))
+#define GPIO_FUNC212_IN_SEL_V 0x3F
+#define GPIO_FUNC212_IN_SEL_S 0
+
+#define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0484)
+/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG213_IN_SEL (BIT(7))
+#define GPIO_SIG213_IN_SEL_M (BIT(7))
+#define GPIO_SIG213_IN_SEL_V 0x1
+#define GPIO_SIG213_IN_SEL_S 7
+/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC213_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC213_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC213_IN_INV_SEL_V 0x1
+#define GPIO_FUNC213_IN_INV_SEL_S 6
+/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC213_IN_SEL 0x0000003F
+#define GPIO_FUNC213_IN_SEL_M ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S))
+#define GPIO_FUNC213_IN_SEL_V 0x3F
+#define GPIO_FUNC213_IN_SEL_S 0
+
+#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0488)
+/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG214_IN_SEL (BIT(7))
+#define GPIO_SIG214_IN_SEL_M (BIT(7))
+#define GPIO_SIG214_IN_SEL_V 0x1
+#define GPIO_SIG214_IN_SEL_S 7
+/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC214_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_V 0x1
+#define GPIO_FUNC214_IN_INV_SEL_S 6
+/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC214_IN_SEL 0x0000003F
+#define GPIO_FUNC214_IN_SEL_M ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S))
+#define GPIO_FUNC214_IN_SEL_V 0x3F
+#define GPIO_FUNC214_IN_SEL_S 0
+
+#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x048c)
+/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG215_IN_SEL (BIT(7))
+#define GPIO_SIG215_IN_SEL_M (BIT(7))
+#define GPIO_SIG215_IN_SEL_V 0x1
+#define GPIO_SIG215_IN_SEL_S 7
+/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC215_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_V 0x1
+#define GPIO_FUNC215_IN_INV_SEL_S 6
+/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC215_IN_SEL 0x0000003F
+#define GPIO_FUNC215_IN_SEL_M ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S))
+#define GPIO_FUNC215_IN_SEL_V 0x3F
+#define GPIO_FUNC215_IN_SEL_S 0
+
+#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0490)
+/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG216_IN_SEL (BIT(7))
+#define GPIO_SIG216_IN_SEL_M (BIT(7))
+#define GPIO_SIG216_IN_SEL_V 0x1
+#define GPIO_SIG216_IN_SEL_S 7
+/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC216_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_V 0x1
+#define GPIO_FUNC216_IN_INV_SEL_S 6
+/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC216_IN_SEL 0x0000003F
+#define GPIO_FUNC216_IN_SEL_M ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S))
+#define GPIO_FUNC216_IN_SEL_V 0x3F
+#define GPIO_FUNC216_IN_SEL_S 0
+
+#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0494)
+/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG217_IN_SEL (BIT(7))
+#define GPIO_SIG217_IN_SEL_M (BIT(7))
+#define GPIO_SIG217_IN_SEL_V 0x1
+#define GPIO_SIG217_IN_SEL_S 7
+/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC217_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_V 0x1
+#define GPIO_FUNC217_IN_INV_SEL_S 6
+/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC217_IN_SEL 0x0000003F
+#define GPIO_FUNC217_IN_SEL_M ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S))
+#define GPIO_FUNC217_IN_SEL_V 0x3F
+#define GPIO_FUNC217_IN_SEL_S 0
+
+#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0498)
+/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG218_IN_SEL (BIT(7))
+#define GPIO_SIG218_IN_SEL_M (BIT(7))
+#define GPIO_SIG218_IN_SEL_V 0x1
+#define GPIO_SIG218_IN_SEL_S 7
+/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC218_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_V 0x1
+#define GPIO_FUNC218_IN_INV_SEL_S 6
+/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC218_IN_SEL 0x0000003F
+#define GPIO_FUNC218_IN_SEL_M ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S))
+#define GPIO_FUNC218_IN_SEL_V 0x3F
+#define GPIO_FUNC218_IN_SEL_S 0
+
+#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x049c)
+/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG219_IN_SEL (BIT(7))
+#define GPIO_SIG219_IN_SEL_M (BIT(7))
+#define GPIO_SIG219_IN_SEL_V 0x1
+#define GPIO_SIG219_IN_SEL_S 7
+/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC219_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_V 0x1
+#define GPIO_FUNC219_IN_INV_SEL_S 6
+/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC219_IN_SEL 0x0000003F
+#define GPIO_FUNC219_IN_SEL_M ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S))
+#define GPIO_FUNC219_IN_SEL_V 0x3F
+#define GPIO_FUNC219_IN_SEL_S 0
+
+#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a0)
+/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG220_IN_SEL (BIT(7))
+#define GPIO_SIG220_IN_SEL_M (BIT(7))
+#define GPIO_SIG220_IN_SEL_V 0x1
+#define GPIO_SIG220_IN_SEL_S 7
+/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC220_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_V 0x1
+#define GPIO_FUNC220_IN_INV_SEL_S 6
+/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC220_IN_SEL 0x0000003F
+#define GPIO_FUNC220_IN_SEL_M ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S))
+#define GPIO_FUNC220_IN_SEL_V 0x3F
+#define GPIO_FUNC220_IN_SEL_S 0
+
+#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a4)
+/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG221_IN_SEL (BIT(7))
+#define GPIO_SIG221_IN_SEL_M (BIT(7))
+#define GPIO_SIG221_IN_SEL_V 0x1
+#define GPIO_SIG221_IN_SEL_S 7
+/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC221_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_V 0x1
+#define GPIO_FUNC221_IN_INV_SEL_S 6
+/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC221_IN_SEL 0x0000003F
+#define GPIO_FUNC221_IN_SEL_M ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S))
+#define GPIO_FUNC221_IN_SEL_V 0x3F
+#define GPIO_FUNC221_IN_SEL_S 0
+
+#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a8)
+/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG222_IN_SEL (BIT(7))
+#define GPIO_SIG222_IN_SEL_M (BIT(7))
+#define GPIO_SIG222_IN_SEL_V 0x1
+#define GPIO_SIG222_IN_SEL_S 7
+/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC222_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_V 0x1
+#define GPIO_FUNC222_IN_INV_SEL_S 6
+/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC222_IN_SEL 0x0000003F
+#define GPIO_FUNC222_IN_SEL_M ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S))
+#define GPIO_FUNC222_IN_SEL_V 0x3F
+#define GPIO_FUNC222_IN_SEL_S 0
+
+#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ac)
+/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG223_IN_SEL (BIT(7))
+#define GPIO_SIG223_IN_SEL_M (BIT(7))
+#define GPIO_SIG223_IN_SEL_V 0x1
+#define GPIO_SIG223_IN_SEL_S 7
+/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC223_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_V 0x1
+#define GPIO_FUNC223_IN_INV_SEL_S 6
+/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC223_IN_SEL 0x0000003F
+#define GPIO_FUNC223_IN_SEL_M ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S))
+#define GPIO_FUNC223_IN_SEL_V 0x3F
+#define GPIO_FUNC223_IN_SEL_S 0
+
+#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b0)
+/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG224_IN_SEL (BIT(7))
+#define GPIO_SIG224_IN_SEL_M (BIT(7))
+#define GPIO_SIG224_IN_SEL_V 0x1
+#define GPIO_SIG224_IN_SEL_S 7
+/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC224_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_V 0x1
+#define GPIO_FUNC224_IN_INV_SEL_S 6
+/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC224_IN_SEL 0x0000003F
+#define GPIO_FUNC224_IN_SEL_M ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S))
+#define GPIO_FUNC224_IN_SEL_V 0x3F
+#define GPIO_FUNC224_IN_SEL_S 0
+
+#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b4)
+/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG225_IN_SEL (BIT(7))
+#define GPIO_SIG225_IN_SEL_M (BIT(7))
+#define GPIO_SIG225_IN_SEL_V 0x1
+#define GPIO_SIG225_IN_SEL_S 7
+/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC225_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_V 0x1
+#define GPIO_FUNC225_IN_INV_SEL_S 6
+/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC225_IN_SEL 0x0000003F
+#define GPIO_FUNC225_IN_SEL_M ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S))
+#define GPIO_FUNC225_IN_SEL_V 0x3F
+#define GPIO_FUNC225_IN_SEL_S 0
+
+#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b8)
+/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG226_IN_SEL (BIT(7))
+#define GPIO_SIG226_IN_SEL_M (BIT(7))
+#define GPIO_SIG226_IN_SEL_V 0x1
+#define GPIO_SIG226_IN_SEL_S 7
+/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC226_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_V 0x1
+#define GPIO_FUNC226_IN_INV_SEL_S 6
+/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC226_IN_SEL 0x0000003F
+#define GPIO_FUNC226_IN_SEL_M ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S))
+#define GPIO_FUNC226_IN_SEL_V 0x3F
+#define GPIO_FUNC226_IN_SEL_S 0
+
+#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04bc)
+/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG227_IN_SEL (BIT(7))
+#define GPIO_SIG227_IN_SEL_M (BIT(7))
+#define GPIO_SIG227_IN_SEL_V 0x1
+#define GPIO_SIG227_IN_SEL_S 7
+/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC227_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_V 0x1
+#define GPIO_FUNC227_IN_INV_SEL_S 6
+/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC227_IN_SEL 0x0000003F
+#define GPIO_FUNC227_IN_SEL_M ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S))
+#define GPIO_FUNC227_IN_SEL_V 0x3F
+#define GPIO_FUNC227_IN_SEL_S 0
+
+#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c0)
+/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG228_IN_SEL (BIT(7))
+#define GPIO_SIG228_IN_SEL_M (BIT(7))
+#define GPIO_SIG228_IN_SEL_V 0x1
+#define GPIO_SIG228_IN_SEL_S 7
+/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC228_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_V 0x1
+#define GPIO_FUNC228_IN_INV_SEL_S 6
+/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC228_IN_SEL 0x0000003F
+#define GPIO_FUNC228_IN_SEL_M ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S))
+#define GPIO_FUNC228_IN_SEL_V 0x3F
+#define GPIO_FUNC228_IN_SEL_S 0
+
+#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c4)
+/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG229_IN_SEL (BIT(7))
+#define GPIO_SIG229_IN_SEL_M (BIT(7))
+#define GPIO_SIG229_IN_SEL_V 0x1
+#define GPIO_SIG229_IN_SEL_S 7
+/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC229_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_V 0x1
+#define GPIO_FUNC229_IN_INV_SEL_S 6
+/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC229_IN_SEL 0x0000003F
+#define GPIO_FUNC229_IN_SEL_M ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S))
+#define GPIO_FUNC229_IN_SEL_V 0x3F
+#define GPIO_FUNC229_IN_SEL_S 0
+
+#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c8)
+/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG230_IN_SEL (BIT(7))
+#define GPIO_SIG230_IN_SEL_M (BIT(7))
+#define GPIO_SIG230_IN_SEL_V 0x1
+#define GPIO_SIG230_IN_SEL_S 7
+/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC230_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_V 0x1
+#define GPIO_FUNC230_IN_INV_SEL_S 6
+/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC230_IN_SEL 0x0000003F
+#define GPIO_FUNC230_IN_SEL_M ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S))
+#define GPIO_FUNC230_IN_SEL_V 0x3F
+#define GPIO_FUNC230_IN_SEL_S 0
+
+#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04cc)
+/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG231_IN_SEL (BIT(7))
+#define GPIO_SIG231_IN_SEL_M (BIT(7))
+#define GPIO_SIG231_IN_SEL_V 0x1
+#define GPIO_SIG231_IN_SEL_S 7
+/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC231_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_V 0x1
+#define GPIO_FUNC231_IN_INV_SEL_S 6
+/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC231_IN_SEL 0x0000003F
+#define GPIO_FUNC231_IN_SEL_M ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S))
+#define GPIO_FUNC231_IN_SEL_V 0x3F
+#define GPIO_FUNC231_IN_SEL_S 0
+
+#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d0)
+/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG232_IN_SEL (BIT(7))
+#define GPIO_SIG232_IN_SEL_M (BIT(7))
+#define GPIO_SIG232_IN_SEL_V 0x1
+#define GPIO_SIG232_IN_SEL_S 7
+/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC232_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_V 0x1
+#define GPIO_FUNC232_IN_INV_SEL_S 6
+/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC232_IN_SEL 0x0000003F
+#define GPIO_FUNC232_IN_SEL_M ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S))
+#define GPIO_FUNC232_IN_SEL_V 0x3F
+#define GPIO_FUNC232_IN_SEL_S 0
+
+#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d4)
+/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG233_IN_SEL (BIT(7))
+#define GPIO_SIG233_IN_SEL_M (BIT(7))
+#define GPIO_SIG233_IN_SEL_V 0x1
+#define GPIO_SIG233_IN_SEL_S 7
+/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC233_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_V 0x1
+#define GPIO_FUNC233_IN_INV_SEL_S 6
+/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC233_IN_SEL 0x0000003F
+#define GPIO_FUNC233_IN_SEL_M ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S))
+#define GPIO_FUNC233_IN_SEL_V 0x3F
+#define GPIO_FUNC233_IN_SEL_S 0
+
+#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d8)
+/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG234_IN_SEL (BIT(7))
+#define GPIO_SIG234_IN_SEL_M (BIT(7))
+#define GPIO_SIG234_IN_SEL_V 0x1
+#define GPIO_SIG234_IN_SEL_S 7
+/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC234_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_V 0x1
+#define GPIO_FUNC234_IN_INV_SEL_S 6
+/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC234_IN_SEL 0x0000003F
+#define GPIO_FUNC234_IN_SEL_M ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S))
+#define GPIO_FUNC234_IN_SEL_V 0x3F
+#define GPIO_FUNC234_IN_SEL_S 0
+
+#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04dc)
+/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG235_IN_SEL (BIT(7))
+#define GPIO_SIG235_IN_SEL_M (BIT(7))
+#define GPIO_SIG235_IN_SEL_V 0x1
+#define GPIO_SIG235_IN_SEL_S 7
+/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC235_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_V 0x1
+#define GPIO_FUNC235_IN_INV_SEL_S 6
+/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC235_IN_SEL 0x0000003F
+#define GPIO_FUNC235_IN_SEL_M ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S))
+#define GPIO_FUNC235_IN_SEL_V 0x3F
+#define GPIO_FUNC235_IN_SEL_S 0
+
+#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e0)
+/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG236_IN_SEL (BIT(7))
+#define GPIO_SIG236_IN_SEL_M (BIT(7))
+#define GPIO_SIG236_IN_SEL_V 0x1
+#define GPIO_SIG236_IN_SEL_S 7
+/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC236_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_V 0x1
+#define GPIO_FUNC236_IN_INV_SEL_S 6
+/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC236_IN_SEL 0x0000003F
+#define GPIO_FUNC236_IN_SEL_M ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S))
+#define GPIO_FUNC236_IN_SEL_V 0x3F
+#define GPIO_FUNC236_IN_SEL_S 0
+
+#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e4)
+/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG237_IN_SEL (BIT(7))
+#define GPIO_SIG237_IN_SEL_M (BIT(7))
+#define GPIO_SIG237_IN_SEL_V 0x1
+#define GPIO_SIG237_IN_SEL_S 7
+/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC237_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_V 0x1
+#define GPIO_FUNC237_IN_INV_SEL_S 6
+/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC237_IN_SEL 0x0000003F
+#define GPIO_FUNC237_IN_SEL_M ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S))
+#define GPIO_FUNC237_IN_SEL_V 0x3F
+#define GPIO_FUNC237_IN_SEL_S 0
+
+#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e8)
+/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG238_IN_SEL (BIT(7))
+#define GPIO_SIG238_IN_SEL_M (BIT(7))
+#define GPIO_SIG238_IN_SEL_V 0x1
+#define GPIO_SIG238_IN_SEL_S 7
+/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC238_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_V 0x1
+#define GPIO_FUNC238_IN_INV_SEL_S 6
+/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC238_IN_SEL 0x0000003F
+#define GPIO_FUNC238_IN_SEL_M ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S))
+#define GPIO_FUNC238_IN_SEL_V 0x3F
+#define GPIO_FUNC238_IN_SEL_S 0
+
+#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ec)
+/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG239_IN_SEL (BIT(7))
+#define GPIO_SIG239_IN_SEL_M (BIT(7))
+#define GPIO_SIG239_IN_SEL_V 0x1
+#define GPIO_SIG239_IN_SEL_S 7
+/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC239_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_V 0x1
+#define GPIO_FUNC239_IN_INV_SEL_S 6
+/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC239_IN_SEL 0x0000003F
+#define GPIO_FUNC239_IN_SEL_M ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S))
+#define GPIO_FUNC239_IN_SEL_V 0x3F
+#define GPIO_FUNC239_IN_SEL_S 0
+
+#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f0)
+/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG240_IN_SEL (BIT(7))
+#define GPIO_SIG240_IN_SEL_M (BIT(7))
+#define GPIO_SIG240_IN_SEL_V 0x1
+#define GPIO_SIG240_IN_SEL_S 7
+/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC240_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_V 0x1
+#define GPIO_FUNC240_IN_INV_SEL_S 6
+/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC240_IN_SEL 0x0000003F
+#define GPIO_FUNC240_IN_SEL_M ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S))
+#define GPIO_FUNC240_IN_SEL_V 0x3F
+#define GPIO_FUNC240_IN_SEL_S 0
+
+#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f4)
+/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG241_IN_SEL (BIT(7))
+#define GPIO_SIG241_IN_SEL_M (BIT(7))
+#define GPIO_SIG241_IN_SEL_V 0x1
+#define GPIO_SIG241_IN_SEL_S 7
+/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC241_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_V 0x1
+#define GPIO_FUNC241_IN_INV_SEL_S 6
+/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC241_IN_SEL 0x0000003F
+#define GPIO_FUNC241_IN_SEL_M ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S))
+#define GPIO_FUNC241_IN_SEL_V 0x3F
+#define GPIO_FUNC241_IN_SEL_S 0
+
+#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f8)
+/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG242_IN_SEL (BIT(7))
+#define GPIO_SIG242_IN_SEL_M (BIT(7))
+#define GPIO_SIG242_IN_SEL_V 0x1
+#define GPIO_SIG242_IN_SEL_S 7
+/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC242_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_V 0x1
+#define GPIO_FUNC242_IN_INV_SEL_S 6
+/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC242_IN_SEL 0x0000003F
+#define GPIO_FUNC242_IN_SEL_M ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S))
+#define GPIO_FUNC242_IN_SEL_V 0x3F
+#define GPIO_FUNC242_IN_SEL_S 0
+
+#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04fc)
+/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG243_IN_SEL (BIT(7))
+#define GPIO_SIG243_IN_SEL_M (BIT(7))
+#define GPIO_SIG243_IN_SEL_V 0x1
+#define GPIO_SIG243_IN_SEL_S 7
+/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC243_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_V 0x1
+#define GPIO_FUNC243_IN_INV_SEL_S 6
+/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC243_IN_SEL 0x0000003F
+#define GPIO_FUNC243_IN_SEL_M ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S))
+#define GPIO_FUNC243_IN_SEL_V 0x3F
+#define GPIO_FUNC243_IN_SEL_S 0
+
+#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0500)
+/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG244_IN_SEL (BIT(7))
+#define GPIO_SIG244_IN_SEL_M (BIT(7))
+#define GPIO_SIG244_IN_SEL_V 0x1
+#define GPIO_SIG244_IN_SEL_S 7
+/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC244_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_V 0x1
+#define GPIO_FUNC244_IN_INV_SEL_S 6
+/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC244_IN_SEL 0x0000003F
+#define GPIO_FUNC244_IN_SEL_M ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S))
+#define GPIO_FUNC244_IN_SEL_V 0x3F
+#define GPIO_FUNC244_IN_SEL_S 0
+
+#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0504)
+/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG245_IN_SEL (BIT(7))
+#define GPIO_SIG245_IN_SEL_M (BIT(7))
+#define GPIO_SIG245_IN_SEL_V 0x1
+#define GPIO_SIG245_IN_SEL_S 7
+/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC245_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_V 0x1
+#define GPIO_FUNC245_IN_INV_SEL_S 6
+/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC245_IN_SEL 0x0000003F
+#define GPIO_FUNC245_IN_SEL_M ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S))
+#define GPIO_FUNC245_IN_SEL_V 0x3F
+#define GPIO_FUNC245_IN_SEL_S 0
+
+#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0508)
+/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG246_IN_SEL (BIT(7))
+#define GPIO_SIG246_IN_SEL_M (BIT(7))
+#define GPIO_SIG246_IN_SEL_V 0x1
+#define GPIO_SIG246_IN_SEL_S 7
+/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC246_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_V 0x1
+#define GPIO_FUNC246_IN_INV_SEL_S 6
+/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC246_IN_SEL 0x0000003F
+#define GPIO_FUNC246_IN_SEL_M ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S))
+#define GPIO_FUNC246_IN_SEL_V 0x3F
+#define GPIO_FUNC246_IN_SEL_S 0
+
+#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x050c)
+/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG247_IN_SEL (BIT(7))
+#define GPIO_SIG247_IN_SEL_M (BIT(7))
+#define GPIO_SIG247_IN_SEL_V 0x1
+#define GPIO_SIG247_IN_SEL_S 7
+/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC247_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_V 0x1
+#define GPIO_FUNC247_IN_INV_SEL_S 6
+/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC247_IN_SEL 0x0000003F
+#define GPIO_FUNC247_IN_SEL_M ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S))
+#define GPIO_FUNC247_IN_SEL_V 0x3F
+#define GPIO_FUNC247_IN_SEL_S 0
+
+#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0510)
+/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG248_IN_SEL (BIT(7))
+#define GPIO_SIG248_IN_SEL_M (BIT(7))
+#define GPIO_SIG248_IN_SEL_V 0x1
+#define GPIO_SIG248_IN_SEL_S 7
+/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC248_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_V 0x1
+#define GPIO_FUNC248_IN_INV_SEL_S 6
+/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC248_IN_SEL 0x0000003F
+#define GPIO_FUNC248_IN_SEL_M ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S))
+#define GPIO_FUNC248_IN_SEL_V 0x3F
+#define GPIO_FUNC248_IN_SEL_S 0
+
+#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0514)
+/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG249_IN_SEL (BIT(7))
+#define GPIO_SIG249_IN_SEL_M (BIT(7))
+#define GPIO_SIG249_IN_SEL_V 0x1
+#define GPIO_SIG249_IN_SEL_S 7
+/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC249_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_V 0x1
+#define GPIO_FUNC249_IN_INV_SEL_S 6
+/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC249_IN_SEL 0x0000003F
+#define GPIO_FUNC249_IN_SEL_M ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S))
+#define GPIO_FUNC249_IN_SEL_V 0x3F
+#define GPIO_FUNC249_IN_SEL_S 0
+
+#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0518)
+/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG250_IN_SEL (BIT(7))
+#define GPIO_SIG250_IN_SEL_M (BIT(7))
+#define GPIO_SIG250_IN_SEL_V 0x1
+#define GPIO_SIG250_IN_SEL_S 7
+/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC250_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_V 0x1
+#define GPIO_FUNC250_IN_INV_SEL_S 6
+/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC250_IN_SEL 0x0000003F
+#define GPIO_FUNC250_IN_SEL_M ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S))
+#define GPIO_FUNC250_IN_SEL_V 0x3F
+#define GPIO_FUNC250_IN_SEL_S 0
+
+#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x051c)
+/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG251_IN_SEL (BIT(7))
+#define GPIO_SIG251_IN_SEL_M (BIT(7))
+#define GPIO_SIG251_IN_SEL_V 0x1
+#define GPIO_SIG251_IN_SEL_S 7
+/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC251_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_V 0x1
+#define GPIO_FUNC251_IN_INV_SEL_S 6
+/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC251_IN_SEL 0x0000003F
+#define GPIO_FUNC251_IN_SEL_M ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S))
+#define GPIO_FUNC251_IN_SEL_V 0x3F
+#define GPIO_FUNC251_IN_SEL_S 0
+
+#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0520)
+/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG252_IN_SEL (BIT(7))
+#define GPIO_SIG252_IN_SEL_M (BIT(7))
+#define GPIO_SIG252_IN_SEL_V 0x1
+#define GPIO_SIG252_IN_SEL_S 7
+/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC252_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_V 0x1
+#define GPIO_FUNC252_IN_INV_SEL_S 6
+/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC252_IN_SEL 0x0000003F
+#define GPIO_FUNC252_IN_SEL_M ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S))
+#define GPIO_FUNC252_IN_SEL_V 0x3F
+#define GPIO_FUNC252_IN_SEL_S 0
+
+#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0524)
+/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG253_IN_SEL (BIT(7))
+#define GPIO_SIG253_IN_SEL_M (BIT(7))
+#define GPIO_SIG253_IN_SEL_V 0x1
+#define GPIO_SIG253_IN_SEL_S 7
+/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC253_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_V 0x1
+#define GPIO_FUNC253_IN_INV_SEL_S 6
+/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC253_IN_SEL 0x0000003F
+#define GPIO_FUNC253_IN_SEL_M ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S))
+#define GPIO_FUNC253_IN_SEL_V 0x3F
+#define GPIO_FUNC253_IN_SEL_S 0
+
+#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0528)
+/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG254_IN_SEL (BIT(7))
+#define GPIO_SIG254_IN_SEL_M (BIT(7))
+#define GPIO_SIG254_IN_SEL_V 0x1
+#define GPIO_SIG254_IN_SEL_S 7
+/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC254_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_V 0x1
+#define GPIO_FUNC254_IN_INV_SEL_S 6
+/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC254_IN_SEL 0x0000003F
+#define GPIO_FUNC254_IN_SEL_M ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S))
+#define GPIO_FUNC254_IN_SEL_V 0x3F
+#define GPIO_FUNC254_IN_SEL_S 0
+
+#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x052c)
+/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
+/*description: if the slow signal bypass the io matrix or not if you want setting
+ the value to 1*/
+#define GPIO_SIG255_IN_SEL (BIT(7))
+#define GPIO_SIG255_IN_SEL_M (BIT(7))
+#define GPIO_SIG255_IN_SEL_V 0x1
+#define GPIO_SIG255_IN_SEL_S 7
+/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
+/*description: revert the value of the input if you want to revert please set the value to 1*/
+#define GPIO_FUNC255_IN_INV_SEL (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_M (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_V 0x1
+#define GPIO_FUNC255_IN_INV_SEL_S 6
+/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
+/*description: select one of the 256 inputs*/
+#define GPIO_FUNC255_IN_SEL 0x0000003F
+#define GPIO_FUNC255_IN_SEL_M ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S))
+#define GPIO_FUNC255_IN_SEL_V 0x3F
+#define GPIO_FUNC255_IN_SEL_S 0
+
+#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0530)
+/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC0_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC0_OEN_INV_SEL_S 11
+/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC0_OEN_SEL (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_V 0x1
+#define GPIO_FUNC0_OEN_SEL_S 10
+/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC0_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC0_OUT_INV_SEL_S 9
+/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC0_OUT_SEL 0x000001FF
+#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
+#define GPIO_FUNC0_OUT_SEL_V 0x1FF
+#define GPIO_FUNC0_OUT_SEL_S 0
+
+#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0534)
+/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC1_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC1_OEN_INV_SEL_S 11
+/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC1_OEN_SEL (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_V 0x1
+#define GPIO_FUNC1_OEN_SEL_S 10
+/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC1_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC1_OUT_INV_SEL_S 9
+/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC1_OUT_SEL 0x000001FF
+#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
+#define GPIO_FUNC1_OUT_SEL_V 0x1FF
+#define GPIO_FUNC1_OUT_SEL_S 0
+
+#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0538)
+/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC2_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC2_OEN_INV_SEL_S 11
+/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC2_OEN_SEL (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_V 0x1
+#define GPIO_FUNC2_OEN_SEL_S 10
+/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC2_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC2_OUT_INV_SEL_S 9
+/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC2_OUT_SEL 0x000001FF
+#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
+#define GPIO_FUNC2_OUT_SEL_V 0x1FF
+#define GPIO_FUNC2_OUT_SEL_S 0
+
+#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x053c)
+/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC3_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC3_OEN_INV_SEL_S 11
+/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC3_OEN_SEL (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_V 0x1
+#define GPIO_FUNC3_OEN_SEL_S 10
+/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC3_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC3_OUT_INV_SEL_S 9
+/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC3_OUT_SEL 0x000001FF
+#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
+#define GPIO_FUNC3_OUT_SEL_V 0x1FF
+#define GPIO_FUNC3_OUT_SEL_S 0
+
+#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0540)
+/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC4_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC4_OEN_INV_SEL_S 11
+/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC4_OEN_SEL (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_V 0x1
+#define GPIO_FUNC4_OEN_SEL_S 10
+/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC4_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC4_OUT_INV_SEL_S 9
+/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC4_OUT_SEL 0x000001FF
+#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
+#define GPIO_FUNC4_OUT_SEL_V 0x1FF
+#define GPIO_FUNC4_OUT_SEL_S 0
+
+#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0544)
+/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC5_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC5_OEN_INV_SEL_S 11
+/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC5_OEN_SEL (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_V 0x1
+#define GPIO_FUNC5_OEN_SEL_S 10
+/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC5_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC5_OUT_INV_SEL_S 9
+/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC5_OUT_SEL 0x000001FF
+#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
+#define GPIO_FUNC5_OUT_SEL_V 0x1FF
+#define GPIO_FUNC5_OUT_SEL_S 0
+
+#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0548)
+/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC6_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC6_OEN_INV_SEL_S 11
+/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC6_OEN_SEL (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_V 0x1
+#define GPIO_FUNC6_OEN_SEL_S 10
+/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC6_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC6_OUT_INV_SEL_S 9
+/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC6_OUT_SEL 0x000001FF
+#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
+#define GPIO_FUNC6_OUT_SEL_V 0x1FF
+#define GPIO_FUNC6_OUT_SEL_S 0
+
+#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x054c)
+/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC7_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC7_OEN_INV_SEL_S 11
+/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC7_OEN_SEL (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_V 0x1
+#define GPIO_FUNC7_OEN_SEL_S 10
+/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC7_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC7_OUT_INV_SEL_S 9
+/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC7_OUT_SEL 0x000001FF
+#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
+#define GPIO_FUNC7_OUT_SEL_V 0x1FF
+#define GPIO_FUNC7_OUT_SEL_S 0
+
+#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0550)
+/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC8_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC8_OEN_INV_SEL_S 11
+/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC8_OEN_SEL (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_V 0x1
+#define GPIO_FUNC8_OEN_SEL_S 10
+/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC8_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC8_OUT_INV_SEL_S 9
+/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC8_OUT_SEL 0x000001FF
+#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
+#define GPIO_FUNC8_OUT_SEL_V 0x1FF
+#define GPIO_FUNC8_OUT_SEL_S 0
+
+#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0554)
+/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC9_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC9_OEN_INV_SEL_S 11
+/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC9_OEN_SEL (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_V 0x1
+#define GPIO_FUNC9_OEN_SEL_S 10
+/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC9_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC9_OUT_INV_SEL_S 9
+/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC9_OUT_SEL 0x000001FF
+#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
+#define GPIO_FUNC9_OUT_SEL_V 0x1FF
+#define GPIO_FUNC9_OUT_SEL_S 0
+
+#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0558)
+/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC10_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC10_OEN_INV_SEL_S 11
+/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC10_OEN_SEL (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_V 0x1
+#define GPIO_FUNC10_OEN_SEL_S 10
+/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC10_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC10_OUT_INV_SEL_S 9
+/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC10_OUT_SEL 0x000001FF
+#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
+#define GPIO_FUNC10_OUT_SEL_V 0x1FF
+#define GPIO_FUNC10_OUT_SEL_S 0
+
+#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x055c)
+/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC11_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC11_OEN_INV_SEL_S 11
+/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC11_OEN_SEL (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_V 0x1
+#define GPIO_FUNC11_OEN_SEL_S 10
+/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC11_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC11_OUT_INV_SEL_S 9
+/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC11_OUT_SEL 0x000001FF
+#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
+#define GPIO_FUNC11_OUT_SEL_V 0x1FF
+#define GPIO_FUNC11_OUT_SEL_S 0
+
+#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0560)
+/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC12_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC12_OEN_INV_SEL_S 11
+/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC12_OEN_SEL (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_V 0x1
+#define GPIO_FUNC12_OEN_SEL_S 10
+/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC12_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC12_OUT_INV_SEL_S 9
+/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC12_OUT_SEL 0x000001FF
+#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
+#define GPIO_FUNC12_OUT_SEL_V 0x1FF
+#define GPIO_FUNC12_OUT_SEL_S 0
+
+#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0564)
+/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC13_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC13_OEN_INV_SEL_S 11
+/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC13_OEN_SEL (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_V 0x1
+#define GPIO_FUNC13_OEN_SEL_S 10
+/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC13_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC13_OUT_INV_SEL_S 9
+/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC13_OUT_SEL 0x000001FF
+#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
+#define GPIO_FUNC13_OUT_SEL_V 0x1FF
+#define GPIO_FUNC13_OUT_SEL_S 0
+
+#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0568)
+/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC14_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC14_OEN_INV_SEL_S 11
+/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC14_OEN_SEL (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_V 0x1
+#define GPIO_FUNC14_OEN_SEL_S 10
+/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC14_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC14_OUT_INV_SEL_S 9
+/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC14_OUT_SEL 0x000001FF
+#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
+#define GPIO_FUNC14_OUT_SEL_V 0x1FF
+#define GPIO_FUNC14_OUT_SEL_S 0
+
+#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x056c)
+/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC15_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC15_OEN_INV_SEL_S 11
+/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC15_OEN_SEL (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_V 0x1
+#define GPIO_FUNC15_OEN_SEL_S 10
+/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC15_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC15_OUT_INV_SEL_S 9
+/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC15_OUT_SEL 0x000001FF
+#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
+#define GPIO_FUNC15_OUT_SEL_V 0x1FF
+#define GPIO_FUNC15_OUT_SEL_S 0
+
+#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0570)
+/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC16_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC16_OEN_INV_SEL_S 11
+/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC16_OEN_SEL (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_V 0x1
+#define GPIO_FUNC16_OEN_SEL_S 10
+/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC16_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC16_OUT_INV_SEL_S 9
+/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC16_OUT_SEL 0x000001FF
+#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
+#define GPIO_FUNC16_OUT_SEL_V 0x1FF
+#define GPIO_FUNC16_OUT_SEL_S 0
+
+#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0574)
+/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC17_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC17_OEN_INV_SEL_S 11
+/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC17_OEN_SEL (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_V 0x1
+#define GPIO_FUNC17_OEN_SEL_S 10
+/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC17_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC17_OUT_INV_SEL_S 9
+/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC17_OUT_SEL 0x000001FF
+#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
+#define GPIO_FUNC17_OUT_SEL_V 0x1FF
+#define GPIO_FUNC17_OUT_SEL_S 0
+
+#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0578)
+/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC18_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC18_OEN_INV_SEL_S 11
+/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC18_OEN_SEL (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_V 0x1
+#define GPIO_FUNC18_OEN_SEL_S 10
+/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC18_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC18_OUT_INV_SEL_S 9
+/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC18_OUT_SEL 0x000001FF
+#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
+#define GPIO_FUNC18_OUT_SEL_V 0x1FF
+#define GPIO_FUNC18_OUT_SEL_S 0
+
+#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x057c)
+/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC19_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC19_OEN_INV_SEL_S 11
+/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC19_OEN_SEL (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_V 0x1
+#define GPIO_FUNC19_OEN_SEL_S 10
+/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC19_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC19_OUT_INV_SEL_S 9
+/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC19_OUT_SEL 0x000001FF
+#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
+#define GPIO_FUNC19_OUT_SEL_V 0x1FF
+#define GPIO_FUNC19_OUT_SEL_S 0
+
+#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0580)
+/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC20_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC20_OEN_INV_SEL_S 11
+/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC20_OEN_SEL (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_V 0x1
+#define GPIO_FUNC20_OEN_SEL_S 10
+/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC20_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC20_OUT_INV_SEL_S 9
+/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC20_OUT_SEL 0x000001FF
+#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
+#define GPIO_FUNC20_OUT_SEL_V 0x1FF
+#define GPIO_FUNC20_OUT_SEL_S 0
+
+#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0584)
+/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC21_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC21_OEN_INV_SEL_S 11
+/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC21_OEN_SEL (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_V 0x1
+#define GPIO_FUNC21_OEN_SEL_S 10
+/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC21_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC21_OUT_INV_SEL_S 9
+/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC21_OUT_SEL 0x000001FF
+#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
+#define GPIO_FUNC21_OUT_SEL_V 0x1FF
+#define GPIO_FUNC21_OUT_SEL_S 0
+
+#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0588)
+/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC22_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC22_OEN_INV_SEL_S 11
+/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC22_OEN_SEL (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_V 0x1
+#define GPIO_FUNC22_OEN_SEL_S 10
+/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC22_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC22_OUT_INV_SEL_S 9
+/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC22_OUT_SEL 0x000001FF
+#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
+#define GPIO_FUNC22_OUT_SEL_V 0x1FF
+#define GPIO_FUNC22_OUT_SEL_S 0
+
+#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x058c)
+/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC23_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC23_OEN_INV_SEL_S 11
+/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC23_OEN_SEL (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_V 0x1
+#define GPIO_FUNC23_OEN_SEL_S 10
+/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC23_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC23_OUT_INV_SEL_S 9
+/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC23_OUT_SEL 0x000001FF
+#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
+#define GPIO_FUNC23_OUT_SEL_V 0x1FF
+#define GPIO_FUNC23_OUT_SEL_S 0
+
+#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0590)
+/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC24_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC24_OEN_INV_SEL_S 11
+/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC24_OEN_SEL (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_V 0x1
+#define GPIO_FUNC24_OEN_SEL_S 10
+/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC24_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC24_OUT_INV_SEL_S 9
+/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC24_OUT_SEL 0x000001FF
+#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
+#define GPIO_FUNC24_OUT_SEL_V 0x1FF
+#define GPIO_FUNC24_OUT_SEL_S 0
+
+#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0594)
+/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC25_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC25_OEN_INV_SEL_S 11
+/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC25_OEN_SEL (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_V 0x1
+#define GPIO_FUNC25_OEN_SEL_S 10
+/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC25_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC25_OUT_INV_SEL_S 9
+/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC25_OUT_SEL 0x000001FF
+#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
+#define GPIO_FUNC25_OUT_SEL_V 0x1FF
+#define GPIO_FUNC25_OUT_SEL_S 0
+
+#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0598)
+/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC26_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC26_OEN_INV_SEL_S 11
+/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC26_OEN_SEL (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_V 0x1
+#define GPIO_FUNC26_OEN_SEL_S 10
+/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC26_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC26_OUT_INV_SEL_S 9
+/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC26_OUT_SEL 0x000001FF
+#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S))
+#define GPIO_FUNC26_OUT_SEL_V 0x1FF
+#define GPIO_FUNC26_OUT_SEL_S 0
+
+#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x059c)
+/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC27_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC27_OEN_INV_SEL_S 11
+/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC27_OEN_SEL (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_V 0x1
+#define GPIO_FUNC27_OEN_SEL_S 10
+/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC27_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC27_OUT_INV_SEL_S 9
+/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC27_OUT_SEL 0x000001FF
+#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S))
+#define GPIO_FUNC27_OUT_SEL_V 0x1FF
+#define GPIO_FUNC27_OUT_SEL_S 0
+
+#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a0)
+/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC28_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC28_OEN_INV_SEL_S 11
+/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC28_OEN_SEL (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_V 0x1
+#define GPIO_FUNC28_OEN_SEL_S 10
+/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC28_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC28_OUT_INV_SEL_S 9
+/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC28_OUT_SEL 0x000001FF
+#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S))
+#define GPIO_FUNC28_OUT_SEL_V 0x1FF
+#define GPIO_FUNC28_OUT_SEL_S 0
+
+#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a4)
+/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC29_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC29_OEN_INV_SEL_S 11
+/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC29_OEN_SEL (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_V 0x1
+#define GPIO_FUNC29_OEN_SEL_S 10
+/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC29_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC29_OUT_INV_SEL_S 9
+/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC29_OUT_SEL 0x000001FF
+#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S))
+#define GPIO_FUNC29_OUT_SEL_V 0x1FF
+#define GPIO_FUNC29_OUT_SEL_S 0
+
+#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a8)
+/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC30_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC30_OEN_INV_SEL_S 11
+/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC30_OEN_SEL (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_V 0x1
+#define GPIO_FUNC30_OEN_SEL_S 10
+/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC30_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC30_OUT_INV_SEL_S 9
+/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC30_OUT_SEL 0x000001FF
+#define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S))
+#define GPIO_FUNC30_OUT_SEL_V 0x1FF
+#define GPIO_FUNC30_OUT_SEL_S 0
+
+#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05ac)
+/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC31_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC31_OEN_INV_SEL_S 11
+/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC31_OEN_SEL (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_V 0x1
+#define GPIO_FUNC31_OEN_SEL_S 10
+/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC31_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC31_OUT_INV_SEL_S 9
+/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC31_OUT_SEL 0x000001FF
+#define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S))
+#define GPIO_FUNC31_OUT_SEL_V 0x1FF
+#define GPIO_FUNC31_OUT_SEL_S 0
+
+#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b0)
+/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC32_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC32_OEN_INV_SEL_S 11
+/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC32_OEN_SEL (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_V 0x1
+#define GPIO_FUNC32_OEN_SEL_S 10
+/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC32_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC32_OUT_INV_SEL_S 9
+/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC32_OUT_SEL 0x000001FF
+#define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S))
+#define GPIO_FUNC32_OUT_SEL_V 0x1FF
+#define GPIO_FUNC32_OUT_SEL_S 0
+
+#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b4)
+/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC33_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC33_OEN_INV_SEL_S 11
+/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC33_OEN_SEL (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_V 0x1
+#define GPIO_FUNC33_OEN_SEL_S 10
+/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC33_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC33_OUT_INV_SEL_S 9
+/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC33_OUT_SEL 0x000001FF
+#define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S))
+#define GPIO_FUNC33_OUT_SEL_V 0x1FF
+#define GPIO_FUNC33_OUT_SEL_S 0
+
+#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b8)
+/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC34_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC34_OEN_INV_SEL_S 11
+/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC34_OEN_SEL (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_V 0x1
+#define GPIO_FUNC34_OEN_SEL_S 10
+/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC34_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC34_OUT_INV_SEL_S 9
+/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC34_OUT_SEL 0x000001FF
+#define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S))
+#define GPIO_FUNC34_OUT_SEL_V 0x1FF
+#define GPIO_FUNC34_OUT_SEL_S 0
+
+#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05bc)
+/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC35_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC35_OEN_INV_SEL_S 11
+/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC35_OEN_SEL (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_V 0x1
+#define GPIO_FUNC35_OEN_SEL_S 10
+/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC35_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC35_OUT_INV_SEL_S 9
+/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC35_OUT_SEL 0x000001FF
+#define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S))
+#define GPIO_FUNC35_OUT_SEL_V 0x1FF
+#define GPIO_FUNC35_OUT_SEL_S 0
+
+#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c0)
+/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC36_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC36_OEN_INV_SEL_S 11
+/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC36_OEN_SEL (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_V 0x1
+#define GPIO_FUNC36_OEN_SEL_S 10
+/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC36_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC36_OUT_INV_SEL_S 9
+/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC36_OUT_SEL 0x000001FF
+#define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S))
+#define GPIO_FUNC36_OUT_SEL_V 0x1FF
+#define GPIO_FUNC36_OUT_SEL_S 0
+
+#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c4)
+/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC37_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC37_OEN_INV_SEL_S 11
+/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC37_OEN_SEL (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_V 0x1
+#define GPIO_FUNC37_OEN_SEL_S 10
+/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC37_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC37_OUT_INV_SEL_S 9
+/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC37_OUT_SEL 0x000001FF
+#define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S))
+#define GPIO_FUNC37_OUT_SEL_V 0x1FF
+#define GPIO_FUNC37_OUT_SEL_S 0
+
+#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c8)
+/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC38_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC38_OEN_INV_SEL_S 11
+/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC38_OEN_SEL (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_V 0x1
+#define GPIO_FUNC38_OEN_SEL_S 10
+/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC38_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC38_OUT_INV_SEL_S 9
+/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC38_OUT_SEL 0x000001FF
+#define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S))
+#define GPIO_FUNC38_OUT_SEL_V 0x1FF
+#define GPIO_FUNC38_OUT_SEL_S 0
+
+#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05cc)
+/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
+/*description: invert the output enable value if you want to revert the output
+ enable value setting the value to 1*/
+#define GPIO_FUNC39_OEN_INV_SEL (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_M (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC39_OEN_INV_SEL_S 11
+/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
+/*description: weather using the logical oen signal or not using the value setting
+ by the register*/
+#define GPIO_FUNC39_OEN_SEL (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_M (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_V 0x1
+#define GPIO_FUNC39_OEN_SEL_S 10
+/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
+/*description: invert the output value if you want to revert the output value
+ setting the value to 1*/
+#define GPIO_FUNC39_OUT_INV_SEL (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_M (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC39_OUT_INV_SEL_S 9
+/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
+/*description: select one of the 256 output to 40 GPIO*/
+#define GPIO_FUNC39_OUT_SEL 0x000001FF
+#define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S))
+#define GPIO_FUNC39_OUT_SEL_V 0x1FF
+#define GPIO_FUNC39_OUT_SEL_S 0
+
+
+
+
+#endif /*_SOC_GPIO_REG_H_ */
+
-//for GPIO_PIN group
-#define GPIO_PIN_CONFIG_MSB 12
-#define GPIO_PIN_CONFIG_LSB 11
-#define GPIO_PIN_CONFIG_MASK 0x00001800
-#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
-#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
-
-#define GPIO_WAKEUP_ENABLE 1
-#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE)
-#define GPIO_PIN_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
-
-#define GPIO_PIN_INT_TYPE_MASK 0x380
-#define GPIO_PIN_INT_TYPE_MSB 9
-#define GPIO_PIN_INT_TYPE_LSB 7
-#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
-#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
-
-#define GPIO_PAD_DRIVER_ENABLE 1
-#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE)
-#define GPIO_PIN_PAD_DRIVER_MSB 2
-#define GPIO_PIN_PAD_DRIVER_LSB 2
-#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
-#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
-
-//end GPIO_PIN group
-
-#define GPIO_BT_SELECT (DR_REG_GPIO_BASE + 0x0000)
-#define GPIO_GPIO_BT_SEL 0xFFFFFFFF
-#define GPIO_GPIO_BT_SEL_S 0
-
-#define GPIO_OUT (DR_REG_GPIO_BASE + 0x0004)
-#define GPIO_GPIO_OUT_DATA 0xFFFFFFFF
-#define GPIO_GPIO_OUT_DATA_S 0
-
-#define GPIO_OUT_W1TS (DR_REG_GPIO_BASE + 0x0008)
-#define GPIO_GPIO_OUT_DATA 0xFFFFFFFF
-#define GPIO_GPIO_OUT_DATA_S 0
-
-#define GPIO_OUT_W1TC (DR_REG_GPIO_BASE + 0x000c)
-#define GPIO_GPIO_OUT_DATA 0xFFFFFFFF
-#define GPIO_GPIO_OUT_DATA_S 0
-
-#define GPIO_OUT1 (DR_REG_GPIO_BASE + 0x0010)
-#define GPIO_GPIO_OUT_DATA_H 0x000000FF
-#define GPIO_GPIO_OUT_DATA_H_S 0
-
-#define GPIO_OUT1_W1TS (DR_REG_GPIO_BASE + 0x0014)
-#define GPIO_GPIO_OUT_DATA_H 0x000000FF
-#define GPIO_GPIO_OUT_DATA_H_S 0
-
-#define GPIO_OUT1_W1TC (DR_REG_GPIO_BASE + 0x0018)
-#define GPIO_GPIO_OUT_DATA_H 0x000000FF
-#define GPIO_GPIO_OUT_DATA_H_S 0
-
-#define GPIO_SDIO_SELECT (DR_REG_GPIO_BASE + 0x001c)
-#define GPIO_GPIO_SDIO_SEL 0x000000FF
-#define GPIO_GPIO_SDIO_SEL_S 0
-
-#define GPIO_ENABLE (DR_REG_GPIO_BASE + 0x0020)
-#define GPIO_GPIO_ENABLE_DATA 0xFFFFFFFF
-#define GPIO_GPIO_ENABLE_DATA_S 0
-
-#define GPIO_ENABLE_W1TS (DR_REG_GPIO_BASE + 0x0024)
-#define GPIO_GPIO_ENABLE_DATA 0xFFFFFFFF
-#define GPIO_GPIO_ENABLE_DATA_S 0
-
-#define GPIO_ENABLE_W1TC (DR_REG_GPIO_BASE + 0x0028)
-#define GPIO_GPIO_ENABLE_DATA 0xFFFFFFFF
-#define GPIO_GPIO_ENABLE_DATA_S 0
-
-#define GPIO_ENABLE1 (DR_REG_GPIO_BASE + 0x002c)
-#define GPIO_GPIO_ENABLE_DATA_H 0x000000FF
-#define GPIO_GPIO_ENABLE_DATA_H_S 0
-
-#define GPIO_ENABLE1_W1TS (DR_REG_GPIO_BASE + 0x0030)
-#define GPIO_GPIO_ENABLE_DATA_H 0x000000FF
-#define GPIO_GPIO_ENABLE_DATA_H_S 0
-
-#define GPIO_ENABLE1_W1TC (DR_REG_GPIO_BASE + 0x0034)
-#define GPIO_GPIO_ENABLE_DATA_H 0x000000FF
-#define GPIO_GPIO_ENABLE_DATA_H_S 0
-
-#define GPIO_STRAP (DR_REG_GPIO_BASE + 0x0038)
-#define GPIO_GPIO_STRAPPING 0x0000FFFF
-#define GPIO_GPIO_STRAPPING_S 0
-
-#define GPIO_IN (DR_REG_GPIO_BASE + 0x003c)
-#define GPIO_GPIO_IN_DATA_NEXT 0xFFFFFFFF
-#define GPIO_GPIO_IN_DATA_NEXT_S 0
-
-#define GPIO_IN1 (DR_REG_GPIO_BASE + 0x0040)
-#define GPIO_GPIO_IN_DATA_NEXT_H 0x000000FF
-#define GPIO_GPIO_IN_DATA_NEXT_H_S 0
-
-#define GPIO_STATUS (DR_REG_GPIO_BASE + 0x0044)
-#define GPIO_GPIO_STATUS_INTERRUPT 0xFFFFFFFF
-#define GPIO_GPIO_STATUS_INTERRUPT_S 0
-
-#define GPIO_STATUS_W1TS (DR_REG_GPIO_BASE + 0x0048)
-#define GPIO_GPIO_STATUS_INTERRUPT 0xFFFFFFFF
-#define GPIO_GPIO_STATUS_INTERRUPT_S 0
-
-#define GPIO_STATUS_W1TC (DR_REG_GPIO_BASE + 0x004c)
-#define GPIO_GPIO_STATUS_INTERRUPT 0xFFFFFFFF
-#define GPIO_GPIO_STATUS_INTERRUPT_S 0
-
-#define GPIO_STATUS1 (DR_REG_GPIO_BASE + 0x0050)
-#define GPIO_GPIO_STATUS_INTERRUPT_H 0x000000FF
-#define GPIO_GPIO_STATUS_INTERRUPT_H_S 0
-
-#define GPIO_STATUS1_W1TS (DR_REG_GPIO_BASE + 0x0054)
-#define GPIO_GPIO_STATUS_INTERRUPT_H 0x000000FF
-#define GPIO_GPIO_STATUS_INTERRUPT_H_S 0
-
-#define GPIO_STATUS1_W1TC (DR_REG_GPIO_BASE + 0x0058)
-#define GPIO_GPIO_STATUS_INTERRUPT_H 0x000000FF
-#define GPIO_GPIO_STATUS_INTERRUPT_H_S 0
-
-#define GPIO_ACPU_INT (DR_REG_GPIO_BASE + 0x0060)
-#define GPIO_GPIO_APPCPU_INT 0xFFFFFFFF
-#define GPIO_GPIO_APPCPU_INT_S 0
-
-#define GPIO_ACPU_NMI_INT (DR_REG_GPIO_BASE + 0x0064)
-#define GPIO_GPIO_APPCPU_NMI_INT 0xFFFFFFFF
-#define GPIO_GPIO_APPCPU_NMI_INT_S 0
-
-#define GPIO_PCPU_INT (DR_REG_GPIO_BASE + 0x0068)
-#define GPIO_GPIO_PROCPU_INT 0xFFFFFFFF
-#define GPIO_GPIO_PROCPU_INT_S 0
-
-#define GPIO_PCPU_NMI_INT (DR_REG_GPIO_BASE + 0x006c)
-#define GPIO_GPIO_PROCPU_NMI_INT 0xFFFFFFFF
-#define GPIO_GPIO_PROCPU_NMI_INT_S 0
-
-#define GPIO_CPUSDIO_INT (DR_REG_GPIO_BASE + 0x0070)
-#define GPIO_GPIO_SDIO_INT 0xFFFFFFFF
-#define GPIO_GPIO_SDIO_INT_S 0
-
-#define GPIO_ACPU_INT1 (DR_REG_GPIO_BASE + 0x0074)
-#define GPIO_GPIO_APPCPU_INT_H 0x000000FF
-#define GPIO_GPIO_APPCPU_INT_H_S 0
-
-#define GPIO_ACPU_NMI_INT1 (DR_REG_GPIO_BASE + 0x0078)
-#define GPIO_GPIO_APPCPU_NMI_INT_H 0x000000FF
-#define GPIO_GPIO_APPCPU_NMI_INT_H_S 0
-
-#define GPIO_PCPU_INT1 (DR_REG_GPIO_BASE + 0x007c)
-#define GPIO_GPIO_PROCPU_INT_H 0x000000FF
-#define GPIO_GPIO_PROCPU_INT_H_S 0
-
-#define GPIO_PCPU_NMI_INT1 (DR_REG_GPIO_BASE + 0x0080)
-#define GPIO_GPIO_PROCPU_NMI_INT_H 0x000000FF
-#define GPIO_GPIO_PROCPU_NMI_INT_H_S 0
-
-#define GPIO_CPUSDIO_INT1 (DR_REG_GPIO_BASE + 0x0084)
-#define GPIO_GPIO_SDIO_INT_H 0x000000FF
-#define GPIO_GPIO_SDIO_INT_H_S 0
-
-#define GPIO_PIN0 (DR_REG_GPIO_BASE + 0x0088)
-#define GPIO_GPIO_PIN0_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN0_INT_ENA_S 13
-#define GPIO_GPIO_PIN0_CONFIG 0x00000003
-#define GPIO_GPIO_PIN0_CONFIG_S 11
-#define GPIO_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN0_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN0_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN0_INT_TYPE_S 7
-#define GPIO_GPIO_PIN0_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN0_PAD_DRIVER_S 2
-
-#define GPIO_PIN1 (DR_REG_GPIO_BASE + 0x008c)
-#define GPIO_GPIO_PIN1_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN1_INT_ENA_S 13
-#define GPIO_GPIO_PIN1_CONFIG 0x00000003
-#define GPIO_GPIO_PIN1_CONFIG_S 11
-#define GPIO_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN1_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN1_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN1_INT_TYPE_S 7
-#define GPIO_GPIO_PIN1_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN1_PAD_DRIVER_S 2
-
-#define GPIO_PIN2 (DR_REG_GPIO_BASE + 0x0090)
-#define GPIO_GPIO_PIN2_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN2_INT_ENA_S 13
-#define GPIO_GPIO_PIN2_CONFIG 0x00000003
-#define GPIO_GPIO_PIN2_CONFIG_S 11
-#define GPIO_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN2_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN2_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN2_INT_TYPE_S 7
-#define GPIO_GPIO_PIN2_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN2_PAD_DRIVER_S 2
-
-#define GPIO_PIN3 (DR_REG_GPIO_BASE + 0x0094)
-#define GPIO_GPIO_PIN3_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN3_INT_ENA_S 13
-#define GPIO_GPIO_PIN3_CONFIG 0x00000003
-#define GPIO_GPIO_PIN3_CONFIG_S 11
-#define GPIO_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN3_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN3_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN3_INT_TYPE_S 7
-#define GPIO_GPIO_PIN3_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN3_PAD_DRIVER_S 2
-
-#define GPIO_PIN4 (DR_REG_GPIO_BASE + 0x0098)
-#define GPIO_GPIO_PIN4_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN4_INT_ENA_S 13
-#define GPIO_GPIO_PIN4_CONFIG 0x00000003
-#define GPIO_GPIO_PIN4_CONFIG_S 11
-#define GPIO_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN4_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN4_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN4_INT_TYPE_S 7
-#define GPIO_GPIO_PIN4_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN4_PAD_DRIVER_S 2
-
-#define GPIO_PIN5 (DR_REG_GPIO_BASE + 0x009c)
-#define GPIO_GPIO_PIN5_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN5_INT_ENA_S 13
-#define GPIO_GPIO_PIN5_CONFIG 0x00000003
-#define GPIO_GPIO_PIN5_CONFIG_S 11
-#define GPIO_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN5_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN5_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN5_INT_TYPE_S 7
-#define GPIO_GPIO_PIN5_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN5_PAD_DRIVER_S 2
-
-#define GPIO_PIN6 (DR_REG_GPIO_BASE + 0x00a0)
-#define GPIO_GPIO_PIN6_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN6_INT_ENA_S 13
-#define GPIO_GPIO_PIN6_CONFIG 0x00000003
-#define GPIO_GPIO_PIN6_CONFIG_S 11
-#define GPIO_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN6_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN6_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN6_INT_TYPE_S 7
-#define GPIO_GPIO_PIN6_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN6_PAD_DRIVER_S 2
-
-#define GPIO_PIN7 (DR_REG_GPIO_BASE + 0x00a4)
-#define GPIO_GPIO_PIN7_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN7_INT_ENA_S 13
-#define GPIO_GPIO_PIN7_CONFIG 0x00000003
-#define GPIO_GPIO_PIN7_CONFIG_S 11
-#define GPIO_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN7_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN7_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN7_INT_TYPE_S 7
-#define GPIO_GPIO_PIN7_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN7_PAD_DRIVER_S 2
-
-#define GPIO_PIN8 (DR_REG_GPIO_BASE + 0x00a8)
-#define GPIO_GPIO_PIN8_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN8_INT_ENA_S 13
-#define GPIO_GPIO_PIN8_CONFIG 0x00000003
-#define GPIO_GPIO_PIN8_CONFIG_S 11
-#define GPIO_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN8_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN8_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN8_INT_TYPE_S 7
-#define GPIO_GPIO_PIN8_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN8_PAD_DRIVER_S 2
-
-#define GPIO_PIN9 (DR_REG_GPIO_BASE + 0x00ac)
-#define GPIO_GPIO_PIN9_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN9_INT_ENA_S 13
-#define GPIO_GPIO_PIN9_CONFIG 0x00000003
-#define GPIO_GPIO_PIN9_CONFIG_S 11
-#define GPIO_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN9_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN9_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN9_INT_TYPE_S 7
-#define GPIO_GPIO_PIN9_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN9_PAD_DRIVER_S 2
-
-#define GPIO_PIN10 (DR_REG_GPIO_BASE + 0x00b0)
-#define GPIO_GPIO_PIN10_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN10_INT_ENA_S 13
-#define GPIO_GPIO_PIN10_CONFIG 0x00000003
-#define GPIO_GPIO_PIN10_CONFIG_S 11
-#define GPIO_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN10_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN10_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN10_INT_TYPE_S 7
-#define GPIO_GPIO_PIN10_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN10_PAD_DRIVER_S 2
-
-#define GPIO_PIN11 (DR_REG_GPIO_BASE + 0x00b4)
-#define GPIO_GPIO_PIN11_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN11_INT_ENA_S 13
-#define GPIO_GPIO_PIN11_CONFIG 0x00000003
-#define GPIO_GPIO_PIN11_CONFIG_S 11
-#define GPIO_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN11_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN11_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN11_INT_TYPE_S 7
-#define GPIO_GPIO_PIN11_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN11_PAD_DRIVER_S 2
-
-#define GPIO_PIN12 (DR_REG_GPIO_BASE + 0x00b8)
-#define GPIO_GPIO_PIN12_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN12_INT_ENA_S 13
-#define GPIO_GPIO_PIN12_CONFIG 0x00000003
-#define GPIO_GPIO_PIN12_CONFIG_S 11
-#define GPIO_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN12_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN12_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN12_INT_TYPE_S 7
-#define GPIO_GPIO_PIN12_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN12_PAD_DRIVER_S 2
-
-#define GPIO_PIN13 (DR_REG_GPIO_BASE + 0x00bc)
-#define GPIO_GPIO_PIN13_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN13_INT_ENA_S 13
-#define GPIO_GPIO_PIN13_CONFIG 0x00000003
-#define GPIO_GPIO_PIN13_CONFIG_S 11
-#define GPIO_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN13_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN13_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN13_INT_TYPE_S 7
-#define GPIO_GPIO_PIN13_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN13_PAD_DRIVER_S 2
-
-#define GPIO_PIN14 (DR_REG_GPIO_BASE + 0x00c0)
-#define GPIO_GPIO_PIN14_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN14_INT_ENA_S 13
-#define GPIO_GPIO_PIN14_CONFIG 0x00000003
-#define GPIO_GPIO_PIN14_CONFIG_S 11
-#define GPIO_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN14_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN14_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN14_INT_TYPE_S 7
-#define GPIO_GPIO_PIN14_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN14_PAD_DRIVER_S 2
-
-#define GPIO_PIN15 (DR_REG_GPIO_BASE + 0x00c4)
-#define GPIO_GPIO_PIN15_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN15_INT_ENA_S 13
-#define GPIO_GPIO_PIN15_CONFIG 0x00000003
-#define GPIO_GPIO_PIN15_CONFIG_S 11
-#define GPIO_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN15_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN15_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN15_INT_TYPE_S 7
-#define GPIO_GPIO_PIN15_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN15_PAD_DRIVER_S 2
-
-#define GPIO_PIN16 (DR_REG_GPIO_BASE + 0x00c8)
-#define GPIO_GPIO_PIN16_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN16_INT_ENA_S 13
-#define GPIO_GPIO_PIN16_CONFIG 0x00000003
-#define GPIO_GPIO_PIN16_CONFIG_S 11
-#define GPIO_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN16_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN16_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN16_INT_TYPE_S 7
-#define GPIO_GPIO_PIN16_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN16_PAD_DRIVER_S 2
-
-#define GPIO_PIN17 (DR_REG_GPIO_BASE + 0x00cc)
-#define GPIO_GPIO_PIN17_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN17_INT_ENA_S 13
-#define GPIO_GPIO_PIN17_CONFIG 0x00000003
-#define GPIO_GPIO_PIN17_CONFIG_S 11
-#define GPIO_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN17_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN17_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN17_INT_TYPE_S 7
-#define GPIO_GPIO_PIN17_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN17_PAD_DRIVER_S 2
-
-#define GPIO_PIN18 (DR_REG_GPIO_BASE + 0x00d0)
-#define GPIO_GPIO_PIN18_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN18_INT_ENA_S 13
-#define GPIO_GPIO_PIN18_CONFIG 0x00000003
-#define GPIO_GPIO_PIN18_CONFIG_S 11
-#define GPIO_GPIO_PIN18_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN18_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN18_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN18_INT_TYPE_S 7
-#define GPIO_GPIO_PIN18_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN18_PAD_DRIVER_S 2
-
-#define GPIO_PIN19 (DR_REG_GPIO_BASE + 0x00d4)
-#define GPIO_GPIO_PIN19_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN19_INT_ENA_S 13
-#define GPIO_GPIO_PIN19_CONFIG 0x00000003
-#define GPIO_GPIO_PIN19_CONFIG_S 11
-#define GPIO_GPIO_PIN19_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN19_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN19_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN19_INT_TYPE_S 7
-#define GPIO_GPIO_PIN19_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN19_PAD_DRIVER_S 2
-
-#define GPIO_PIN20 (DR_REG_GPIO_BASE + 0x00d8)
-#define GPIO_GPIO_PIN20_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN20_INT_ENA_S 13
-#define GPIO_GPIO_PIN20_CONFIG 0x00000003
-#define GPIO_GPIO_PIN20_CONFIG_S 11
-#define GPIO_GPIO_PIN20_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN20_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN20_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN20_INT_TYPE_S 7
-#define GPIO_GPIO_PIN20_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN20_PAD_DRIVER_S 2
-
-#define GPIO_PIN21 (DR_REG_GPIO_BASE + 0x00dc)
-#define GPIO_GPIO_PIN21_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN21_INT_ENA_S 13
-#define GPIO_GPIO_PIN21_CONFIG 0x00000003
-#define GPIO_GPIO_PIN21_CONFIG_S 11
-#define GPIO_GPIO_PIN21_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN21_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN21_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN21_INT_TYPE_S 7
-#define GPIO_GPIO_PIN21_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN21_PAD_DRIVER_S 2
-
-#define GPIO_PIN22 (DR_REG_GPIO_BASE + 0x00e0)
-#define GPIO_GPIO_PIN22_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN22_INT_ENA_S 13
-#define GPIO_GPIO_PIN22_CONFIG 0x00000003
-#define GPIO_GPIO_PIN22_CONFIG_S 11
-#define GPIO_GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN22_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN22_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN22_INT_TYPE_S 7
-#define GPIO_GPIO_PIN22_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN22_PAD_DRIVER_S 2
-
-#define GPIO_PIN23 (DR_REG_GPIO_BASE + 0x00e4)
-#define GPIO_GPIO_PIN23_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN23_INT_ENA_S 13
-#define GPIO_GPIO_PIN23_CONFIG 0x00000003
-#define GPIO_GPIO_PIN23_CONFIG_S 11
-#define GPIO_GPIO_PIN23_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN23_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN23_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN23_INT_TYPE_S 7
-#define GPIO_GPIO_PIN23_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN23_PAD_DRIVER_S 2
-
-#define GPIO_PIN24 (DR_REG_GPIO_BASE + 0x00e8)
-#define GPIO_GPIO_PIN24_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN24_INT_ENA_S 13
-#define GPIO_GPIO_PIN24_CONFIG 0x00000003
-#define GPIO_GPIO_PIN24_CONFIG_S 11
-#define GPIO_GPIO_PIN24_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN24_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN24_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN24_INT_TYPE_S 7
-#define GPIO_GPIO_PIN24_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN24_PAD_DRIVER_S 2
-
-#define GPIO_PIN25 (DR_REG_GPIO_BASE + 0x00ec)
-#define GPIO_GPIO_PIN25_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN25_INT_ENA_S 13
-#define GPIO_GPIO_PIN25_CONFIG 0x00000003
-#define GPIO_GPIO_PIN25_CONFIG_S 11
-#define GPIO_GPIO_PIN25_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN25_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN25_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN25_INT_TYPE_S 7
-#define GPIO_GPIO_PIN25_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN25_PAD_DRIVER_S 2
-
-#define GPIO_PIN26 (DR_REG_GPIO_BASE + 0x00f0)
-#define GPIO_GPIO_PIN26_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN26_INT_ENA_S 13
-#define GPIO_GPIO_PIN26_CONFIG 0x00000003
-#define GPIO_GPIO_PIN26_CONFIG_S 11
-#define GPIO_GPIO_PIN26_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN26_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN26_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN26_INT_TYPE_S 7
-#define GPIO_GPIO_PIN26_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN26_PAD_DRIVER_S 2
-
-#define GPIO_PIN27 (DR_REG_GPIO_BASE + 0x00f4)
-#define GPIO_GPIO_PIN27_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN27_INT_ENA_S 13
-#define GPIO_GPIO_PIN27_CONFIG 0x00000003
-#define GPIO_GPIO_PIN27_CONFIG_S 11
-#define GPIO_GPIO_PIN27_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN27_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN27_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN27_INT_TYPE_S 7
-#define GPIO_GPIO_PIN27_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN27_PAD_DRIVER_S 2
-
-#define GPIO_PIN28 (DR_REG_GPIO_BASE + 0x00f8)
-#define GPIO_GPIO_PIN28_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN28_INT_ENA_S 13
-#define GPIO_GPIO_PIN28_CONFIG 0x00000003
-#define GPIO_GPIO_PIN28_CONFIG_S 11
-#define GPIO_GPIO_PIN28_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN28_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN28_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN28_INT_TYPE_S 7
-#define GPIO_GPIO_PIN28_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN28_PAD_DRIVER_S 2
-
-#define GPIO_PIN29 (DR_REG_GPIO_BASE + 0x00fc)
-#define GPIO_GPIO_PIN29_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN29_INT_ENA_S 13
-#define GPIO_GPIO_PIN29_CONFIG 0x00000003
-#define GPIO_GPIO_PIN29_CONFIG_S 11
-#define GPIO_GPIO_PIN29_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN29_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN29_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN29_INT_TYPE_S 7
-#define GPIO_GPIO_PIN29_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN29_PAD_DRIVER_S 2
-
-#define GPIO_PIN30 (DR_REG_GPIO_BASE + 0x0100)
-#define GPIO_GPIO_PIN30_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN30_INT_ENA_S 13
-#define GPIO_GPIO_PIN30_CONFIG 0x00000003
-#define GPIO_GPIO_PIN30_CONFIG_S 11
-#define GPIO_GPIO_PIN30_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN30_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN30_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN30_INT_TYPE_S 7
-#define GPIO_GPIO_PIN30_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN30_PAD_DRIVER_S 2
-
-#define GPIO_PIN31 (DR_REG_GPIO_BASE + 0x0104)
-#define GPIO_GPIO_PIN31_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN31_INT_ENA_S 13
-#define GPIO_GPIO_PIN31_CONFIG 0x00000003
-#define GPIO_GPIO_PIN31_CONFIG_S 11
-#define GPIO_GPIO_PIN31_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN31_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN31_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN31_INT_TYPE_S 7
-#define GPIO_GPIO_PIN31_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN31_PAD_DRIVER_S 2
-
-#define GPIO_PIN32 (DR_REG_GPIO_BASE + 0x0108)
-#define GPIO_GPIO_PIN32_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN32_INT_ENA_S 13
-#define GPIO_GPIO_PIN32_CONFIG 0x00000003
-#define GPIO_GPIO_PIN32_CONFIG_S 11
-#define GPIO_GPIO_PIN32_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN32_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN32_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN32_INT_TYPE_S 7
-#define GPIO_GPIO_PIN32_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN32_PAD_DRIVER_S 2
-
-#define GPIO_PIN33 (DR_REG_GPIO_BASE + 0x010c)
-#define GPIO_GPIO_PIN33_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN33_INT_ENA_S 13
-#define GPIO_GPIO_PIN33_CONFIG 0x00000003
-#define GPIO_GPIO_PIN33_CONFIG_S 11
-#define GPIO_GPIO_PIN33_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN33_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN33_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN33_INT_TYPE_S 7
-#define GPIO_GPIO_PIN33_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN33_PAD_DRIVER_S 2
-
-#define GPIO_PIN34 (DR_REG_GPIO_BASE + 0x0110)
-#define GPIO_GPIO_PIN34_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN34_INT_ENA_S 13
-#define GPIO_GPIO_PIN34_CONFIG 0x00000003
-#define GPIO_GPIO_PIN34_CONFIG_S 11
-#define GPIO_GPIO_PIN34_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN34_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN34_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN34_INT_TYPE_S 7
-#define GPIO_GPIO_PIN34_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN34_PAD_DRIVER_S 2
-
-#define GPIO_PIN35 (DR_REG_GPIO_BASE + 0x0114)
-#define GPIO_GPIO_PIN35_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN35_INT_ENA_S 13
-#define GPIO_GPIO_PIN35_CONFIG 0x00000003
-#define GPIO_GPIO_PIN35_CONFIG_S 11
-#define GPIO_GPIO_PIN35_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN35_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN35_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN35_INT_TYPE_S 7
-#define GPIO_GPIO_PIN35_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN35_PAD_DRIVER_S 2
-
-#define GPIO_PIN36 (DR_REG_GPIO_BASE + 0x0118)
-#define GPIO_GPIO_PIN36_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN36_INT_ENA_S 13
-#define GPIO_GPIO_PIN36_CONFIG 0x00000003
-#define GPIO_GPIO_PIN36_CONFIG_S 11
-#define GPIO_GPIO_PIN36_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN36_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN36_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN36_INT_TYPE_S 7
-#define GPIO_GPIO_PIN36_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN36_PAD_DRIVER_S 2
-
-#define GPIO_PIN37 (DR_REG_GPIO_BASE + 0x011c)
-#define GPIO_GPIO_PIN37_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN37_INT_ENA_S 13
-#define GPIO_GPIO_PIN37_CONFIG 0x00000003
-#define GPIO_GPIO_PIN37_CONFIG_S 11
-#define GPIO_GPIO_PIN37_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN37_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN37_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN37_INT_TYPE_S 7
-#define GPIO_GPIO_PIN37_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN37_PAD_DRIVER_S 2
-
-#define GPIO_PIN38 (DR_REG_GPIO_BASE + 0x0120)
-#define GPIO_GPIO_PIN38_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN38_INT_ENA_S 13
-#define GPIO_GPIO_PIN38_CONFIG 0x00000003
-#define GPIO_GPIO_PIN38_CONFIG_S 11
-#define GPIO_GPIO_PIN38_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN38_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN38_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN38_INT_TYPE_S 7
-#define GPIO_GPIO_PIN38_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN38_PAD_DRIVER_S 2
-
-#define GPIO_PIN39 (DR_REG_GPIO_BASE + 0x0124)
-#define GPIO_GPIO_PIN39_INT_ENA 0x0000001F
-#define GPIO_GPIO_PIN39_INT_ENA_S 13
-#define GPIO_GPIO_PIN39_CONFIG 0x00000003
-#define GPIO_GPIO_PIN39_CONFIG_S 11
-#define GPIO_GPIO_PIN39_WAKEUP_ENABLE (BIT(10))
-#define GPIO_GPIO_PIN39_WAKEUP_ENABLE_S 10
-#define GPIO_GPIO_PIN39_INT_TYPE 0x00000007
-#define GPIO_GPIO_PIN39_INT_TYPE_S 7
-#define GPIO_GPIO_PIN39_PAD_DRIVER (BIT(2))
-#define GPIO_GPIO_PIN39_PAD_DRIVER_S 2
-
-#define CALI_CONF (DR_REG_GPIO_BASE + 0x0128)
-#define GPIO_CALI_START (BIT(31))
-#define GPIO_CALI_START_S 31
-#define GPIO_CALI_RTC_MAX 0x000003FF
-#define GPIO_CALI_RTC_MAX_S 0
-
-#define CALI_DATA (DR_REG_GPIO_BASE + 0x012c)
-#define GPIO_CALI_RDY_SYNC2 (BIT(31))
-#define GPIO_CALI_RDY_SYNC2_S 31
-#define GPIO_CALI_RDY_REAL (BIT(30))
-#define GPIO_CALI_RDY_REAL_S 30
-#define GPIO_CALI_VALUE_SYNC2 0x000FFFFF
-#define GPIO_CALI_VALUE_SYNC2_S 0
-
-#define GPIO_FUNC0_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0130)
-#define GPIO_GPIO_SIG0_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG0_IN_SEL_S 7
-#define GPIO_GPIO_FUNC0_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC0_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC0_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC0_IN_SEL_S 0
-
-#define GPIO_FUNC1_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0134)
-#define GPIO_GPIO_SIG1_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG1_IN_SEL_S 7
-#define GPIO_GPIO_FUNC1_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC1_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC1_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC1_IN_SEL_S 0
-
-#define GPIO_FUNC2_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0138)
-#define GPIO_GPIO_SIG2_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG2_IN_SEL_S 7
-#define GPIO_GPIO_FUNC2_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC2_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC2_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC2_IN_SEL_S 0
-
-#define GPIO_FUNC3_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x013c)
-#define GPIO_GPIO_SIG3_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG3_IN_SEL_S 7
-#define GPIO_GPIO_FUNC3_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC3_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC3_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC3_IN_SEL_S 0
-
-#define GPIO_FUNC4_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0140)
-#define GPIO_GPIO_SIG4_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG4_IN_SEL_S 7
-#define GPIO_GPIO_FUNC4_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC4_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC4_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC4_IN_SEL_S 0
-
-#define GPIO_FUNC5_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0144)
-#define GPIO_GPIO_SIG5_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG5_IN_SEL_S 7
-#define GPIO_GPIO_FUNC5_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC5_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC5_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC5_IN_SEL_S 0
-
-#define GPIO_FUNC6_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0148)
-#define GPIO_GPIO_SIG6_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG6_IN_SEL_S 7
-#define GPIO_GPIO_FUNC6_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC6_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC6_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC6_IN_SEL_S 0
-
-#define GPIO_FUNC7_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x014c)
-#define GPIO_GPIO_SIG7_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG7_IN_SEL_S 7
-#define GPIO_GPIO_FUNC7_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC7_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC7_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC7_IN_SEL_S 0
-
-#define GPIO_FUNC8_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0150)
-#define GPIO_GPIO_SIG8_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG8_IN_SEL_S 7
-#define GPIO_GPIO_FUNC8_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC8_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC8_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC8_IN_SEL_S 0
-
-#define GPIO_FUNC9_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0154)
-#define GPIO_GPIO_SIG9_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG9_IN_SEL_S 7
-#define GPIO_GPIO_FUNC9_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC9_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC9_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC9_IN_SEL_S 0
-
-#define GPIO_FUNC10_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0158)
-#define GPIO_GPIO_SIG10_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG10_IN_SEL_S 7
-#define GPIO_GPIO_FUNC10_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC10_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC10_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC10_IN_SEL_S 0
-
-#define GPIO_FUNC11_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x015c)
-#define GPIO_GPIO_SIG11_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG11_IN_SEL_S 7
-#define GPIO_GPIO_FUNC11_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC11_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC11_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC11_IN_SEL_S 0
-
-#define GPIO_FUNC12_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0160)
-#define GPIO_GPIO_SIG12_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG12_IN_SEL_S 7
-#define GPIO_GPIO_FUNC12_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC12_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC12_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC12_IN_SEL_S 0
-
-#define GPIO_FUNC13_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0164)
-#define GPIO_GPIO_SIG13_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG13_IN_SEL_S 7
-#define GPIO_GPIO_FUNC13_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC13_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC13_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC13_IN_SEL_S 0
-
-#define GPIO_FUNC14_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0168)
-#define GPIO_GPIO_SIG14_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG14_IN_SEL_S 7
-#define GPIO_GPIO_FUNC14_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC14_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC14_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC14_IN_SEL_S 0
-
-#define GPIO_FUNC15_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x016c)
-#define GPIO_GPIO_SIG15_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG15_IN_SEL_S 7
-#define GPIO_GPIO_FUNC15_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC15_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC15_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC15_IN_SEL_S 0
-
-#define GPIO_FUNC16_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0170)
-#define GPIO_GPIO_SIG16_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG16_IN_SEL_S 7
-#define GPIO_GPIO_FUNC16_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC16_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC16_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC16_IN_SEL_S 0
-
-#define GPIO_FUNC17_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0174)
-#define GPIO_GPIO_SIG17_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG17_IN_SEL_S 7
-#define GPIO_GPIO_FUNC17_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC17_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC17_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC17_IN_SEL_S 0
-
-#define GPIO_FUNC18_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0178)
-#define GPIO_GPIO_SIG18_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG18_IN_SEL_S 7
-#define GPIO_GPIO_FUNC18_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC18_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC18_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC18_IN_SEL_S 0
-
-#define GPIO_FUNC19_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x017c)
-#define GPIO_GPIO_SIG19_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG19_IN_SEL_S 7
-#define GPIO_GPIO_FUNC19_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC19_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC19_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC19_IN_SEL_S 0
-
-#define GPIO_FUNC20_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0180)
-#define GPIO_GPIO_SIG20_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG20_IN_SEL_S 7
-#define GPIO_GPIO_FUNC20_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC20_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC20_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC20_IN_SEL_S 0
-
-#define GPIO_FUNC21_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0184)
-#define GPIO_GPIO_SIG21_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG21_IN_SEL_S 7
-#define GPIO_GPIO_FUNC21_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC21_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC21_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC21_IN_SEL_S 0
-
-#define GPIO_FUNC22_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0188)
-#define GPIO_GPIO_SIG22_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG22_IN_SEL_S 7
-#define GPIO_GPIO_FUNC22_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC22_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC22_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC22_IN_SEL_S 0
-
-#define GPIO_FUNC23_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x018c)
-#define GPIO_GPIO_SIG23_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG23_IN_SEL_S 7
-#define GPIO_GPIO_FUNC23_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC23_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC23_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC23_IN_SEL_S 0
-
-#define GPIO_FUNC24_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0190)
-#define GPIO_GPIO_SIG24_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG24_IN_SEL_S 7
-#define GPIO_GPIO_FUNC24_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC24_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC24_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC24_IN_SEL_S 0
-
-#define GPIO_FUNC25_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0194)
-#define GPIO_GPIO_SIG25_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG25_IN_SEL_S 7
-#define GPIO_GPIO_FUNC25_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC25_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC25_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC25_IN_SEL_S 0
-
-#define GPIO_FUNC26_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0198)
-#define GPIO_GPIO_SIG26_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG26_IN_SEL_S 7
-#define GPIO_GPIO_FUNC26_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC26_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC26_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC26_IN_SEL_S 0
-
-#define GPIO_FUNC27_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x019c)
-#define GPIO_GPIO_SIG27_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG27_IN_SEL_S 7
-#define GPIO_GPIO_FUNC27_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC27_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC27_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC27_IN_SEL_S 0
-
-#define GPIO_FUNC28_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01a0)
-#define GPIO_GPIO_SIG28_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG28_IN_SEL_S 7
-#define GPIO_GPIO_FUNC28_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC28_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC28_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC28_IN_SEL_S 0
-
-#define GPIO_FUNC29_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01a4)
-#define GPIO_GPIO_SIG29_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG29_IN_SEL_S 7
-#define GPIO_GPIO_FUNC29_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC29_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC29_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC29_IN_SEL_S 0
-
-#define GPIO_FUNC30_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01a8)
-#define GPIO_GPIO_SIG30_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG30_IN_SEL_S 7
-#define GPIO_GPIO_FUNC30_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC30_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC30_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC30_IN_SEL_S 0
-
-#define GPIO_FUNC31_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01ac)
-#define GPIO_GPIO_SIG31_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG31_IN_SEL_S 7
-#define GPIO_GPIO_FUNC31_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC31_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC31_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC31_IN_SEL_S 0
-
-#define GPIO_FUNC32_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01b0)
-#define GPIO_GPIO_SIG32_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG32_IN_SEL_S 7
-#define GPIO_GPIO_FUNC32_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC32_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC32_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC32_IN_SEL_S 0
-
-#define GPIO_FUNC33_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01b4)
-#define GPIO_GPIO_SIG33_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG33_IN_SEL_S 7
-#define GPIO_GPIO_FUNC33_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC33_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC33_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC33_IN_SEL_S 0
-
-#define GPIO_FUNC34_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01b8)
-#define GPIO_GPIO_SIG34_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG34_IN_SEL_S 7
-#define GPIO_GPIO_FUNC34_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC34_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC34_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC34_IN_SEL_S 0
-
-#define GPIO_FUNC35_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01bc)
-#define GPIO_GPIO_SIG35_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG35_IN_SEL_S 7
-#define GPIO_GPIO_FUNC35_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC35_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC35_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC35_IN_SEL_S 0
-
-#define GPIO_FUNC36_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01c0)
-#define GPIO_GPIO_SIG36_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG36_IN_SEL_S 7
-#define GPIO_GPIO_FUNC36_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC36_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC36_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC36_IN_SEL_S 0
-
-#define GPIO_FUNC37_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01c4)
-#define GPIO_GPIO_SIG37_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG37_IN_SEL_S 7
-#define GPIO_GPIO_FUNC37_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC37_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC37_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC37_IN_SEL_S 0
-
-#define GPIO_FUNC38_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01c8)
-#define GPIO_GPIO_SIG38_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG38_IN_SEL_S 7
-#define GPIO_GPIO_FUNC38_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC38_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC38_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC38_IN_SEL_S 0
-
-#define GPIO_FUNC39_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01cc)
-#define GPIO_GPIO_SIG39_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG39_IN_SEL_S 7
-#define GPIO_GPIO_FUNC39_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC39_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC39_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC39_IN_SEL_S 0
-
-#define GPIO_FUNC40_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01d0)
-#define GPIO_GPIO_SIG40_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG40_IN_SEL_S 7
-#define GPIO_GPIO_FUNC40_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC40_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC40_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC40_IN_SEL_S 0
-
-#define GPIO_FUNC41_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01d4)
-#define GPIO_GPIO_SIG41_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG41_IN_SEL_S 7
-#define GPIO_GPIO_FUNC41_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC41_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC41_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC41_IN_SEL_S 0
-
-#define GPIO_FUNC42_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01d8)
-#define GPIO_GPIO_SIG42_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG42_IN_SEL_S 7
-#define GPIO_GPIO_FUNC42_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC42_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC42_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC42_IN_SEL_S 0
-
-#define GPIO_FUNC43_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01dc)
-#define GPIO_GPIO_SIG43_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG43_IN_SEL_S 7
-#define GPIO_GPIO_FUNC43_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC43_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC43_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC43_IN_SEL_S 0
-
-#define GPIO_FUNC44_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01e0)
-#define GPIO_GPIO_SIG44_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG44_IN_SEL_S 7
-#define GPIO_GPIO_FUNC44_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC44_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC44_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC44_IN_SEL_S 0
-
-#define GPIO_FUNC45_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01e4)
-#define GPIO_GPIO_SIG45_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG45_IN_SEL_S 7
-#define GPIO_GPIO_FUNC45_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC45_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC45_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC45_IN_SEL_S 0
-
-#define GPIO_FUNC46_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01e8)
-#define GPIO_GPIO_SIG46_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG46_IN_SEL_S 7
-#define GPIO_GPIO_FUNC46_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC46_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC46_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC46_IN_SEL_S 0
-
-#define GPIO_FUNC47_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01ec)
-#define GPIO_GPIO_SIG47_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG47_IN_SEL_S 7
-#define GPIO_GPIO_FUNC47_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC47_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC47_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC47_IN_SEL_S 0
-
-#define GPIO_FUNC48_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01f0)
-#define GPIO_GPIO_SIG48_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG48_IN_SEL_S 7
-#define GPIO_GPIO_FUNC48_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC48_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC48_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC48_IN_SEL_S 0
-
-#define GPIO_FUNC49_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01f4)
-#define GPIO_GPIO_SIG49_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG49_IN_SEL_S 7
-#define GPIO_GPIO_FUNC49_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC49_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC49_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC49_IN_SEL_S 0
-
-#define GPIO_FUNC50_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01f8)
-#define GPIO_GPIO_SIG50_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG50_IN_SEL_S 7
-#define GPIO_GPIO_FUNC50_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC50_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC50_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC50_IN_SEL_S 0
-
-#define GPIO_FUNC51_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01fc)
-#define GPIO_GPIO_SIG51_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG51_IN_SEL_S 7
-#define GPIO_GPIO_FUNC51_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC51_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC51_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC51_IN_SEL_S 0
-
-#define GPIO_FUNC52_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0200)
-#define GPIO_GPIO_SIG52_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG52_IN_SEL_S 7
-#define GPIO_GPIO_FUNC52_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC52_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC52_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC52_IN_SEL_S 0
-
-#define GPIO_FUNC53_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0204)
-#define GPIO_GPIO_SIG53_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG53_IN_SEL_S 7
-#define GPIO_GPIO_FUNC53_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC53_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC53_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC53_IN_SEL_S 0
-
-#define GPIO_FUNC54_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0208)
-#define GPIO_GPIO_SIG54_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG54_IN_SEL_S 7
-#define GPIO_GPIO_FUNC54_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC54_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC54_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC54_IN_SEL_S 0
-
-#define GPIO_FUNC55_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x020c)
-#define GPIO_GPIO_SIG55_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG55_IN_SEL_S 7
-#define GPIO_GPIO_FUNC55_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC55_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC55_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC55_IN_SEL_S 0
-
-#define GPIO_FUNC56_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0210)
-#define GPIO_GPIO_SIG56_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG56_IN_SEL_S 7
-#define GPIO_GPIO_FUNC56_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC56_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC56_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC56_IN_SEL_S 0
-
-#define GPIO_FUNC57_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0214)
-#define GPIO_GPIO_SIG57_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG57_IN_SEL_S 7
-#define GPIO_GPIO_FUNC57_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC57_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC57_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC57_IN_SEL_S 0
-
-#define GPIO_FUNC58_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0218)
-#define GPIO_GPIO_SIG58_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG58_IN_SEL_S 7
-#define GPIO_GPIO_FUNC58_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC58_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC58_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC58_IN_SEL_S 0
-
-#define GPIO_FUNC59_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x021c)
-#define GPIO_GPIO_SIG59_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG59_IN_SEL_S 7
-#define GPIO_GPIO_FUNC59_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC59_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC59_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC59_IN_SEL_S 0
-
-#define GPIO_FUNC60_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0220)
-#define GPIO_GPIO_SIG60_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG60_IN_SEL_S 7
-#define GPIO_GPIO_FUNC60_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC60_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC60_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC60_IN_SEL_S 0
-
-#define GPIO_FUNC61_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0224)
-#define GPIO_GPIO_SIG61_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG61_IN_SEL_S 7
-#define GPIO_GPIO_FUNC61_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC61_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC61_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC61_IN_SEL_S 0
-
-#define GPIO_FUNC62_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0228)
-#define GPIO_GPIO_SIG62_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG62_IN_SEL_S 7
-#define GPIO_GPIO_FUNC62_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC62_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC62_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC62_IN_SEL_S 0
-
-#define GPIO_FUNC63_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x022c)
-#define GPIO_GPIO_SIG63_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG63_IN_SEL_S 7
-#define GPIO_GPIO_FUNC63_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC63_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC63_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC63_IN_SEL_S 0
-
-#define GPIO_FUNC64_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0230)
-#define GPIO_GPIO_SIG64_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG64_IN_SEL_S 7
-#define GPIO_GPIO_FUNC64_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC64_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC64_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC64_IN_SEL_S 0
-
-#define GPIO_FUNC65_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0234)
-#define GPIO_GPIO_SIG65_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG65_IN_SEL_S 7
-#define GPIO_GPIO_FUNC65_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC65_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC65_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC65_IN_SEL_S 0
-
-#define GPIO_FUNC66_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0238)
-#define GPIO_GPIO_SIG66_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG66_IN_SEL_S 7
-#define GPIO_GPIO_FUNC66_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC66_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC66_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC66_IN_SEL_S 0
-
-#define GPIO_FUNC67_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x023c)
-#define GPIO_GPIO_SIG67_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG67_IN_SEL_S 7
-#define GPIO_GPIO_FUNC67_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC67_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC67_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC67_IN_SEL_S 0
-
-#define GPIO_FUNC68_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0240)
-#define GPIO_GPIO_SIG68_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG68_IN_SEL_S 7
-#define GPIO_GPIO_FUNC68_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC68_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC68_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC68_IN_SEL_S 0
-
-#define GPIO_FUNC69_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0244)
-#define GPIO_GPIO_SIG69_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG69_IN_SEL_S 7
-#define GPIO_GPIO_FUNC69_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC69_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC69_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC69_IN_SEL_S 0
-
-#define GPIO_FUNC70_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0248)
-#define GPIO_GPIO_SIG70_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG70_IN_SEL_S 7
-#define GPIO_GPIO_FUNC70_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC70_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC70_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC70_IN_SEL_S 0
-
-#define GPIO_FUNC71_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x024c)
-#define GPIO_GPIO_SIG71_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG71_IN_SEL_S 7
-#define GPIO_GPIO_FUNC71_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC71_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC71_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC71_IN_SEL_S 0
-
-#define GPIO_FUNC72_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0250)
-#define GPIO_GPIO_SIG72_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG72_IN_SEL_S 7
-#define GPIO_GPIO_FUNC72_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC72_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC72_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC72_IN_SEL_S 0
-
-#define GPIO_FUNC73_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0254)
-#define GPIO_GPIO_SIG73_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG73_IN_SEL_S 7
-#define GPIO_GPIO_FUNC73_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC73_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC73_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC73_IN_SEL_S 0
-
-#define GPIO_FUNC74_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0258)
-#define GPIO_GPIO_SIG74_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG74_IN_SEL_S 7
-#define GPIO_GPIO_FUNC74_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC74_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC74_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC74_IN_SEL_S 0
-
-#define GPIO_FUNC75_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x025c)
-#define GPIO_GPIO_SIG75_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG75_IN_SEL_S 7
-#define GPIO_GPIO_FUNC75_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC75_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC75_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC75_IN_SEL_S 0
-
-#define GPIO_FUNC76_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0260)
-#define GPIO_GPIO_SIG76_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG76_IN_SEL_S 7
-#define GPIO_GPIO_FUNC76_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC76_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC76_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC76_IN_SEL_S 0
-
-#define GPIO_FUNC77_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0264)
-#define GPIO_GPIO_SIG77_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG77_IN_SEL_S 7
-#define GPIO_GPIO_FUNC77_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC77_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC77_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC77_IN_SEL_S 0
-
-#define GPIO_FUNC78_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0268)
-#define GPIO_GPIO_SIG78_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG78_IN_SEL_S 7
-#define GPIO_GPIO_FUNC78_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC78_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC78_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC78_IN_SEL_S 0
-
-#define GPIO_FUNC79_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x026c)
-#define GPIO_GPIO_SIG79_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG79_IN_SEL_S 7
-#define GPIO_GPIO_FUNC79_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC79_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC79_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC79_IN_SEL_S 0
-
-#define GPIO_FUNC80_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0270)
-#define GPIO_GPIO_SIG80_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG80_IN_SEL_S 7
-#define GPIO_GPIO_FUNC80_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC80_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC80_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC80_IN_SEL_S 0
-
-#define GPIO_FUNC81_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0274)
-#define GPIO_GPIO_SIG81_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG81_IN_SEL_S 7
-#define GPIO_GPIO_FUNC81_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC81_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC81_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC81_IN_SEL_S 0
-
-#define GPIO_FUNC82_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0278)
-#define GPIO_GPIO_SIG82_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG82_IN_SEL_S 7
-#define GPIO_GPIO_FUNC82_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC82_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC82_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC82_IN_SEL_S 0
-
-#define GPIO_FUNC83_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x027c)
-#define GPIO_GPIO_SIG83_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG83_IN_SEL_S 7
-#define GPIO_GPIO_FUNC83_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC83_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC83_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC83_IN_SEL_S 0
-
-#define GPIO_FUNC84_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0280)
-#define GPIO_GPIO_SIG84_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG84_IN_SEL_S 7
-#define GPIO_GPIO_FUNC84_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC84_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC84_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC84_IN_SEL_S 0
-
-#define GPIO_FUNC85_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0284)
-#define GPIO_GPIO_SIG85_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG85_IN_SEL_S 7
-#define GPIO_GPIO_FUNC85_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC85_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC85_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC85_IN_SEL_S 0
-
-#define GPIO_FUNC86_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0288)
-#define GPIO_GPIO_SIG86_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG86_IN_SEL_S 7
-#define GPIO_GPIO_FUNC86_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC86_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC86_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC86_IN_SEL_S 0
-
-#define GPIO_FUNC87_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x028c)
-#define GPIO_GPIO_SIG87_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG87_IN_SEL_S 7
-#define GPIO_GPIO_FUNC87_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC87_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC87_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC87_IN_SEL_S 0
-
-#define GPIO_FUNC88_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0290)
-#define GPIO_GPIO_SIG88_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG88_IN_SEL_S 7
-#define GPIO_GPIO_FUNC88_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC88_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC88_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC88_IN_SEL_S 0
-
-#define GPIO_FUNC89_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0294)
-#define GPIO_GPIO_SIG89_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG89_IN_SEL_S 7
-#define GPIO_GPIO_FUNC89_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC89_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC89_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC89_IN_SEL_S 0
-
-#define GPIO_FUNC90_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0298)
-#define GPIO_GPIO_SIG90_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG90_IN_SEL_S 7
-#define GPIO_GPIO_FUNC90_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC90_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC90_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC90_IN_SEL_S 0
-
-#define GPIO_FUNC91_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x029c)
-#define GPIO_GPIO_SIG91_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG91_IN_SEL_S 7
-#define GPIO_GPIO_FUNC91_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC91_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC91_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC91_IN_SEL_S 0
-
-#define GPIO_FUNC92_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02a0)
-#define GPIO_GPIO_SIG92_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG92_IN_SEL_S 7
-#define GPIO_GPIO_FUNC92_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC92_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC92_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC92_IN_SEL_S 0
-
-#define GPIO_FUNC93_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02a4)
-#define GPIO_GPIO_SIG93_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG93_IN_SEL_S 7
-#define GPIO_GPIO_FUNC93_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC93_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC93_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC93_IN_SEL_S 0
-
-#define GPIO_FUNC94_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02a8)
-#define GPIO_GPIO_SIG94_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG94_IN_SEL_S 7
-#define GPIO_GPIO_FUNC94_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC94_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC94_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC94_IN_SEL_S 0
-
-#define GPIO_FUNC95_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02ac)
-#define GPIO_GPIO_SIG95_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG95_IN_SEL_S 7
-#define GPIO_GPIO_FUNC95_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC95_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC95_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC95_IN_SEL_S 0
-
-#define GPIO_FUNC96_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02b0)
-#define GPIO_GPIO_SIG96_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG96_IN_SEL_S 7
-#define GPIO_GPIO_FUNC96_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC96_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC96_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC96_IN_SEL_S 0
-
-#define GPIO_FUNC97_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02b4)
-#define GPIO_GPIO_SIG97_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG97_IN_SEL_S 7
-#define GPIO_GPIO_FUNC97_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC97_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC97_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC97_IN_SEL_S 0
-
-#define GPIO_FUNC98_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02b8)
-#define GPIO_GPIO_SIG98_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG98_IN_SEL_S 7
-#define GPIO_GPIO_FUNC98_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC98_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC98_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC98_IN_SEL_S 0
-
-#define GPIO_FUNC99_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02bc)
-#define GPIO_GPIO_SIG99_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG99_IN_SEL_S 7
-#define GPIO_GPIO_FUNC99_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC99_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC99_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC99_IN_SEL_S 0
-
-#define GPIO_FUNC100_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02c0)
-#define GPIO_GPIO_SIG100_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG100_IN_SEL_S 7
-#define GPIO_GPIO_FUNC100_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC100_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC100_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC100_IN_SEL_S 0
-
-#define GPIO_FUNC101_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02c4)
-#define GPIO_GPIO_SIG101_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG101_IN_SEL_S 7
-#define GPIO_GPIO_FUNC101_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC101_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC101_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC101_IN_SEL_S 0
-
-#define GPIO_FUNC102_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02c8)
-#define GPIO_GPIO_SIG102_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG102_IN_SEL_S 7
-#define GPIO_GPIO_FUNC102_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC102_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC102_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC102_IN_SEL_S 0
-
-#define GPIO_FUNC103_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02cc)
-#define GPIO_GPIO_SIG103_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG103_IN_SEL_S 7
-#define GPIO_GPIO_FUNC103_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC103_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC103_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC103_IN_SEL_S 0
-
-#define GPIO_FUNC104_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02d0)
-#define GPIO_GPIO_SIG104_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG104_IN_SEL_S 7
-#define GPIO_GPIO_FUNC104_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC104_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC104_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC104_IN_SEL_S 0
-
-#define GPIO_FUNC105_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02d4)
-#define GPIO_GPIO_SIG105_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG105_IN_SEL_S 7
-#define GPIO_GPIO_FUNC105_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC105_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC105_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC105_IN_SEL_S 0
-
-#define GPIO_FUNC106_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02d8)
-#define GPIO_GPIO_SIG106_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG106_IN_SEL_S 7
-#define GPIO_GPIO_FUNC106_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC106_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC106_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC106_IN_SEL_S 0
-
-#define GPIO_FUNC107_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02dc)
-#define GPIO_GPIO_SIG107_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG107_IN_SEL_S 7
-#define GPIO_GPIO_FUNC107_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC107_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC107_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC107_IN_SEL_S 0
-
-#define GPIO_FUNC108_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02e0)
-#define GPIO_GPIO_SIG108_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG108_IN_SEL_S 7
-#define GPIO_GPIO_FUNC108_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC108_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC108_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC108_IN_SEL_S 0
-
-#define GPIO_FUNC109_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02e4)
-#define GPIO_GPIO_SIG109_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG109_IN_SEL_S 7
-#define GPIO_GPIO_FUNC109_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC109_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC109_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC109_IN_SEL_S 0
-
-#define GPIO_FUNC110_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02e8)
-#define GPIO_GPIO_SIG110_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG110_IN_SEL_S 7
-#define GPIO_GPIO_FUNC110_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC110_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC110_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC110_IN_SEL_S 0
-
-#define GPIO_FUNC111_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02ec)
-#define GPIO_GPIO_SIG111_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG111_IN_SEL_S 7
-#define GPIO_GPIO_FUNC111_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC111_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC111_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC111_IN_SEL_S 0
-
-#define GPIO_FUNC112_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02f0)
-#define GPIO_GPIO_SIG112_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG112_IN_SEL_S 7
-#define GPIO_GPIO_FUNC112_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC112_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC112_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC112_IN_SEL_S 0
-
-#define GPIO_FUNC113_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02f4)
-#define GPIO_GPIO_SIG113_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG113_IN_SEL_S 7
-#define GPIO_GPIO_FUNC113_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC113_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC113_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC113_IN_SEL_S 0
-
-#define GPIO_FUNC114_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02f8)
-#define GPIO_GPIO_SIG114_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG114_IN_SEL_S 7
-#define GPIO_GPIO_FUNC114_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC114_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC114_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC114_IN_SEL_S 0
-
-#define GPIO_FUNC115_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02fc)
-#define GPIO_GPIO_SIG115_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG115_IN_SEL_S 7
-#define GPIO_GPIO_FUNC115_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC115_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC115_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC115_IN_SEL_S 0
-
-#define GPIO_FUNC116_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0300)
-#define GPIO_GPIO_SIG116_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG116_IN_SEL_S 7
-#define GPIO_GPIO_FUNC116_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC116_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC116_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC116_IN_SEL_S 0
-
-#define GPIO_FUNC117_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0304)
-#define GPIO_GPIO_SIG117_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG117_IN_SEL_S 7
-#define GPIO_GPIO_FUNC117_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC117_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC117_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC117_IN_SEL_S 0
-
-#define GPIO_FUNC118_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0308)
-#define GPIO_GPIO_SIG118_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG118_IN_SEL_S 7
-#define GPIO_GPIO_FUNC118_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC118_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC118_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC118_IN_SEL_S 0
-
-#define GPIO_FUNC119_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x030c)
-#define GPIO_GPIO_SIG119_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG119_IN_SEL_S 7
-#define GPIO_GPIO_FUNC119_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC119_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC119_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC119_IN_SEL_S 0
-
-#define GPIO_FUNC120_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0310)
-#define GPIO_GPIO_SIG120_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG120_IN_SEL_S 7
-#define GPIO_GPIO_FUNC120_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC120_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC120_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC120_IN_SEL_S 0
-
-#define GPIO_FUNC121_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0314)
-#define GPIO_GPIO_SIG121_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG121_IN_SEL_S 7
-#define GPIO_GPIO_FUNC121_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC121_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC121_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC121_IN_SEL_S 0
-
-#define GPIO_FUNC122_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0318)
-#define GPIO_GPIO_SIG122_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG122_IN_SEL_S 7
-#define GPIO_GPIO_FUNC122_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC122_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC122_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC122_IN_SEL_S 0
-
-#define GPIO_FUNC123_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x031c)
-#define GPIO_GPIO_SIG123_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG123_IN_SEL_S 7
-#define GPIO_GPIO_FUNC123_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC123_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC123_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC123_IN_SEL_S 0
-
-#define GPIO_FUNC124_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0320)
-#define GPIO_GPIO_SIG124_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG124_IN_SEL_S 7
-#define GPIO_GPIO_FUNC124_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC124_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC124_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC124_IN_SEL_S 0
-
-#define GPIO_FUNC125_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0324)
-#define GPIO_GPIO_SIG125_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG125_IN_SEL_S 7
-#define GPIO_GPIO_FUNC125_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC125_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC125_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC125_IN_SEL_S 0
-
-#define GPIO_FUNC126_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0328)
-#define GPIO_GPIO_SIG126_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG126_IN_SEL_S 7
-#define GPIO_GPIO_FUNC126_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC126_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC126_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC126_IN_SEL_S 0
-
-#define GPIO_FUNC127_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x032c)
-#define GPIO_GPIO_SIG127_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG127_IN_SEL_S 7
-#define GPIO_GPIO_FUNC127_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC127_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC127_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC127_IN_SEL_S 0
-
-#define GPIO_FUNC128_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0330)
-#define GPIO_GPIO_SIG128_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG128_IN_SEL_S 7
-#define GPIO_GPIO_FUNC128_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC128_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC128_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC128_IN_SEL_S 0
-
-#define GPIO_FUNC129_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0334)
-#define GPIO_GPIO_SIG129_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG129_IN_SEL_S 7
-#define GPIO_GPIO_FUNC129_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC129_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC129_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC129_IN_SEL_S 0
-
-#define GPIO_FUNC130_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0338)
-#define GPIO_GPIO_SIG130_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG130_IN_SEL_S 7
-#define GPIO_GPIO_FUNC130_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC130_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC130_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC130_IN_SEL_S 0
-
-#define GPIO_FUNC131_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x033c)
-#define GPIO_GPIO_SIG131_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG131_IN_SEL_S 7
-#define GPIO_GPIO_FUNC131_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC131_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC131_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC131_IN_SEL_S 0
-
-#define GPIO_FUNC132_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0340)
-#define GPIO_GPIO_SIG132_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG132_IN_SEL_S 7
-#define GPIO_GPIO_FUNC132_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC132_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC132_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC132_IN_SEL_S 0
-
-#define GPIO_FUNC133_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0344)
-#define GPIO_GPIO_SIG133_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG133_IN_SEL_S 7
-#define GPIO_GPIO_FUNC133_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC133_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC133_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC133_IN_SEL_S 0
-
-#define GPIO_FUNC134_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0348)
-#define GPIO_GPIO_SIG134_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG134_IN_SEL_S 7
-#define GPIO_GPIO_FUNC134_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC134_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC134_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC134_IN_SEL_S 0
-
-#define GPIO_FUNC135_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x034c)
-#define GPIO_GPIO_SIG135_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG135_IN_SEL_S 7
-#define GPIO_GPIO_FUNC135_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC135_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC135_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC135_IN_SEL_S 0
-
-#define GPIO_FUNC136_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0350)
-#define GPIO_GPIO_SIG136_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG136_IN_SEL_S 7
-#define GPIO_GPIO_FUNC136_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC136_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC136_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC136_IN_SEL_S 0
-
-#define GPIO_FUNC137_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0354)
-#define GPIO_GPIO_SIG137_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG137_IN_SEL_S 7
-#define GPIO_GPIO_FUNC137_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC137_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC137_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC137_IN_SEL_S 0
-
-#define GPIO_FUNC138_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0358)
-#define GPIO_GPIO_SIG138_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG138_IN_SEL_S 7
-#define GPIO_GPIO_FUNC138_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC138_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC138_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC138_IN_SEL_S 0
-
-#define GPIO_FUNC139_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x035c)
-#define GPIO_GPIO_SIG139_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG139_IN_SEL_S 7
-#define GPIO_GPIO_FUNC139_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC139_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC139_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC139_IN_SEL_S 0
-
-#define GPIO_FUNC140_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0360)
-#define GPIO_GPIO_SIG140_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG140_IN_SEL_S 7
-#define GPIO_GPIO_FUNC140_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC140_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC140_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC140_IN_SEL_S 0
-
-#define GPIO_FUNC141_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0364)
-#define GPIO_GPIO_SIG141_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG141_IN_SEL_S 7
-#define GPIO_GPIO_FUNC141_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC141_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC141_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC141_IN_SEL_S 0
-
-#define GPIO_FUNC142_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0368)
-#define GPIO_GPIO_SIG142_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG142_IN_SEL_S 7
-#define GPIO_GPIO_FUNC142_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC142_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC142_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC142_IN_SEL_S 0
-
-#define GPIO_FUNC143_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x036c)
-#define GPIO_GPIO_SIG143_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG143_IN_SEL_S 7
-#define GPIO_GPIO_FUNC143_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC143_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC143_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC143_IN_SEL_S 0
-
-#define GPIO_FUNC144_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0370)
-#define GPIO_GPIO_SIG144_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG144_IN_SEL_S 7
-#define GPIO_GPIO_FUNC144_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC144_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC144_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC144_IN_SEL_S 0
-
-#define GPIO_FUNC145_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0374)
-#define GPIO_GPIO_SIG145_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG145_IN_SEL_S 7
-#define GPIO_GPIO_FUNC145_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC145_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC145_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC145_IN_SEL_S 0
-
-#define GPIO_FUNC146_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0378)
-#define GPIO_GPIO_SIG146_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG146_IN_SEL_S 7
-#define GPIO_GPIO_FUNC146_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC146_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC146_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC146_IN_SEL_S 0
-
-#define GPIO_FUNC147_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x037c)
-#define GPIO_GPIO_SIG147_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG147_IN_SEL_S 7
-#define GPIO_GPIO_FUNC147_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC147_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC147_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC147_IN_SEL_S 0
-
-#define GPIO_FUNC148_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0380)
-#define GPIO_GPIO_SIG148_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG148_IN_SEL_S 7
-#define GPIO_GPIO_FUNC148_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC148_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC148_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC148_IN_SEL_S 0
-
-#define GPIO_FUNC149_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0384)
-#define GPIO_GPIO_SIG149_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG149_IN_SEL_S 7
-#define GPIO_GPIO_FUNC149_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC149_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC149_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC149_IN_SEL_S 0
-
-#define GPIO_FUNC150_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0388)
-#define GPIO_GPIO_SIG150_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG150_IN_SEL_S 7
-#define GPIO_GPIO_FUNC150_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC150_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC150_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC150_IN_SEL_S 0
-
-#define GPIO_FUNC151_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x038c)
-#define GPIO_GPIO_SIG151_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG151_IN_SEL_S 7
-#define GPIO_GPIO_FUNC151_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC151_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC151_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC151_IN_SEL_S 0
-
-#define GPIO_FUNC152_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0390)
-#define GPIO_GPIO_SIG152_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG152_IN_SEL_S 7
-#define GPIO_GPIO_FUNC152_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC152_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC152_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC152_IN_SEL_S 0
-
-#define GPIO_FUNC153_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0394)
-#define GPIO_GPIO_SIG153_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG153_IN_SEL_S 7
-#define GPIO_GPIO_FUNC153_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC153_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC153_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC153_IN_SEL_S 0
-
-#define GPIO_FUNC154_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0398)
-#define GPIO_GPIO_SIG154_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG154_IN_SEL_S 7
-#define GPIO_GPIO_FUNC154_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC154_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC154_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC154_IN_SEL_S 0
-
-#define GPIO_FUNC155_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x039c)
-#define GPIO_GPIO_SIG155_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG155_IN_SEL_S 7
-#define GPIO_GPIO_FUNC155_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC155_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC155_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC155_IN_SEL_S 0
-
-#define GPIO_FUNC156_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03a0)
-#define GPIO_GPIO_SIG156_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG156_IN_SEL_S 7
-#define GPIO_GPIO_FUNC156_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC156_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC156_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC156_IN_SEL_S 0
-
-#define GPIO_FUNC157_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03a4)
-#define GPIO_GPIO_SIG157_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG157_IN_SEL_S 7
-#define GPIO_GPIO_FUNC157_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC157_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC157_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC157_IN_SEL_S 0
-
-#define GPIO_FUNC158_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03a8)
-#define GPIO_GPIO_SIG158_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG158_IN_SEL_S 7
-#define GPIO_GPIO_FUNC158_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC158_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC158_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC158_IN_SEL_S 0
-
-#define GPIO_FUNC159_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03ac)
-#define GPIO_GPIO_SIG159_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG159_IN_SEL_S 7
-#define GPIO_GPIO_FUNC159_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC159_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC159_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC159_IN_SEL_S 0
-
-#define GPIO_FUNC160_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03b0)
-#define GPIO_GPIO_SIG160_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG160_IN_SEL_S 7
-#define GPIO_GPIO_FUNC160_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC160_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC160_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC160_IN_SEL_S 0
-
-#define GPIO_FUNC161_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03b4)
-#define GPIO_GPIO_SIG161_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG161_IN_SEL_S 7
-#define GPIO_GPIO_FUNC161_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC161_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC161_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC161_IN_SEL_S 0
-
-#define GPIO_FUNC162_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03b8)
-#define GPIO_GPIO_SIG162_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG162_IN_SEL_S 7
-#define GPIO_GPIO_FUNC162_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC162_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC162_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC162_IN_SEL_S 0
-
-#define GPIO_FUNC163_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03bc)
-#define GPIO_GPIO_SIG163_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG163_IN_SEL_S 7
-#define GPIO_GPIO_FUNC163_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC163_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC163_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC163_IN_SEL_S 0
-
-#define GPIO_FUNC164_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03c0)
-#define GPIO_GPIO_SIG164_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG164_IN_SEL_S 7
-#define GPIO_GPIO_FUNC164_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC164_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC164_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC164_IN_SEL_S 0
-
-#define GPIO_FUNC165_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03c4)
-#define GPIO_GPIO_SIG165_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG165_IN_SEL_S 7
-#define GPIO_GPIO_FUNC165_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC165_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC165_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC165_IN_SEL_S 0
-
-#define GPIO_FUNC166_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03c8)
-#define GPIO_GPIO_SIG166_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG166_IN_SEL_S 7
-#define GPIO_GPIO_FUNC166_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC166_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC166_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC166_IN_SEL_S 0
-
-#define GPIO_FUNC167_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03cc)
-#define GPIO_GPIO_SIG167_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG167_IN_SEL_S 7
-#define GPIO_GPIO_FUNC167_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC167_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC167_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC167_IN_SEL_S 0
-
-#define GPIO_FUNC168_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03d0)
-#define GPIO_GPIO_SIG168_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG168_IN_SEL_S 7
-#define GPIO_GPIO_FUNC168_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC168_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC168_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC168_IN_SEL_S 0
-
-#define GPIO_FUNC169_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03d4)
-#define GPIO_GPIO_SIG169_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG169_IN_SEL_S 7
-#define GPIO_GPIO_FUNC169_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC169_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC169_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC169_IN_SEL_S 0
-
-#define GPIO_FUNC170_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03d8)
-#define GPIO_GPIO_SIG170_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG170_IN_SEL_S 7
-#define GPIO_GPIO_FUNC170_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC170_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC170_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC170_IN_SEL_S 0
-
-#define GPIO_FUNC171_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03dc)
-#define GPIO_GPIO_SIG171_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG171_IN_SEL_S 7
-#define GPIO_GPIO_FUNC171_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC171_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC171_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC171_IN_SEL_S 0
-
-#define GPIO_FUNC172_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03e0)
-#define GPIO_GPIO_SIG172_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG172_IN_SEL_S 7
-#define GPIO_GPIO_FUNC172_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC172_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC172_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC172_IN_SEL_S 0
-
-#define GPIO_FUNC173_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03e4)
-#define GPIO_GPIO_SIG173_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG173_IN_SEL_S 7
-#define GPIO_GPIO_FUNC173_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC173_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC173_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC173_IN_SEL_S 0
-
-#define GPIO_FUNC174_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03e8)
-#define GPIO_GPIO_SIG174_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG174_IN_SEL_S 7
-#define GPIO_GPIO_FUNC174_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC174_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC174_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC174_IN_SEL_S 0
-
-#define GPIO_FUNC175_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03ec)
-#define GPIO_GPIO_SIG175_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG175_IN_SEL_S 7
-#define GPIO_GPIO_FUNC175_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC175_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC175_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC175_IN_SEL_S 0
-
-#define GPIO_FUNC176_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03f0)
-#define GPIO_GPIO_SIG176_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG176_IN_SEL_S 7
-#define GPIO_GPIO_FUNC176_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC176_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC176_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC176_IN_SEL_S 0
-
-#define GPIO_FUNC177_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03f4)
-#define GPIO_GPIO_SIG177_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG177_IN_SEL_S 7
-#define GPIO_GPIO_FUNC177_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC177_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC177_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC177_IN_SEL_S 0
-
-#define GPIO_FUNC178_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03f8)
-#define GPIO_GPIO_SIG178_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG178_IN_SEL_S 7
-#define GPIO_GPIO_FUNC178_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC178_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC178_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC178_IN_SEL_S 0
-
-#define GPIO_FUNC179_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03fc)
-#define GPIO_GPIO_SIG179_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG179_IN_SEL_S 7
-#define GPIO_GPIO_FUNC179_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC179_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC179_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC179_IN_SEL_S 0
-
-#define GPIO_FUNC180_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0400)
-#define GPIO_GPIO_SIG180_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG180_IN_SEL_S 7
-#define GPIO_GPIO_FUNC180_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC180_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC180_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC180_IN_SEL_S 0
-
-#define GPIO_FUNC181_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0404)
-#define GPIO_GPIO_SIG181_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG181_IN_SEL_S 7
-#define GPIO_GPIO_FUNC181_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC181_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC181_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC181_IN_SEL_S 0
-
-#define GPIO_FUNC182_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0408)
-#define GPIO_GPIO_SIG182_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG182_IN_SEL_S 7
-#define GPIO_GPIO_FUNC182_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC182_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC182_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC182_IN_SEL_S 0
-
-#define GPIO_FUNC183_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x040c)
-#define GPIO_GPIO_SIG183_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG183_IN_SEL_S 7
-#define GPIO_GPIO_FUNC183_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC183_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC183_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC183_IN_SEL_S 0
-
-#define GPIO_FUNC184_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0410)
-#define GPIO_GPIO_SIG184_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG184_IN_SEL_S 7
-#define GPIO_GPIO_FUNC184_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC184_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC184_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC184_IN_SEL_S 0
-
-#define GPIO_FUNC185_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0414)
-#define GPIO_GPIO_SIG185_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG185_IN_SEL_S 7
-#define GPIO_GPIO_FUNC185_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC185_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC185_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC185_IN_SEL_S 0
-
-#define GPIO_FUNC186_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0418)
-#define GPIO_GPIO_SIG186_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG186_IN_SEL_S 7
-#define GPIO_GPIO_FUNC186_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC186_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC186_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC186_IN_SEL_S 0
-
-#define GPIO_FUNC187_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x041c)
-#define GPIO_GPIO_SIG187_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG187_IN_SEL_S 7
-#define GPIO_GPIO_FUNC187_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC187_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC187_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC187_IN_SEL_S 0
-
-#define GPIO_FUNC188_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0420)
-#define GPIO_GPIO_SIG188_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG188_IN_SEL_S 7
-#define GPIO_GPIO_FUNC188_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC188_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC188_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC188_IN_SEL_S 0
-
-#define GPIO_FUNC189_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0424)
-#define GPIO_GPIO_SIG189_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG189_IN_SEL_S 7
-#define GPIO_GPIO_FUNC189_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC189_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC189_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC189_IN_SEL_S 0
-
-#define GPIO_FUNC190_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0428)
-#define GPIO_GPIO_SIG190_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG190_IN_SEL_S 7
-#define GPIO_GPIO_FUNC190_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC190_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC190_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC190_IN_SEL_S 0
-
-#define GPIO_FUNC191_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x042c)
-#define GPIO_GPIO_SIG191_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG191_IN_SEL_S 7
-#define GPIO_GPIO_FUNC191_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC191_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC191_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC191_IN_SEL_S 0
-
-#define GPIO_FUNC192_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0430)
-#define GPIO_GPIO_SIG192_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG192_IN_SEL_S 7
-#define GPIO_GPIO_FUNC192_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC192_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC192_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC192_IN_SEL_S 0
-
-#define GPIO_FUNC193_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0434)
-#define GPIO_GPIO_SIG193_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG193_IN_SEL_S 7
-#define GPIO_GPIO_FUNC193_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC193_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC193_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC193_IN_SEL_S 0
-
-#define GPIO_FUNC194_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0438)
-#define GPIO_GPIO_SIG194_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG194_IN_SEL_S 7
-#define GPIO_GPIO_FUNC194_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC194_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC194_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC194_IN_SEL_S 0
-
-#define GPIO_FUNC195_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x043c)
-#define GPIO_GPIO_SIG195_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG195_IN_SEL_S 7
-#define GPIO_GPIO_FUNC195_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC195_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC195_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC195_IN_SEL_S 0
-
-#define GPIO_FUNC196_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0440)
-#define GPIO_GPIO_SIG196_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG196_IN_SEL_S 7
-#define GPIO_GPIO_FUNC196_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC196_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC196_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC196_IN_SEL_S 0
-
-#define GPIO_FUNC197_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0444)
-#define GPIO_GPIO_SIG197_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG197_IN_SEL_S 7
-#define GPIO_GPIO_FUNC197_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC197_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC197_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC197_IN_SEL_S 0
-
-#define GPIO_FUNC198_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0448)
-#define GPIO_GPIO_SIG198_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG198_IN_SEL_S 7
-#define GPIO_GPIO_FUNC198_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC198_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC198_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC198_IN_SEL_S 0
-
-#define GPIO_FUNC199_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x044c)
-#define GPIO_GPIO_SIG199_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG199_IN_SEL_S 7
-#define GPIO_GPIO_FUNC199_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC199_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC199_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC199_IN_SEL_S 0
-
-#define GPIO_FUNC200_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0450)
-#define GPIO_GPIO_SIG200_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG200_IN_SEL_S 7
-#define GPIO_GPIO_FUNC200_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC200_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC200_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC200_IN_SEL_S 0
-
-#define GPIO_FUNC201_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0454)
-#define GPIO_GPIO_SIG201_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG201_IN_SEL_S 7
-#define GPIO_GPIO_FUNC201_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC201_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC201_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC201_IN_SEL_S 0
-
-#define GPIO_FUNC202_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0458)
-#define GPIO_GPIO_SIG202_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG202_IN_SEL_S 7
-#define GPIO_GPIO_FUNC202_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC202_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC202_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC202_IN_SEL_S 0
-
-#define GPIO_FUNC203_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x045c)
-#define GPIO_GPIO_SIG203_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG203_IN_SEL_S 7
-#define GPIO_GPIO_FUNC203_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC203_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC203_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC203_IN_SEL_S 0
-
-#define GPIO_FUNC204_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0460)
-#define GPIO_GPIO_SIG204_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG204_IN_SEL_S 7
-#define GPIO_GPIO_FUNC204_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC204_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC204_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC204_IN_SEL_S 0
-
-#define GPIO_FUNC205_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0464)
-#define GPIO_GPIO_SIG205_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG205_IN_SEL_S 7
-#define GPIO_GPIO_FUNC205_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC205_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC205_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC205_IN_SEL_S 0
-
-#define GPIO_FUNC206_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0468)
-#define GPIO_GPIO_SIG206_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG206_IN_SEL_S 7
-#define GPIO_GPIO_FUNC206_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC206_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC206_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC206_IN_SEL_S 0
-
-#define GPIO_FUNC207_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x046c)
-#define GPIO_GPIO_SIG207_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG207_IN_SEL_S 7
-#define GPIO_GPIO_FUNC207_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC207_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC207_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC207_IN_SEL_S 0
-
-#define GPIO_FUNC208_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0470)
-#define GPIO_GPIO_SIG208_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG208_IN_SEL_S 7
-#define GPIO_GPIO_FUNC208_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC208_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC208_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC208_IN_SEL_S 0
-
-#define GPIO_FUNC209_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0474)
-#define GPIO_GPIO_SIG209_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG209_IN_SEL_S 7
-#define GPIO_GPIO_FUNC209_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC209_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC209_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC209_IN_SEL_S 0
-
-#define GPIO_FUNC210_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0478)
-#define GPIO_GPIO_SIG210_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG210_IN_SEL_S 7
-#define GPIO_GPIO_FUNC210_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC210_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC210_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC210_IN_SEL_S 0
-
-#define GPIO_FUNC211_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x047c)
-#define GPIO_GPIO_SIG211_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG211_IN_SEL_S 7
-#define GPIO_GPIO_FUNC211_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC211_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC211_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC211_IN_SEL_S 0
-
-#define GPIO_FUNC212_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0480)
-#define GPIO_GPIO_SIG212_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG212_IN_SEL_S 7
-#define GPIO_GPIO_FUNC212_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC212_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC212_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC212_IN_SEL_S 0
-
-#define GPIO_FUNC213_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0484)
-#define GPIO_GPIO_SIG213_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG213_IN_SEL_S 7
-#define GPIO_GPIO_FUNC213_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC213_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC213_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC213_IN_SEL_S 0
-
-#define GPIO_FUNC214_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0488)
-#define GPIO_GPIO_SIG214_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG214_IN_SEL_S 7
-#define GPIO_GPIO_FUNC214_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC214_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC214_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC214_IN_SEL_S 0
-
-#define GPIO_FUNC215_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x048c)
-#define GPIO_GPIO_SIG215_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG215_IN_SEL_S 7
-#define GPIO_GPIO_FUNC215_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC215_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC215_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC215_IN_SEL_S 0
-
-#define GPIO_FUNC216_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0490)
-#define GPIO_GPIO_SIG216_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG216_IN_SEL_S 7
-#define GPIO_GPIO_FUNC216_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC216_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC216_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC216_IN_SEL_S 0
-
-#define GPIO_FUNC217_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0494)
-#define GPIO_GPIO_SIG217_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG217_IN_SEL_S 7
-#define GPIO_GPIO_FUNC217_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC217_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC217_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC217_IN_SEL_S 0
-
-#define GPIO_FUNC218_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0498)
-#define GPIO_GPIO_SIG218_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG218_IN_SEL_S 7
-#define GPIO_GPIO_FUNC218_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC218_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC218_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC218_IN_SEL_S 0
-
-#define GPIO_FUNC219_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x049c)
-#define GPIO_GPIO_SIG219_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG219_IN_SEL_S 7
-#define GPIO_GPIO_FUNC219_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC219_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC219_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC219_IN_SEL_S 0
-
-#define GPIO_FUNC220_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04a0)
-#define GPIO_GPIO_SIG220_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG220_IN_SEL_S 7
-#define GPIO_GPIO_FUNC220_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC220_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC220_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC220_IN_SEL_S 0
-
-#define GPIO_FUNC221_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04a4)
-#define GPIO_GPIO_SIG221_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG221_IN_SEL_S 7
-#define GPIO_GPIO_FUNC221_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC221_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC221_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC221_IN_SEL_S 0
-
-#define GPIO_FUNC222_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04a8)
-#define GPIO_GPIO_SIG222_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG222_IN_SEL_S 7
-#define GPIO_GPIO_FUNC222_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC222_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC222_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC222_IN_SEL_S 0
-
-#define GPIO_FUNC223_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04ac)
-#define GPIO_GPIO_SIG223_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG223_IN_SEL_S 7
-#define GPIO_GPIO_FUNC223_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC223_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC223_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC223_IN_SEL_S 0
-
-#define GPIO_FUNC224_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04b0)
-#define GPIO_GPIO_SIG224_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG224_IN_SEL_S 7
-#define GPIO_GPIO_FUNC224_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC224_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC224_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC224_IN_SEL_S 0
-
-#define GPIO_FUNC225_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04b4)
-#define GPIO_GPIO_SIG225_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG225_IN_SEL_S 7
-#define GPIO_GPIO_FUNC225_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC225_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC225_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC225_IN_SEL_S 0
-
-#define GPIO_FUNC226_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04b8)
-#define GPIO_GPIO_SIG226_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG226_IN_SEL_S 7
-#define GPIO_GPIO_FUNC226_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC226_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC226_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC226_IN_SEL_S 0
-
-#define GPIO_FUNC227_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04bc)
-#define GPIO_GPIO_SIG227_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG227_IN_SEL_S 7
-#define GPIO_GPIO_FUNC227_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC227_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC227_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC227_IN_SEL_S 0
-
-#define GPIO_FUNC228_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04c0)
-#define GPIO_GPIO_SIG228_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG228_IN_SEL_S 7
-#define GPIO_GPIO_FUNC228_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC228_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC228_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC228_IN_SEL_S 0
-
-#define GPIO_FUNC229_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04c4)
-#define GPIO_GPIO_SIG229_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG229_IN_SEL_S 7
-#define GPIO_GPIO_FUNC229_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC229_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC229_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC229_IN_SEL_S 0
-
-#define GPIO_FUNC230_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04c8)
-#define GPIO_GPIO_SIG230_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG230_IN_SEL_S 7
-#define GPIO_GPIO_FUNC230_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC230_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC230_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC230_IN_SEL_S 0
-
-#define GPIO_FUNC231_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04cc)
-#define GPIO_GPIO_SIG231_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG231_IN_SEL_S 7
-#define GPIO_GPIO_FUNC231_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC231_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC231_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC231_IN_SEL_S 0
-
-#define GPIO_FUNC232_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04d0)
-#define GPIO_GPIO_SIG232_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG232_IN_SEL_S 7
-#define GPIO_GPIO_FUNC232_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC232_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC232_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC232_IN_SEL_S 0
-
-#define GPIO_FUNC233_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04d4)
-#define GPIO_GPIO_SIG233_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG233_IN_SEL_S 7
-#define GPIO_GPIO_FUNC233_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC233_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC233_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC233_IN_SEL_S 0
-
-#define GPIO_FUNC234_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04d8)
-#define GPIO_GPIO_SIG234_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG234_IN_SEL_S 7
-#define GPIO_GPIO_FUNC234_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC234_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC234_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC234_IN_SEL_S 0
-
-#define GPIO_FUNC235_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04dc)
-#define GPIO_GPIO_SIG235_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG235_IN_SEL_S 7
-#define GPIO_GPIO_FUNC235_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC235_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC235_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC235_IN_SEL_S 0
-
-#define GPIO_FUNC236_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04e0)
-#define GPIO_GPIO_SIG236_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG236_IN_SEL_S 7
-#define GPIO_GPIO_FUNC236_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC236_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC236_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC236_IN_SEL_S 0
-
-#define GPIO_FUNC237_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04e4)
-#define GPIO_GPIO_SIG237_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG237_IN_SEL_S 7
-#define GPIO_GPIO_FUNC237_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC237_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC237_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC237_IN_SEL_S 0
-
-#define GPIO_FUNC238_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04e8)
-#define GPIO_GPIO_SIG238_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG238_IN_SEL_S 7
-#define GPIO_GPIO_FUNC238_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC238_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC238_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC238_IN_SEL_S 0
-
-#define GPIO_FUNC239_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04ec)
-#define GPIO_GPIO_SIG239_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG239_IN_SEL_S 7
-#define GPIO_GPIO_FUNC239_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC239_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC239_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC239_IN_SEL_S 0
-
-#define GPIO_FUNC240_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04f0)
-#define GPIO_GPIO_SIG240_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG240_IN_SEL_S 7
-#define GPIO_GPIO_FUNC240_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC240_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC240_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC240_IN_SEL_S 0
-
-#define GPIO_FUNC241_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04f4)
-#define GPIO_GPIO_SIG241_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG241_IN_SEL_S 7
-#define GPIO_GPIO_FUNC241_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC241_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC241_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC241_IN_SEL_S 0
-
-#define GPIO_FUNC242_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04f8)
-#define GPIO_GPIO_SIG242_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG242_IN_SEL_S 7
-#define GPIO_GPIO_FUNC242_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC242_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC242_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC242_IN_SEL_S 0
-
-#define GPIO_FUNC243_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04fc)
-#define GPIO_GPIO_SIG243_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG243_IN_SEL_S 7
-#define GPIO_GPIO_FUNC243_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC243_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC243_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC243_IN_SEL_S 0
-
-#define GPIO_FUNC244_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0500)
-#define GPIO_GPIO_SIG244_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG244_IN_SEL_S 7
-#define GPIO_GPIO_FUNC244_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC244_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC244_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC244_IN_SEL_S 0
-
-#define GPIO_FUNC245_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0504)
-#define GPIO_GPIO_SIG245_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG245_IN_SEL_S 7
-#define GPIO_GPIO_FUNC245_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC245_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC245_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC245_IN_SEL_S 0
-
-#define GPIO_FUNC246_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0508)
-#define GPIO_GPIO_SIG246_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG246_IN_SEL_S 7
-#define GPIO_GPIO_FUNC246_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC246_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC246_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC246_IN_SEL_S 0
-
-#define GPIO_FUNC247_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x050c)
-#define GPIO_GPIO_SIG247_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG247_IN_SEL_S 7
-#define GPIO_GPIO_FUNC247_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC247_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC247_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC247_IN_SEL_S 0
-
-#define GPIO_FUNC248_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0510)
-#define GPIO_GPIO_SIG248_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG248_IN_SEL_S 7
-#define GPIO_GPIO_FUNC248_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC248_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC248_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC248_IN_SEL_S 0
-
-#define GPIO_FUNC249_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0514)
-#define GPIO_GPIO_SIG249_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG249_IN_SEL_S 7
-#define GPIO_GPIO_FUNC249_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC249_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC249_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC249_IN_SEL_S 0
-
-#define GPIO_FUNC250_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0518)
-#define GPIO_GPIO_SIG250_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG250_IN_SEL_S 7
-#define GPIO_GPIO_FUNC250_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC250_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC250_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC250_IN_SEL_S 0
-
-#define GPIO_FUNC251_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x051c)
-#define GPIO_GPIO_SIG251_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG251_IN_SEL_S 7
-#define GPIO_GPIO_FUNC251_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC251_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC251_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC251_IN_SEL_S 0
-
-#define GPIO_FUNC252_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0520)
-#define GPIO_GPIO_SIG252_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG252_IN_SEL_S 7
-#define GPIO_GPIO_FUNC252_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC252_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC252_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC252_IN_SEL_S 0
-
-#define GPIO_FUNC253_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0524)
-#define GPIO_GPIO_SIG253_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG253_IN_SEL_S 7
-#define GPIO_GPIO_FUNC253_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC253_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC253_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC253_IN_SEL_S 0
-
-#define GPIO_FUNC254_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0528)
-#define GPIO_GPIO_SIG254_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG254_IN_SEL_S 7
-#define GPIO_GPIO_FUNC254_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC254_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC254_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC254_IN_SEL_S 0
-
-#define GPIO_FUNC255_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x052c)
-#define GPIO_GPIO_SIG255_IN_SEL (BIT(7))
-#define GPIO_GPIO_SIG255_IN_SEL_S 7
-#define GPIO_GPIO_FUNC255_IN_INV_SEL (BIT(6))
-#define GPIO_GPIO_FUNC255_IN_INV_SEL_S 6
-#define GPIO_GPIO_FUNC255_IN_SEL 0x0000003F
-#define GPIO_GPIO_FUNC255_IN_SEL_S 0
-
-#define GPIO_FUNC0_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0530)
-#define GPIO_GPIO_FUNC0_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC0_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC0_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC0_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC0_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC0_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC0_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC0_OUT_SEL_S 0
-
-#define GPIO_FUNC1_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0534)
-#define GPIO_GPIO_FUNC1_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC1_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC1_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC1_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC1_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC1_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC1_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC1_OUT_SEL_S 0
-
-#define GPIO_FUNC2_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0538)
-#define GPIO_GPIO_FUNC2_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC2_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC2_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC2_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC2_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC2_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC2_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC2_OUT_SEL_S 0
-
-#define GPIO_FUNC3_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x053c)
-#define GPIO_GPIO_FUNC3_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC3_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC3_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC3_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC3_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC3_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC3_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC3_OUT_SEL_S 0
-
-#define GPIO_FUNC4_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0540)
-#define GPIO_GPIO_FUNC4_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC4_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC4_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC4_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC4_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC4_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC4_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC4_OUT_SEL_S 0
-
-#define GPIO_FUNC5_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0544)
-#define GPIO_GPIO_FUNC5_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC5_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC5_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC5_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC5_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC5_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC5_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC5_OUT_SEL_S 0
-
-#define GPIO_FUNC6_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0548)
-#define GPIO_GPIO_FUNC6_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC6_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC6_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC6_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC6_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC6_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC6_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC6_OUT_SEL_S 0
-
-#define GPIO_FUNC7_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x054c)
-#define GPIO_GPIO_FUNC7_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC7_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC7_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC7_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC7_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC7_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC7_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC7_OUT_SEL_S 0
-
-#define GPIO_FUNC8_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0550)
-#define GPIO_GPIO_FUNC8_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC8_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC8_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC8_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC8_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC8_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC8_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC8_OUT_SEL_S 0
-
-#define GPIO_FUNC9_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0554)
-#define GPIO_GPIO_FUNC9_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC9_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC9_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC9_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC9_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC9_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC9_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC9_OUT_SEL_S 0
-
-#define GPIO_FUNC10_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0558)
-#define GPIO_GPIO_FUNC10_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC10_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC10_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC10_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC10_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC10_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC10_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC10_OUT_SEL_S 0
-
-#define GPIO_FUNC11_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x055c)
-#define GPIO_GPIO_FUNC11_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC11_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC11_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC11_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC11_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC11_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC11_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC11_OUT_SEL_S 0
-
-#define GPIO_FUNC12_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0560)
-#define GPIO_GPIO_FUNC12_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC12_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC12_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC12_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC12_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC12_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC12_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC12_OUT_SEL_S 0
-
-#define GPIO_FUNC13_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0564)
-#define GPIO_GPIO_FUNC13_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC13_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC13_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC13_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC13_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC13_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC13_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC13_OUT_SEL_S 0
-
-#define GPIO_FUNC14_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0568)
-#define GPIO_GPIO_FUNC14_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC14_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC14_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC14_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC14_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC14_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC14_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC14_OUT_SEL_S 0
-
-#define GPIO_FUNC15_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x056c)
-#define GPIO_GPIO_FUNC15_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC15_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC15_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC15_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC15_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC15_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC15_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC15_OUT_SEL_S 0
-
-#define GPIO_FUNC16_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0570)
-#define GPIO_GPIO_FUNC16_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC16_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC16_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC16_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC16_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC16_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC16_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC16_OUT_SEL_S 0
-
-#define GPIO_FUNC17_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0574)
-#define GPIO_GPIO_FUNC17_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC17_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC17_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC17_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC17_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC17_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC17_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC17_OUT_SEL_S 0
-
-#define GPIO_FUNC18_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0578)
-#define GPIO_GPIO_FUNC18_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC18_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC18_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC18_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC18_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC18_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC18_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC18_OUT_SEL_S 0
-
-#define GPIO_FUNC19_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x057c)
-#define GPIO_GPIO_FUNC19_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC19_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC19_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC19_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC19_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC19_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC19_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC19_OUT_SEL_S 0
-
-#define GPIO_FUNC20_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0580)
-#define GPIO_GPIO_FUNC20_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC20_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC20_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC20_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC20_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC20_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC20_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC20_OUT_SEL_S 0
-
-#define GPIO_FUNC21_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0584)
-#define GPIO_GPIO_FUNC21_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC21_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC21_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC21_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC21_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC21_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC21_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC21_OUT_SEL_S 0
-
-#define GPIO_FUNC22_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0588)
-#define GPIO_GPIO_FUNC22_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC22_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC22_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC22_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC22_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC22_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC22_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC22_OUT_SEL_S 0
-
-#define GPIO_FUNC23_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x058c)
-#define GPIO_GPIO_FUNC23_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC23_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC23_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC23_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC23_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC23_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC23_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC23_OUT_SEL_S 0
-
-#define GPIO_FUNC24_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0590)
-#define GPIO_GPIO_FUNC24_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC24_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC24_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC24_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC24_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC24_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC24_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC24_OUT_SEL_S 0
-
-#define GPIO_FUNC25_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0594)
-#define GPIO_GPIO_FUNC25_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC25_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC25_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC25_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC25_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC25_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC25_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC25_OUT_SEL_S 0
-
-#define GPIO_FUNC26_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0598)
-#define GPIO_GPIO_FUNC26_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC26_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC26_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC26_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC26_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC26_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC26_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC26_OUT_SEL_S 0
-
-#define GPIO_FUNC27_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x059c)
-#define GPIO_GPIO_FUNC27_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC27_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC27_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC27_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC27_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC27_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC27_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC27_OUT_SEL_S 0
-
-#define GPIO_FUNC28_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05a0)
-#define GPIO_GPIO_FUNC28_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC28_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC28_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC28_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC28_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC28_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC28_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC28_OUT_SEL_S 0
-
-#define GPIO_FUNC29_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05a4)
-#define GPIO_GPIO_FUNC29_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC29_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC29_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC29_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC29_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC29_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC29_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC29_OUT_SEL_S 0
-
-#define GPIO_FUNC30_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05a8)
-#define GPIO_GPIO_FUNC30_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC30_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC30_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC30_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC30_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC30_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC30_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC30_OUT_SEL_S 0
-
-#define GPIO_FUNC31_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05ac)
-#define GPIO_GPIO_FUNC31_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC31_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC31_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC31_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC31_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC31_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC31_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC31_OUT_SEL_S 0
-
-#define GPIO_FUNC32_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05b0)
-#define GPIO_GPIO_FUNC32_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC32_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC32_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC32_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC32_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC32_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC32_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC32_OUT_SEL_S 0
-
-#define GPIO_FUNC33_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05b4)
-#define GPIO_GPIO_FUNC33_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC33_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC33_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC33_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC33_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC33_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC33_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC33_OUT_SEL_S 0
-
-#define GPIO_FUNC34_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05b8)
-#define GPIO_GPIO_FUNC34_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC34_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC34_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC34_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC34_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC34_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC34_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC34_OUT_SEL_S 0
-
-#define GPIO_FUNC35_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05bc)
-#define GPIO_GPIO_FUNC35_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC35_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC35_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC35_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC35_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC35_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC35_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC35_OUT_SEL_S 0
-
-#define GPIO_FUNC36_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05c0)
-#define GPIO_GPIO_FUNC36_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC36_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC36_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC36_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC36_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC36_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC36_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC36_OUT_SEL_S 0
-
-#define GPIO_FUNC37_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05c4)
-#define GPIO_GPIO_FUNC37_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC37_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC37_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC37_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC37_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC37_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC37_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC37_OUT_SEL_S 0
-
-#define GPIO_FUNC38_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05c8)
-#define GPIO_GPIO_FUNC38_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC38_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC38_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC38_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC38_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC38_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC38_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC38_OUT_SEL_S 0
-
-#define GPIO_FUNC39_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05cc)
-#define GPIO_GPIO_FUNC39_OEN_INV_SEL (BIT(11))
-#define GPIO_GPIO_FUNC39_OEN_INV_SEL_S 11
-#define GPIO_GPIO_FUNC39_OEN_SEL (BIT(10))
-#define GPIO_GPIO_FUNC39_OEN_SEL_S 10
-#define GPIO_GPIO_FUNC39_OUT_INV_SEL (BIT(9))
-#define GPIO_GPIO_FUNC39_OUT_INV_SEL_S 9
-#define GPIO_GPIO_FUNC39_OUT_SEL 0x000001FF
-#define GPIO_GPIO_FUNC39_OUT_SEL_S 0
-
-#endif /* _SOC_GPIO_REG_H_ */
#define _SOC_GPIO_SD_REG_H_
#include "soc.h"
+#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
+/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD0_PRESCALE 0x000000FF
+#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
+#define GPIO_SD0_PRESCALE_V 0xFF
+#define GPIO_SD0_PRESCALE_S 8
+/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD0_IN 0x000000FF
+#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
+#define GPIO_SD0_IN_V 0xFF
+#define GPIO_SD0_IN_S 0
-#define SIGMADELTA0 (DR_REG_GPIO_SD_BASE + 0x0000)
-#define SIGMADELTA_SD0_PRESCALE 0x000000FF
-#define SIGMADELTA_SD0_PRESCALE_S 8
-#define SIGMADELTA_SD0_IN 0x000000FF
-#define SIGMADELTA_SD0_IN_S 0
-
-#define SIGMADELTA1 (DR_REG_GPIO_SD_BASE + 0x0004)
-#define SIGMADELTA_SD1_PRESCALE 0x000000FF
-#define SIGMADELTA_SD1_PRESCALE_S 8
-#define SIGMADELTA_SD1_IN 0x000000FF
-#define SIGMADELTA_SD1_IN_S 0
-
-#define SIGMADELTA2 (DR_REG_GPIO_SD_BASE + 0x0008)
-#define SIGMADELTA_SD2_PRESCALE 0x000000FF
-#define SIGMADELTA_SD2_PRESCALE_S 8
-#define SIGMADELTA_SD2_IN 0x000000FF
-#define SIGMADELTA_SD2_IN_S 0
-
-#define SIGMADELTA3 (DR_REG_GPIO_SD_BASE + 0x000c)
-#define SIGMADELTA_SD3_PRESCALE 0x000000FF
-#define SIGMADELTA_SD3_PRESCALE_S 8
-#define SIGMADELTA_SD3_IN 0x000000FF
-#define SIGMADELTA_SD3_IN_S 0
-
-#define SIGMADELTA4 (DR_REG_GPIO_SD_BASE + 0x0010)
-#define SIGMADELTA_SD4_PRESCALE 0x000000FF
-#define SIGMADELTA_SD4_PRESCALE_S 8
-#define SIGMADELTA_SD4_IN 0x000000FF
-#define SIGMADELTA_SD4_IN_S 0
-
-#define SIGMADELTA5 (DR_REG_GPIO_SD_BASE + 0x0014)
-#define SIGMADELTA_SD5_PRESCALE 0x000000FF
-#define SIGMADELTA_SD5_PRESCALE_S 8
-#define SIGMADELTA_SD5_IN 0x000000FF
-#define SIGMADELTA_SD5_IN_S 0
-
-#define SIGMADELTA6 (DR_REG_GPIO_SD_BASE + 0x0018)
-#define SIGMADELTA_SD6_PRESCALE 0x000000FF
-#define SIGMADELTA_SD6_PRESCALE_S 8
-#define SIGMADELTA_SD6_IN 0x000000FF
-#define SIGMADELTA_SD6_IN_S 0
-
-#define SIGMADELTA7 (DR_REG_GPIO_SD_BASE + 0x001c)
-#define SIGMADELTA_SD7_PRESCALE 0x000000FF
-#define SIGMADELTA_SD7_PRESCALE_S 8
-#define SIGMADELTA_SD7_IN 0x000000FF
-#define SIGMADELTA_SD7_IN_S 0
-
-#define SIGMADELTA_CG (DR_REG_GPIO_SD_BASE + 0x0020)
-#define SIGMADELTA_GPIO_SD_CLK_EN (BIT(31))
-#define SIGMADELTA_GPIO_SD_CLK_EN_S 31
-
-#define SIGMADELTA_MISC (DR_REG_GPIO_SD_BASE + 0x0024)
-#define SIGMADELTA_SPI_SWAP (BIT(31))
-#define SIGMADELTA_SPI_SWAP_S 31
-
-#define SIGMADELTA_VERSION (DR_REG_GPIO_SD_BASE + 0x0028)
-#define SIGMADELTA_GPIO_SD_DATE 0x0FFFFFFF
-#define SIGMADELTA_GPIO_SD_DATE_S 0
+#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
+/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD1_PRESCALE 0x000000FF
+#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
+#define GPIO_SD1_PRESCALE_V 0xFF
+#define GPIO_SD1_PRESCALE_S 8
+/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD1_IN 0x000000FF
+#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
+#define GPIO_SD1_IN_V 0xFF
+#define GPIO_SD1_IN_S 0
+
+#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
+/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD2_PRESCALE 0x000000FF
+#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
+#define GPIO_SD2_PRESCALE_V 0xFF
+#define GPIO_SD2_PRESCALE_S 8
+/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD2_IN 0x000000FF
+#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
+#define GPIO_SD2_IN_V 0xFF
+#define GPIO_SD2_IN_S 0
+
+#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
+/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD3_PRESCALE 0x000000FF
+#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
+#define GPIO_SD3_PRESCALE_V 0xFF
+#define GPIO_SD3_PRESCALE_S 8
+/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD3_IN 0x000000FF
+#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
+#define GPIO_SD3_IN_V 0xFF
+#define GPIO_SD3_IN_S 0
+
+#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010)
+/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD4_PRESCALE 0x000000FF
+#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
+#define GPIO_SD4_PRESCALE_V 0xFF
+#define GPIO_SD4_PRESCALE_S 8
+/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD4_IN 0x000000FF
+#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
+#define GPIO_SD4_IN_V 0xFF
+#define GPIO_SD4_IN_S 0
+
+#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014)
+/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD5_PRESCALE 0x000000FF
+#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
+#define GPIO_SD5_PRESCALE_V 0xFF
+#define GPIO_SD5_PRESCALE_S 8
+/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD5_IN 0x000000FF
+#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
+#define GPIO_SD5_IN_V 0xFF
+#define GPIO_SD5_IN_S 0
+
+#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018)
+/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD6_PRESCALE 0x000000FF
+#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
+#define GPIO_SD6_PRESCALE_V 0xFF
+#define GPIO_SD6_PRESCALE_S 8
+/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD6_IN 0x000000FF
+#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
+#define GPIO_SD6_IN_V 0xFF
+#define GPIO_SD6_IN_S 0
+
+#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c)
+/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD7_PRESCALE 0x000000FF
+#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
+#define GPIO_SD7_PRESCALE_V 0xFF
+#define GPIO_SD7_PRESCALE_S 8
+/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD7_IN 0x000000FF
+#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
+#define GPIO_SD7_IN_V 0xFF
+#define GPIO_SD7_IN_S 0
+
+#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
+/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SD_CLK_EN (BIT(31))
+#define GPIO_SD_CLK_EN_M (BIT(31))
+#define GPIO_SD_CLK_EN_V 0x1
+#define GPIO_SD_CLK_EN_S 31
+
+#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
+/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SPI_SWAP (BIT(31))
+#define GPIO_SPI_SWAP_M (BIT(31))
+#define GPIO_SPI_SWAP_V 0x1
+#define GPIO_SPI_SWAP_S 31
+
+#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
+/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1506190 ; */
+/*description: */
+#define GPIO_SD_DATE 0x0FFFFFFF
+#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
+#define GPIO_SD_DATE_V 0xFFFFFFF
+#define GPIO_SD_DATE_S 0
#define SIGMADELTA_GPIO_SD_DATE_VERSION 0x1506190
-#endif /* _SOC_GPIO_SD_REG_H_ */
+
+
+
+#endif /*_SOC_GPIO_SD_REG_H_ */
+
+
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef _SOC_I2C_REG_H_\r
+#define _SOC_I2C_REG_H_\r
+\r
+\r
+#include "soc.h"\r
+\r
+#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )\r
+\r
+#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000)\r
+/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This register is used to configure the low level width of SCL clock.*/\r
+#define I2C_SCL_LOW_PERIOD 0x00003FFF\r
+#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))\r
+#define I2C_SCL_LOW_PERIOD_V 0x3FFF\r
+#define I2C_SCL_LOW_PERIOD_S 0\r
+\r
+#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004)\r
+/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: This is the clock gating control bit for reading or writing registers.*/\r
+#define I2C_CLK_EN (BIT(8))\r
+#define I2C_CLK_EN_M (BIT(8))\r
+#define I2C_CLK_EN_V 0x1\r
+#define I2C_CLK_EN_S 8\r
+/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */\r
+/*description: This bit is used to control the storage mode for received datas.\r
+ 1: receive data from most significant bit 0: receive data from least significant bit*/\r
+#define I2C_RX_LSB_FIRST (BIT(7))\r
+#define I2C_RX_LSB_FIRST_M (BIT(7))\r
+#define I2C_RX_LSB_FIRST_V 0x1\r
+#define I2C_RX_LSB_FIRST_S 7\r
+/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the sending mode for data need to\r
+ be send. 1: receive data from most significant bit 0: receive data from least significant bit*/\r
+#define I2C_TX_LSB_FIRST (BIT(6))\r
+#define I2C_TX_LSB_FIRST_M (BIT(6))\r
+#define I2C_TX_LSB_FIRST_V 0x1\r
+#define I2C_TX_LSB_FIRST_S 6\r
+/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to start sending data in txfifo.*/\r
+#define I2C_TRANS_START (BIT(5))\r
+#define I2C_TRANS_START_M (BIT(5))\r
+#define I2C_TRANS_START_V 0x1\r
+#define I2C_TRANS_START_S 5\r
+/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to configure the module as i2c master clear this\r
+ bit to configure the module as i2c slave.*/\r
+#define I2C_MS_MODE (BIT(4))\r
+#define I2C_MS_MODE_M (BIT(4))\r
+#define I2C_MS_MODE_V 0x1\r
+#define I2C_MS_MODE_S 4\r
+/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to sample data in SCL low level. clear this bit\r
+ to sample data in SCL high level.*/\r
+#define I2C_SAMPLE_SCL_LEVEL (BIT(2))\r
+#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2))\r
+#define I2C_SAMPLE_SCL_LEVEL_V 0x1\r
+#define I2C_SAMPLE_SCL_LEVEL_S 2\r
+/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */\r
+/*description: 1: normally ouput scl clock 0: exchange the function of scl_o\r
+ and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/\r
+#define I2C_SCL_FORCE_OUT (BIT(1))\r
+#define I2C_SCL_FORCE_OUT_M (BIT(1))\r
+#define I2C_SCL_FORCE_OUT_V 0x1\r
+#define I2C_SCL_FORCE_OUT_S 1\r
+/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */\r
+/*description: 1: normally ouput sda data 0: exchange the function of sda_o\r
+ and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/\r
+#define I2C_SDA_FORCE_OUT (BIT(0))\r
+#define I2C_SDA_FORCE_OUT_M (BIT(0))\r
+#define I2C_SDA_FORCE_OUT_V 0x1\r
+#define I2C_SDA_FORCE_OUT_S 0\r
+\r
+#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008)\r
+/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */\r
+/*description: This register stores the value of state machine to produce SCL.\r
+ 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/\r
+#define I2C_SCL_STATE_LAST 0x00000007\r
+#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))\r
+#define I2C_SCL_STATE_LAST_V 0x7\r
+#define I2C_SCL_STATE_LAST_S 28\r
+/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */\r
+/*description: This register stores the value of state machine for i2c module.\r
+ 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/\r
+#define I2C_SCL_MAIN_STATE_LAST 0x00000007\r
+#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))\r
+#define I2C_SCL_MAIN_STATE_LAST_V 0x7\r
+#define I2C_SCL_MAIN_STATE_LAST_S 24\r
+/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */\r
+/*description: This register stores the amount of received data in ram.*/\r
+#define I2C_TXFIFO_CNT 0x0000003F\r
+#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))\r
+#define I2C_TXFIFO_CNT_V 0x3F\r
+#define I2C_TXFIFO_CNT_S 18\r
+/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */\r
+/*description: This register represent the amount of data need to send.*/\r
+#define I2C_RXFIFO_CNT 0x0000003F\r
+#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))\r
+#define I2C_RXFIFO_CNT_V 0x3F\r
+#define I2C_RXFIFO_CNT_S 8\r
+/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This register changes to high level when one byte is transferred.*/\r
+#define I2C_BYTE_TRANS (BIT(6))\r
+#define I2C_BYTE_TRANS_M (BIT(6))\r
+#define I2C_BYTE_TRANS_V 0x1\r
+#define I2C_BYTE_TRANS_S 6\r
+/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: when configured as i2c slave and the address send by master\r
+ is equal to slave's address then this bit will be high level.*/\r
+#define I2C_SLAVE_ADDRESSED (BIT(5))\r
+#define I2C_SLAVE_ADDRESSED_M (BIT(5))\r
+#define I2C_SLAVE_ADDRESSED_V 0x1\r
+#define I2C_SLAVE_ADDRESSED_S 5\r
+/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/\r
+#define I2C_BUS_BUSY (BIT(4))\r
+#define I2C_BUS_BUSY_M (BIT(4))\r
+#define I2C_BUS_BUSY_V 0x1\r
+#define I2C_BUS_BUSY_S 4\r
+/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: when I2C lost control of SDA line this register changes to high level.*/\r
+#define I2C_ARB_LOST (BIT(3))\r
+#define I2C_ARB_LOST_M (BIT(3))\r
+#define I2C_ARB_LOST_V 0x1\r
+#define I2C_ARB_LOST_S 3\r
+/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: when I2C takes more than time_out_reg clocks to receive a data\r
+ then this register changes to high level.*/\r
+#define I2C_TIME_OUT (BIT(2))\r
+#define I2C_TIME_OUT_M (BIT(2))\r
+#define I2C_TIME_OUT_V 0x1\r
+#define I2C_TIME_OUT_S 2\r
+/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: when in slave mode 1: master read slave 0: master write slave.*/\r
+#define I2C_SLAVE_RW (BIT(1))\r
+#define I2C_SLAVE_RW_M (BIT(1))\r
+#define I2C_SLAVE_RW_V 0x1\r
+#define I2C_SLAVE_RW_S 1\r
+/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This register stores the value of ACK bit.*/\r
+#define I2C_ACK_REC (BIT(0))\r
+#define I2C_ACK_REC_M (BIT(0))\r
+#define I2C_ACK_REC_V 0x1\r
+#define I2C_ACK_REC_S 0\r
+\r
+#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c)\r
+/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: This register is used to configure the max clock number of receiving a data.*/\r
+#define I2C_TIME_OUT_REG 0x000FFFFF\r
+#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))\r
+#define I2C_TIME_OUT_REG_V 0xFFFFF\r
+#define I2C_TIME_OUT_REG_S 0\r
+\r
+#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010)\r
+/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: This register is used to enable slave 10bit address mode.*/\r
+#define I2C_ADDR_10BIT_EN (BIT(31))\r
+#define I2C_ADDR_10BIT_EN_M (BIT(31))\r
+#define I2C_ADDR_10BIT_EN_V 0x1\r
+#define I2C_ADDR_10BIT_EN_S 31\r
+/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */\r
+/*description: when configured as i2c slave this register is used to configure\r
+ slave's address.*/\r
+#define I2C_SLAVE_ADDR 0x00007FFF\r
+#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))\r
+#define I2C_SLAVE_ADDR_V 0x7FFF\r
+#define I2C_SLAVE_ADDR_S 0\r
+\r
+#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014)\r
+/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */\r
+/*description: This is the offset address of the last sending data as described\r
+ in nonfifo_tx_thres register.*/\r
+#define I2C_TXFIFO_END_ADDR 0x0000001F\r
+#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))\r
+#define I2C_TXFIFO_END_ADDR_V 0x1F\r
+#define I2C_TXFIFO_END_ADDR_S 15\r
+/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */\r
+/*description: This is the offset address of the first sending data as described\r
+ in nonfifo_tx_thres register.*/\r
+#define I2C_TXFIFO_START_ADDR 0x0000001F\r
+#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S))\r
+#define I2C_TXFIFO_START_ADDR_V 0x1F\r
+#define I2C_TXFIFO_START_ADDR_S 10\r
+/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */\r
+/*description: This is the offset address of the first receiving data as described\r
+ in nonfifo_rx_thres_register.*/\r
+#define I2C_RXFIFO_END_ADDR 0x0000001F\r
+#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S))\r
+#define I2C_RXFIFO_END_ADDR_V 0x1F\r
+#define I2C_RXFIFO_END_ADDR_S 5\r
+/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */\r
+/*description: This is the offset address of the last receiving data as described\r
+ in nonfifo_rx_thres_register.*/\r
+#define I2C_RXFIFO_START_ADDR 0x0000001F\r
+#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))\r
+#define I2C_RXFIFO_START_ADDR_V 0x1F\r
+#define I2C_RXFIFO_START_ADDR_S 0\r
+\r
+#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018)\r
+/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */\r
+/*description: when I2C sends more than nonfifo_tx_thres data it will produce\r
+ tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/\r
+#define I2C_NONFIFO_TX_THRES 0x0000003F\r
+#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S))\r
+#define I2C_NONFIFO_TX_THRES_V 0x3F\r
+#define I2C_NONFIFO_TX_THRES_S 20\r
+/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */\r
+/*description: when I2C receives more than nonfifo_rx_thres data it will produce\r
+ rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/\r
+#define I2C_NONFIFO_RX_THRES 0x0000003F\r
+#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S))\r
+#define I2C_NONFIFO_RX_THRES_V 0x3F\r
+#define I2C_NONFIFO_RX_THRES_S 14\r
+/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset tx fifo when using apb fifo access.*/\r
+#define I2C_TX_FIFO_RST (BIT(13))\r
+#define I2C_TX_FIFO_RST_M (BIT(13))\r
+#define I2C_TX_FIFO_RST_V 0x1\r
+#define I2C_TX_FIFO_RST_S 13\r
+/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset rx fifo when using apb fifo access.*/\r
+#define I2C_RX_FIFO_RST (BIT(12))\r
+#define I2C_RX_FIFO_RST_M (BIT(12))\r
+#define I2C_RX_FIFO_RST_V 0x1\r
+#define I2C_RX_FIFO_RST_S 12\r
+/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: When this bit is set to 1 then the byte after address represent\r
+ the offset address of I2C Slave's ram.*/\r
+#define I2C_FIFO_ADDR_CFG_EN (BIT(11))\r
+#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11))\r
+#define I2C_FIFO_ADDR_CFG_EN_V 0x1\r
+#define I2C_FIFO_ADDR_CFG_EN_S 11\r
+/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: Set this bit to enble apb nonfifo access.*/\r
+#define I2C_NONFIFO_EN (BIT(10))\r
+#define I2C_NONFIFO_EN_M (BIT(10))\r
+#define I2C_NONFIFO_EN_V 0x1\r
+#define I2C_NONFIFO_EN_S 10\r
+/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */\r
+/*description: Config txfifo empty threhd value when using apb fifo access*/\r
+#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F\r
+#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S))\r
+#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F\r
+#define I2C_TXFIFO_EMPTY_THRHD_S 5\r
+/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */\r
+/*description: */\r
+#define I2C_RXFIFO_FULL_THRHD 0x0000001F\r
+#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S))\r
+#define I2C_RXFIFO_FULL_THRHD_V 0x1F\r
+#define I2C_RXFIFO_FULL_THRHD_S 0\r
+\r
+#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c)\r
+/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */\r
+/*description: The register represent the byte data read from rxfifo when use apb fifo access*/\r
+#define I2C_FIFO_RDATA 0x000000FF\r
+#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))\r
+#define I2C_FIFO_RDATA_V 0xFF\r
+#define I2C_FIFO_RDATA_S 0\r
+\r
+#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020)\r
+/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when\r
+ I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/\r
+#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12))\r
+#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12))\r
+#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1\r
+#define I2C_TX_SEND_EMPTY_INT_RAW_S 12\r
+/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when\r
+ I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/\r
+#define I2C_RX_REC_FULL_INT_RAW (BIT(11))\r
+#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11))\r
+#define I2C_RX_REC_FULL_INT_RAW_V 0x1\r
+#define I2C_RX_REC_FULL_INT_RAW_S 11\r
+/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for ack_err_int interrupt. when\r
+ I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/\r
+#define I2C_ACK_ERR_INT_RAW (BIT(10))\r
+#define I2C_ACK_ERR_INT_RAW_M (BIT(10))\r
+#define I2C_ACK_ERR_INT_RAW_V 0x1\r
+#define I2C_ACK_ERR_INT_RAW_S 10\r
+/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for trans_start_int interrupt. when\r
+ I2C sends the START bit it will produce trans_start_int interrupt.*/\r
+#define I2C_TRANS_START_INT_RAW (BIT(9))\r
+#define I2C_TRANS_START_INT_RAW_M (BIT(9))\r
+#define I2C_TRANS_START_INT_RAW_V 0x1\r
+#define I2C_TRANS_START_INT_RAW_S 9\r
+/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for time_out_int interrupt. when\r
+ I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/\r
+#define I2C_TIME_OUT_INT_RAW (BIT(8))\r
+#define I2C_TIME_OUT_INT_RAW_M (BIT(8))\r
+#define I2C_TIME_OUT_INT_RAW_V 0x1\r
+#define I2C_TIME_OUT_INT_RAW_S 8\r
+/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for trans_complete_int interrupt.\r
+ when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/\r
+#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7))\r
+#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7))\r
+#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1\r
+#define I2C_TRANS_COMPLETE_INT_RAW_S 7\r
+/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for master_tra_comp_int interrupt.\r
+ when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/\r
+#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6))\r
+#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6))\r
+#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1\r
+#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6\r
+/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when\r
+ I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/\r
+#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5))\r
+#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5))\r
+#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1\r
+#define I2C_ARBITRATION_LOST_INT_RAW_S 5\r
+/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for slave_tran_comp_int interrupt.\r
+ when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/\r
+#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4))\r
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4))\r
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1\r
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4\r
+/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for end_detect_int interrupt. when\r
+ I2C deals with the END command it will produce end_detect_int interrupt.*/\r
+#define I2C_END_DETECT_INT_RAW (BIT(3))\r
+#define I2C_END_DETECT_INT_RAW_M (BIT(3))\r
+#define I2C_END_DETECT_INT_RAW_V 0x1\r
+#define I2C_END_DETECT_INT_RAW_S 3\r
+/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for receiving data overflow when\r
+ use apb fifo access.*/\r
+#define I2C_RXFIFO_OVF_INT_RAW (BIT(2))\r
+#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2))\r
+#define I2C_RXFIFO_OVF_INT_RAW_V 0x1\r
+#define I2C_RXFIFO_OVF_INT_RAW_S 2\r
+/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/\r
+#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1))\r
+#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1))\r
+#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1\r
+#define I2C_TXFIFO_EMPTY_INT_RAW_S 1\r
+/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/\r
+#define I2C_RXFIFO_FULL_INT_RAW (BIT(0))\r
+#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0))\r
+#define I2C_RXFIFO_FULL_INT_RAW_V 0x1\r
+#define I2C_RXFIFO_FULL_INT_RAW_S 0\r
+\r
+#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024)\r
+/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the tx_send_empty_int interrupt.*/\r
+#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12))\r
+#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12))\r
+#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1\r
+#define I2C_TX_SEND_EMPTY_INT_CLR_S 12\r
+/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rx_rec_full_int interrupt.*/\r
+#define I2C_RX_REC_FULL_INT_CLR (BIT(11))\r
+#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11))\r
+#define I2C_RX_REC_FULL_INT_CLR_V 0x1\r
+#define I2C_RX_REC_FULL_INT_CLR_S 11\r
+/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the ack_err_int interrupt.*/\r
+#define I2C_ACK_ERR_INT_CLR (BIT(10))\r
+#define I2C_ACK_ERR_INT_CLR_M (BIT(10))\r
+#define I2C_ACK_ERR_INT_CLR_V 0x1\r
+#define I2C_ACK_ERR_INT_CLR_S 10\r
+/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the trans_start_int interrupt.*/\r
+#define I2C_TRANS_START_INT_CLR (BIT(9))\r
+#define I2C_TRANS_START_INT_CLR_M (BIT(9))\r
+#define I2C_TRANS_START_INT_CLR_V 0x1\r
+#define I2C_TRANS_START_INT_CLR_S 9\r
+/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the time_out_int interrupt.*/\r
+#define I2C_TIME_OUT_INT_CLR (BIT(8))\r
+#define I2C_TIME_OUT_INT_CLR_M (BIT(8))\r
+#define I2C_TIME_OUT_INT_CLR_V 0x1\r
+#define I2C_TIME_OUT_INT_CLR_S 8\r
+/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the trans_complete_int interrupt.*/\r
+#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7))\r
+#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7))\r
+#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1\r
+#define I2C_TRANS_COMPLETE_INT_CLR_S 7\r
+/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the master_tran_comp interrupt.*/\r
+#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6))\r
+#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6))\r
+#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1\r
+#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6\r
+/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the arbitration_lost_int interrupt.*/\r
+#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))\r
+#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))\r
+#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1\r
+#define I2C_ARBITRATION_LOST_INT_CLR_S 5\r
+/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/\r
+#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4))\r
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4))\r
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1\r
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4\r
+/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the end_detect_int interrupt.*/\r
+#define I2C_END_DETECT_INT_CLR (BIT(3))\r
+#define I2C_END_DETECT_INT_CLR_M (BIT(3))\r
+#define I2C_END_DETECT_INT_CLR_V 0x1\r
+#define I2C_END_DETECT_INT_CLR_S 3\r
+/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/\r
+#define I2C_RXFIFO_OVF_INT_CLR (BIT(2))\r
+#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2))\r
+#define I2C_RXFIFO_OVF_INT_CLR_V 0x1\r
+#define I2C_RXFIFO_OVF_INT_CLR_S 2\r
+/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the txfifo_empty_int interrupt.*/\r
+#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1))\r
+#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1))\r
+#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1\r
+#define I2C_TXFIFO_EMPTY_INT_CLR_S 1\r
+/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rxfifo_full_int interrupt.*/\r
+#define I2C_RXFIFO_FULL_INT_CLR (BIT(0))\r
+#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0))\r
+#define I2C_RXFIFO_FULL_INT_CLR_V 0x1\r
+#define I2C_RXFIFO_FULL_INT_CLR_S 0\r
+\r
+#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028)\r
+/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: The enable bit for tx_send_empty_int interrupt.*/\r
+#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12))\r
+#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12))\r
+#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1\r
+#define I2C_TX_SEND_EMPTY_INT_ENA_S 12\r
+/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: The enable bit for rx_rec_full_int interrupt.*/\r
+#define I2C_RX_REC_FULL_INT_ENA (BIT(11))\r
+#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11))\r
+#define I2C_RX_REC_FULL_INT_ENA_V 0x1\r
+#define I2C_RX_REC_FULL_INT_ENA_S 11\r
+/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: The enable bit for ack_err_int interrupt.*/\r
+#define I2C_ACK_ERR_INT_ENA (BIT(10))\r
+#define I2C_ACK_ERR_INT_ENA_M (BIT(10))\r
+#define I2C_ACK_ERR_INT_ENA_V 0x1\r
+#define I2C_ACK_ERR_INT_ENA_S 10\r
+/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: The enable bit for trans_start_int interrupt.*/\r
+#define I2C_TRANS_START_INT_ENA (BIT(9))\r
+#define I2C_TRANS_START_INT_ENA_M (BIT(9))\r
+#define I2C_TRANS_START_INT_ENA_V 0x1\r
+#define I2C_TRANS_START_INT_ENA_S 9\r
+/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The enable bit for time_out_int interrupt.*/\r
+#define I2C_TIME_OUT_INT_ENA (BIT(8))\r
+#define I2C_TIME_OUT_INT_ENA_M (BIT(8))\r
+#define I2C_TIME_OUT_INT_ENA_V 0x1\r
+#define I2C_TIME_OUT_INT_ENA_S 8\r
+/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The enable bit for trans_complete_int interrupt.*/\r
+#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7))\r
+#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7))\r
+#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1\r
+#define I2C_TRANS_COMPLETE_INT_ENA_S 7\r
+/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The enable bit for master_tran_comp_int interrupt.*/\r
+#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6))\r
+#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6))\r
+#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1\r
+#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6\r
+/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The enable bit for arbitration_lost_int interrupt.*/\r
+#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5))\r
+#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5))\r
+#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1\r
+#define I2C_ARBITRATION_LOST_INT_ENA_S 5\r
+/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The enable bit for slave_tran_comp_int interrupt.*/\r
+#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4))\r
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4))\r
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1\r
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4\r
+/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The enable bit for end_detect_int interrupt.*/\r
+#define I2C_END_DETECT_INT_ENA (BIT(3))\r
+#define I2C_END_DETECT_INT_ENA_M (BIT(3))\r
+#define I2C_END_DETECT_INT_ENA_V 0x1\r
+#define I2C_END_DETECT_INT_ENA_S 3\r
+/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The enable bit for rxfifo_ovf_int interrupt.*/\r
+#define I2C_RXFIFO_OVF_INT_ENA (BIT(2))\r
+#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2))\r
+#define I2C_RXFIFO_OVF_INT_ENA_V 0x1\r
+#define I2C_RXFIFO_OVF_INT_ENA_S 2\r
+/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The enable bit for txfifo_empty_int interrupt.*/\r
+#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1))\r
+#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1))\r
+#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1\r
+#define I2C_TXFIFO_EMPTY_INT_ENA_S 1\r
+/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The enable bit for rxfifo_full_int interrupt.*/\r
+#define I2C_RXFIFO_FULL_INT_ENA (BIT(0))\r
+#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0))\r
+#define I2C_RXFIFO_FULL_INT_ENA_V 0x1\r
+#define I2C_RXFIFO_FULL_INT_ENA_S 0\r
+\r
+#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c)\r
+/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for tx_send_empty_int interrupt.*/\r
+#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12))\r
+#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12))\r
+#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1\r
+#define I2C_TX_SEND_EMPTY_INT_ST_S 12\r
+/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for rx_rec_full_int interrupt.*/\r
+#define I2C_RX_REC_FULL_INT_ST (BIT(11))\r
+#define I2C_RX_REC_FULL_INT_ST_M (BIT(11))\r
+#define I2C_RX_REC_FULL_INT_ST_V 0x1\r
+#define I2C_RX_REC_FULL_INT_ST_S 11\r
+/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for ack_err_int interrupt.*/\r
+#define I2C_ACK_ERR_INT_ST (BIT(10))\r
+#define I2C_ACK_ERR_INT_ST_M (BIT(10))\r
+#define I2C_ACK_ERR_INT_ST_V 0x1\r
+#define I2C_ACK_ERR_INT_ST_S 10\r
+/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for trans_start_int interrupt.*/\r
+#define I2C_TRANS_START_INT_ST (BIT(9))\r
+#define I2C_TRANS_START_INT_ST_M (BIT(9))\r
+#define I2C_TRANS_START_INT_ST_V 0x1\r
+#define I2C_TRANS_START_INT_ST_S 9\r
+/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for time_out_int interrupt.*/\r
+#define I2C_TIME_OUT_INT_ST (BIT(8))\r
+#define I2C_TIME_OUT_INT_ST_M (BIT(8))\r
+#define I2C_TIME_OUT_INT_ST_V 0x1\r
+#define I2C_TIME_OUT_INT_ST_S 8\r
+/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for trans_complete_int interrupt.*/\r
+#define I2C_TRANS_COMPLETE_INT_ST (BIT(7))\r
+#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7))\r
+#define I2C_TRANS_COMPLETE_INT_ST_V 0x1\r
+#define I2C_TRANS_COMPLETE_INT_ST_S 7\r
+/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for master_tran_comp_int interrupt.*/\r
+#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6))\r
+#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6))\r
+#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1\r
+#define I2C_MASTER_TRAN_COMP_INT_ST_S 6\r
+/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for arbitration_lost_int interrupt.*/\r
+#define I2C_ARBITRATION_LOST_INT_ST (BIT(5))\r
+#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5))\r
+#define I2C_ARBITRATION_LOST_INT_ST_V 0x1\r
+#define I2C_ARBITRATION_LOST_INT_ST_S 5\r
+/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/\r
+#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4))\r
+#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4))\r
+#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1\r
+#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4\r
+/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for end_detect_int interrupt.*/\r
+#define I2C_END_DETECT_INT_ST (BIT(3))\r
+#define I2C_END_DETECT_INT_ST_M (BIT(3))\r
+#define I2C_END_DETECT_INT_ST_V 0x1\r
+#define I2C_END_DETECT_INT_ST_S 3\r
+/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/\r
+#define I2C_RXFIFO_OVF_INT_ST (BIT(2))\r
+#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2))\r
+#define I2C_RXFIFO_OVF_INT_ST_V 0x1\r
+#define I2C_RXFIFO_OVF_INT_ST_S 2\r
+/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for txfifo_empty_int interrupt.*/\r
+#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1))\r
+#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1))\r
+#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1\r
+#define I2C_TXFIFO_EMPTY_INT_ST_S 1\r
+/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The masked interrupt status for rxfifo_full_int interrupt.*/\r
+#define I2C_RXFIFO_FULL_INT_ST (BIT(0))\r
+#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0))\r
+#define I2C_RXFIFO_FULL_INT_ST_V 0x1\r
+#define I2C_RXFIFO_FULL_INT_ST_S 0\r
+\r
+#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030)\r
+/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */\r
+/*description: This register is used to configure the clock num I2C used to\r
+ hold the data after the negedge of SCL.*/\r
+#define I2C_SDA_HOLD_TIME 0x000003FF\r
+#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))\r
+#define I2C_SDA_HOLD_TIME_V 0x3FF\r
+#define I2C_SDA_HOLD_TIME_S 0\r
+\r
+#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034)\r
+/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */\r
+/*description: This register is used to configure the clock num I2C used to\r
+ sample data on SDA after the posedge of SCL*/\r
+#define I2C_SDA_SAMPLE_TIME 0x000003FF\r
+#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))\r
+#define I2C_SDA_SAMPLE_TIME_V 0x3FF\r
+#define I2C_SDA_SAMPLE_TIME_S 0\r
+\r
+#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038)\r
+/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This register is used to configure the clock num during SCL is low level.*/\r
+#define I2C_SCL_HIGH_PERIOD 0x00003FFF\r
+#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))\r
+#define I2C_SCL_HIGH_PERIOD_V 0x3FFF\r
+#define I2C_SCL_HIGH_PERIOD_S 0\r
+\r
+#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040)\r
+/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */\r
+/*description: This register is used to configure the clock num between the\r
+ negedge of SDA and negedge of SCL for start mark.*/\r
+#define I2C_SCL_START_HOLD_TIME 0x000003FF\r
+#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))\r
+#define I2C_SCL_START_HOLD_TIME_V 0x3FF\r
+#define I2C_SCL_START_HOLD_TIME_S 0\r
+\r
+#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044)\r
+/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */\r
+/*description: This register is used to configure the clock num between the\r
+ posedge of SCL and the negedge of SDA for restart mark.*/\r
+#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF\r
+#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))\r
+#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF\r
+#define I2C_SCL_RSTART_SETUP_TIME_S 0\r
+\r
+#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048)\r
+/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This register is used to configure the clock num after the STOP bit's posedge.*/\r
+#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF\r
+#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))\r
+#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF\r
+#define I2C_SCL_STOP_HOLD_TIME_S 0\r
+\r
+#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C)\r
+/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */\r
+/*description: This register is used to configure the clock num between the\r
+ posedge of SCL and the posedge of SDA.*/\r
+#define I2C_SCL_STOP_SETUP_TIME 0x000003FF\r
+#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))\r
+#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF\r
+#define I2C_SCL_STOP_SETUP_TIME_S 0\r
+\r
+#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050)\r
+/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */\r
+/*description: This is the filter enable bit for SCL.*/\r
+#define I2C_SCL_FILTER_EN (BIT(3))\r
+#define I2C_SCL_FILTER_EN_M (BIT(3))\r
+#define I2C_SCL_FILTER_EN_V 0x1\r
+#define I2C_SCL_FILTER_EN_S 3\r
+/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */\r
+/*description: When input SCL's pulse width is smaller than this register value\r
+ I2C ignores this pulse.*/\r
+#define I2C_SCL_FILTER_THRES 0x00000007\r
+#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))\r
+#define I2C_SCL_FILTER_THRES_V 0x7\r
+#define I2C_SCL_FILTER_THRES_S 0\r
+\r
+#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054)\r
+/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */\r
+/*description: This is the filter enable bit for SDA.*/\r
+#define I2C_SDA_FILTER_EN (BIT(3))\r
+#define I2C_SDA_FILTER_EN_M (BIT(3))\r
+#define I2C_SDA_FILTER_EN_V 0x1\r
+#define I2C_SDA_FILTER_EN_S 3\r
+/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */\r
+/*description: When input SCL's pulse width is smaller than this register value\r
+ I2C ignores this pulse.*/\r
+#define I2C_SDA_FILTER_THRES 0x00000007\r
+#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))\r
+#define I2C_SDA_FILTER_THRES_V 0x7\r
+#define I2C_SDA_FILTER_THRES_S 0\r
+\r
+#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058)\r
+/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command0 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND0_DONE (BIT(31))\r
+#define I2C_COMMAND0_DONE_M (BIT(31))\r
+#define I2C_COMMAND0_DONE_V 0x1\r
+#define I2C_COMMAND0_DONE_S 31\r
+/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command0. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND0 0x00003FFF\r
+#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))\r
+#define I2C_COMMAND0_V 0x3FFF\r
+#define I2C_COMMAND0_S 0\r
+\r
+#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C)\r
+/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command1 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND1_DONE (BIT(31))\r
+#define I2C_COMMAND1_DONE_M (BIT(31))\r
+#define I2C_COMMAND1_DONE_V 0x1\r
+#define I2C_COMMAND1_DONE_S 31\r
+/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command1. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND1 0x00003FFF\r
+#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))\r
+#define I2C_COMMAND1_V 0x3FFF\r
+#define I2C_COMMAND1_S 0\r
+\r
+#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060)\r
+/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command2 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND2_DONE (BIT(31))\r
+#define I2C_COMMAND2_DONE_M (BIT(31))\r
+#define I2C_COMMAND2_DONE_V 0x1\r
+#define I2C_COMMAND2_DONE_S 31\r
+/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command2. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND2 0x00003FFF\r
+#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))\r
+#define I2C_COMMAND2_V 0x3FFF\r
+#define I2C_COMMAND2_S 0\r
+\r
+#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064)\r
+/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command3 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND3_DONE (BIT(31))\r
+#define I2C_COMMAND3_DONE_M (BIT(31))\r
+#define I2C_COMMAND3_DONE_V 0x1\r
+#define I2C_COMMAND3_DONE_S 31\r
+/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command3. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND3 0x00003FFF\r
+#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))\r
+#define I2C_COMMAND3_V 0x3FFF\r
+#define I2C_COMMAND3_S 0\r
+\r
+#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068)\r
+/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command4 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND4_DONE (BIT(31))\r
+#define I2C_COMMAND4_DONE_M (BIT(31))\r
+#define I2C_COMMAND4_DONE_V 0x1\r
+#define I2C_COMMAND4_DONE_S 31\r
+/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command4. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND4 0x00003FFF\r
+#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))\r
+#define I2C_COMMAND4_V 0x3FFF\r
+#define I2C_COMMAND4_S 0\r
+\r
+#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C)\r
+/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command5 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND5_DONE (BIT(31))\r
+#define I2C_COMMAND5_DONE_M (BIT(31))\r
+#define I2C_COMMAND5_DONE_V 0x1\r
+#define I2C_COMMAND5_DONE_S 31\r
+/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command5. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND5 0x00003FFF\r
+#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))\r
+#define I2C_COMMAND5_V 0x3FFF\r
+#define I2C_COMMAND5_S 0\r
+\r
+#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070)\r
+/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command6 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND6_DONE (BIT(31))\r
+#define I2C_COMMAND6_DONE_M (BIT(31))\r
+#define I2C_COMMAND6_DONE_V 0x1\r
+#define I2C_COMMAND6_DONE_S 31\r
+/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command6. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND6 0x00003FFF\r
+#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))\r
+#define I2C_COMMAND6_V 0x3FFF\r
+#define I2C_COMMAND6_S 0\r
+\r
+#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074)\r
+/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command7 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND7_DONE (BIT(31))\r
+#define I2C_COMMAND7_DONE_M (BIT(31))\r
+#define I2C_COMMAND7_DONE_V 0x1\r
+#define I2C_COMMAND7_DONE_S 31\r
+/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command7. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND7 0x00003FFF\r
+#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))\r
+#define I2C_COMMAND7_V 0x3FFF\r
+#define I2C_COMMAND7_S 0\r
+\r
+#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078)\r
+/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command8 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND8_DONE (BIT(31))\r
+#define I2C_COMMAND8_DONE_M (BIT(31))\r
+#define I2C_COMMAND8_DONE_V 0x1\r
+#define I2C_COMMAND8_DONE_S 31\r
+/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command8. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND8 0x00003FFF\r
+#define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S))\r
+#define I2C_COMMAND8_V 0x3FFF\r
+#define I2C_COMMAND8_S 0\r
+\r
+#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C)\r
+/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command9 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND9_DONE (BIT(31))\r
+#define I2C_COMMAND9_DONE_M (BIT(31))\r
+#define I2C_COMMAND9_DONE_V 0x1\r
+#define I2C_COMMAND9_DONE_S 31\r
+/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command9. It consists of three part. op_code\r
+ is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND9 0x00003FFF\r
+#define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))\r
+#define I2C_COMMAND9_V 0x3FFF\r
+#define I2C_COMMAND9_S 0\r
+\r
+#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080)\r
+/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command10 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND10_DONE (BIT(31))\r
+#define I2C_COMMAND10_DONE_M (BIT(31))\r
+#define I2C_COMMAND10_DONE_V 0x1\r
+#define I2C_COMMAND10_DONE_S 31\r
+/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command10. It consists of three part.\r
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND10 0x00003FFF\r
+#define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S))\r
+#define I2C_COMMAND10_V 0x3FFF\r
+#define I2C_COMMAND10_S 0\r
+\r
+#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084)\r
+/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command11 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND11_DONE (BIT(31))\r
+#define I2C_COMMAND11_DONE_M (BIT(31))\r
+#define I2C_COMMAND11_DONE_V 0x1\r
+#define I2C_COMMAND11_DONE_S 31\r
+/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command11. It consists of three part.\r
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND11 0x00003FFF\r
+#define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S))\r
+#define I2C_COMMAND11_V 0x3FFF\r
+#define I2C_COMMAND11_S 0\r
+\r
+#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088)\r
+/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command12 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND12_DONE (BIT(31))\r
+#define I2C_COMMAND12_DONE_M (BIT(31))\r
+#define I2C_COMMAND12_DONE_V 0x1\r
+#define I2C_COMMAND12_DONE_S 31\r
+/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command12. It consists of three part.\r
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND12 0x00003FFF\r
+#define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S))\r
+#define I2C_COMMAND12_V 0x3FFF\r
+#define I2C_COMMAND12_S 0\r
+\r
+#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C)\r
+/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command13 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND13_DONE (BIT(31))\r
+#define I2C_COMMAND13_DONE_M (BIT(31))\r
+#define I2C_COMMAND13_DONE_V 0x1\r
+#define I2C_COMMAND13_DONE_S 31\r
+/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command13. It consists of three part.\r
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND13 0x00003FFF\r
+#define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))\r
+#define I2C_COMMAND13_V 0x3FFF\r
+#define I2C_COMMAND13_S 0\r
+\r
+#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090)\r
+/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command14 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND14_DONE (BIT(31))\r
+#define I2C_COMMAND14_DONE_M (BIT(31))\r
+#define I2C_COMMAND14_DONE_V 0x1\r
+#define I2C_COMMAND14_DONE_S 31\r
+/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command14. It consists of three part.\r
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND14 0x00003FFF\r
+#define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S))\r
+#define I2C_COMMAND14_V 0x3FFF\r
+#define I2C_COMMAND14_S 0\r
+\r
+#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094)\r
+/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When command15 is done in I2C Master mode this bit changes to high level.*/\r
+#define I2C_COMMAND15_DONE (BIT(31))\r
+#define I2C_COMMAND15_DONE_M (BIT(31))\r
+#define I2C_COMMAND15_DONE_V 0x1\r
+#define I2C_COMMAND15_DONE_S 31\r
+/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */\r
+/*description: This is the content of command15. It consists of three part.\r
+ op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/\r
+#define I2C_COMMAND15 0x00003FFF\r
+#define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S))\r
+#define I2C_COMMAND15_V 0x3FFF\r
+#define I2C_COMMAND15_S 0\r
+\r
+#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8)\r
+/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */\r
+/*description: */\r
+#define I2C_DATE 0xFFFFFFFF\r
+#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S))\r
+#define I2C_DATE_V 0xFFFFFFFF\r
+#define I2C_DATE_S 0\r
+\r
+#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100)\r
+\r
+\r
+\r
+\r
+#endif /*_SOC_I2C_REG_H_ */\r
+\r
+\r
#include "soc.h"
-#define I2SCONF (DR_REG_I2S_BASE + 0x0008)
-#define I2S_I2S_SIG_LOOPBACK (BIT(18))
-#define I2S_I2S_SIG_LOOPBACK_S 18
-#define I2S_RX_MSB_RIGHT (BIT(17))
-#define I2S_RX_MSB_RIGHT_S 17
-#define I2S_TX_MSB_RIGHT (BIT(16))
-#define I2S_TX_MSB_RIGHT_S 16
-#define I2S_I2S_RX_MONO (BIT(15))
-#define I2S_I2S_RX_MONO_S 15
-#define I2S_I2S_TX_MONO (BIT(14))
-#define I2S_I2S_TX_MONO_S 14
-#define I2S_I2S_RX_SHORT_SYNC (BIT(13))
-#define I2S_I2S_RX_SHORT_SYNC_S 13
-#define I2S_I2S_TX_SHORT_SYNC (BIT(12))
-#define I2S_I2S_TX_SHORT_SYNC_S 12
-#define I2S_RX_MSB_SHIFT (BIT(11))
-#define I2S_RX_MSB_SHIFT_S 11
-#define I2S_TX_MSB_SHIFT (BIT(10))
-#define I2S_TX_MSB_SHIFT_S 10
-#define I2S_RX_RIGHT_FIRST (BIT(9))
-#define I2S_RX_RIGHT_FIRST_S 9
-#define I2S_TX_RIGHT_FIRST (BIT(8))
-#define I2S_TX_RIGHT_FIRST_S 8
-#define I2S_RX_SLAVE_MOD (BIT(7))
-#define I2S_RX_SLAVE_MOD_S 7
-#define I2S_TX_SLAVE_MOD (BIT(6))
-#define I2S_TX_SLAVE_MOD_S 6
-#define I2S_I2S_RX_START (BIT(5))
-#define I2S_I2S_RX_START_S 5
-#define I2S_I2S_TX_START (BIT(4))
-#define I2S_I2S_TX_START_S 4
-#define I2S_I2S_RX_FIFO_RESET (BIT(3))
-#define I2S_I2S_RX_FIFO_RESET_S 3
-#define I2S_I2S_TX_FIFO_RESET (BIT(2))
-#define I2S_I2S_TX_FIFO_RESET_S 2
-#define I2S_I2S_RX_RESET (BIT(1))
-#define I2S_I2S_RX_RESET_S 1
-#define I2S_I2S_TX_RESET (BIT(0))
-#define I2S_I2S_TX_RESET_S 0
-
-#define I2SINT_RAW (DR_REG_I2S_BASE + 0x000c)
-#define I2S_I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16))
-#define I2S_I2S_OUT_TOTAL_EOF_INT_RAW_S 16
-#define I2S_I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15))
-#define I2S_I2S_IN_DSCR_EMPTY_INT_RAW_S 15
-#define I2S_I2S_OUT_DSCR_ERR_INT_RAW (BIT(14))
-#define I2S_I2S_OUT_DSCR_ERR_INT_RAW_S 14
-#define I2S_I2S_IN_DSCR_ERR_INT_RAW (BIT(13))
-#define I2S_I2S_IN_DSCR_ERR_INT_RAW_S 13
-#define I2S_I2S_OUT_EOF_INT_RAW (BIT(12))
-#define I2S_I2S_OUT_EOF_INT_RAW_S 12
-#define I2S_I2S_OUT_DONE_INT_RAW (BIT(11))
-#define I2S_I2S_OUT_DONE_INT_RAW_S 11
-#define I2S_I2S_IN_ERR_EOF_INT_RAW (BIT(10))
-#define I2S_I2S_IN_ERR_EOF_INT_RAW_S 10
-#define I2S_I2S_IN_SUC_EOF_INT_RAW (BIT(9))
-#define I2S_I2S_IN_SUC_EOF_INT_RAW_S 9
-#define I2S_I2S_IN_DONE_INT_RAW (BIT(8))
-#define I2S_I2S_IN_DONE_INT_RAW_S 8
-#define I2S_I2S_TX_HUNG_INT_RAW (BIT(7))
-#define I2S_I2S_TX_HUNG_INT_RAW_S 7
-#define I2S_I2S_RX_HUNG_INT_RAW (BIT(6))
-#define I2S_I2S_RX_HUNG_INT_RAW_S 6
-#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
-#define I2S_I2S_TX_REMPTY_INT_RAW_S 5
-#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
-#define I2S_I2S_TX_WFULL_INT_RAW_S 4
-#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
-#define I2S_I2S_RX_REMPTY_INT_RAW_S 3
-#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
-#define I2S_I2S_RX_WFULL_INT_RAW_S 2
-#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
-#define I2S_I2S_TX_PUT_DATA_INT_RAW_S 1
-#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
-#define I2S_I2S_RX_TAKE_DATA_INT_RAW_S 0
-
-#define I2SINT_ST (DR_REG_I2S_BASE + 0x0010)
-#define I2S_I2S_OUT_TOTAL_EOF_INT_ST (BIT(16))
-#define I2S_I2S_OUT_TOTAL_EOF_INT_ST_S 16
-#define I2S_I2S_IN_DSCR_EMPTY_INT_ST (BIT(15))
-#define I2S_I2S_IN_DSCR_EMPTY_INT_ST_S 15
-#define I2S_I2S_OUT_DSCR_ERR_INT_ST (BIT(14))
-#define I2S_I2S_OUT_DSCR_ERR_INT_ST_S 14
-#define I2S_I2S_IN_DSCR_ERR_INT_ST (BIT(13))
-#define I2S_I2S_IN_DSCR_ERR_INT_ST_S 13
-#define I2S_I2S_OUT_EOF_INT_ST (BIT(12))
-#define I2S_I2S_OUT_EOF_INT_ST_S 12
-#define I2S_I2S_OUT_DONE_INT_ST (BIT(11))
-#define I2S_I2S_OUT_DONE_INT_ST_S 11
-#define I2S_I2S_IN_ERR_EOF_INT_ST (BIT(10))
-#define I2S_I2S_IN_ERR_EOF_INT_ST_S 10
-#define I2S_I2S_IN_SUC_EOF_INT_ST (BIT(9))
-#define I2S_I2S_IN_SUC_EOF_INT_ST_S 9
-#define I2S_I2S_IN_DONE_INT_ST (BIT(8))
-#define I2S_I2S_IN_DONE_INT_ST_S 8
-#define I2S_I2S_TX_HUNG_INT_ST (BIT(7))
-#define I2S_I2S_TX_HUNG_INT_ST_S 7
-#define I2S_I2S_RX_HUNG_INT_ST (BIT(6))
-#define I2S_I2S_RX_HUNG_INT_ST_S 6
-#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
-#define I2S_I2S_TX_REMPTY_INT_ST_S 5
-#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
-#define I2S_I2S_TX_WFULL_INT_ST_S 4
-#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
-#define I2S_I2S_RX_REMPTY_INT_ST_S 3
-#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
-#define I2S_I2S_RX_WFULL_INT_ST_S 2
-#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
-#define I2S_I2S_TX_PUT_DATA_INT_ST_S 1
-#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
-#define I2S_I2S_RX_TAKE_DATA_INT_ST_S 0
-
-#define I2SINT_ENA (DR_REG_I2S_BASE + 0x0014)
-#define I2S_I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16))
-#define I2S_I2S_OUT_TOTAL_EOF_INT_ENA_S 16
-#define I2S_I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15))
-#define I2S_I2S_IN_DSCR_EMPTY_INT_ENA_S 15
-#define I2S_I2S_OUT_DSCR_ERR_INT_ENA (BIT(14))
-#define I2S_I2S_OUT_DSCR_ERR_INT_ENA_S 14
-#define I2S_I2S_IN_DSCR_ERR_INT_ENA (BIT(13))
-#define I2S_I2S_IN_DSCR_ERR_INT_ENA_S 13
-#define I2S_I2S_OUT_EOF_INT_ENA (BIT(12))
-#define I2S_I2S_OUT_EOF_INT_ENA_S 12
-#define I2S_I2S_OUT_DONE_INT_ENA (BIT(11))
-#define I2S_I2S_OUT_DONE_INT_ENA_S 11
-#define I2S_I2S_IN_ERR_EOF_INT_ENA (BIT(10))
-#define I2S_I2S_IN_ERR_EOF_INT_ENA_S 10
-#define I2S_I2S_IN_SUC_EOF_INT_ENA (BIT(9))
-#define I2S_I2S_IN_SUC_EOF_INT_ENA_S 9
-#define I2S_I2S_IN_DONE_INT_ENA (BIT(8))
-#define I2S_I2S_IN_DONE_INT_ENA_S 8
-#define I2S_I2S_TX_HUNG_INT_ENA (BIT(7))
-#define I2S_I2S_TX_HUNG_INT_ENA_S 7
-#define I2S_I2S_RX_HUNG_INT_ENA (BIT(6))
-#define I2S_I2S_RX_HUNG_INT_ENA_S 6
-#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
-#define I2S_I2S_TX_REMPTY_INT_ENA_S 5
-#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
-#define I2S_I2S_TX_WFULL_INT_ENA_S 4
-#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
-#define I2S_I2S_RX_REMPTY_INT_ENA_S 3
-#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
-#define I2S_I2S_RX_WFULL_INT_ENA_S 2
-#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
-#define I2S_I2S_TX_PUT_DATA_INT_ENA_S 1
-#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
-#define I2S_I2S_RX_TAKE_DATA_INT_ENA_S 0
-
-#define I2SINT_CLR (DR_REG_I2S_BASE + 0x0018)
-#define I2S_I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16))
-#define I2S_I2S_OUT_TOTAL_EOF_INT_CLR_S 16
-#define I2S_I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15))
-#define I2S_I2S_IN_DSCR_EMPTY_INT_CLR_S 15
-#define I2S_I2S_OUT_DSCR_ERR_INT_CLR (BIT(14))
-#define I2S_I2S_OUT_DSCR_ERR_INT_CLR_S 14
-#define I2S_I2S_IN_DSCR_ERR_INT_CLR (BIT(13))
-#define I2S_I2S_IN_DSCR_ERR_INT_CLR_S 13
-#define I2S_I2S_OUT_EOF_INT_CLR (BIT(12))
-#define I2S_I2S_OUT_EOF_INT_CLR_S 12
-#define I2S_I2S_OUT_DONE_INT_CLR (BIT(11))
-#define I2S_I2S_OUT_DONE_INT_CLR_S 11
-#define I2S_I2S_IN_ERR_EOF_INT_CLR (BIT(10))
-#define I2S_I2S_IN_ERR_EOF_INT_CLR_S 10
-#define I2S_I2S_IN_SUC_EOF_INT_CLR (BIT(9))
-#define I2S_I2S_IN_SUC_EOF_INT_CLR_S 9
-#define I2S_I2S_IN_DONE_INT_CLR (BIT(8))
-#define I2S_I2S_IN_DONE_INT_CLR_S 8
-#define I2S_I2S_TX_HUNG_INT_CLR (BIT(7))
-#define I2S_I2S_TX_HUNG_INT_CLR_S 7
-#define I2S_I2S_RX_HUNG_INT_CLR (BIT(6))
-#define I2S_I2S_RX_HUNG_INT_CLR_S 6
-#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
-#define I2S_I2S_TX_REMPTY_INT_CLR_S 5
-#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
-#define I2S_I2S_TX_WFULL_INT_CLR_S 4
-#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
-#define I2S_I2S_RX_REMPTY_INT_CLR_S 3
-#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
-#define I2S_I2S_RX_WFULL_INT_CLR_S 2
-#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
-#define I2S_I2S_PUT_DATA_INT_CLR_S 1
-#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
-#define I2S_I2S_TAKE_DATA_INT_CLR_S 0
-
-#define I2STIMING (DR_REG_I2S_BASE + 0x001c)
-#define I2S_TX_BCK_IN_INV (BIT(24))
-#define I2S_TX_BCK_IN_INV_S 24
-#define I2S_DATA_ENABLE_DELAY 0x00000003
-#define I2S_DATA_ENABLE_DELAY_S 22
-#define I2S_RX_DSYNC_SW (BIT(21))
-#define I2S_RX_DSYNC_SW_S 21
-#define I2S_TX_DSYNC_SW (BIT(20))
-#define I2S_TX_DSYNC_SW_S 20
-#define I2S_RX_BCK_OUT_DELAY 0x00000003
-#define I2S_RX_BCK_OUT_DELAY_S 18
-#define I2S_RX_WS_OUT_DELAY 0x00000003
-#define I2S_RX_WS_OUT_DELAY_S 16
-#define I2S_TX_SD_OUT_DELAY 0x00000003
-#define I2S_TX_SD_OUT_DELAY_S 14
-#define I2S_TX_WS_OUT_DELAY 0x00000003
-#define I2S_TX_WS_OUT_DELAY_S 12
-#define I2S_TX_BCK_OUT_DELAY 0x00000003
-#define I2S_TX_BCK_OUT_DELAY_S 10
-#define I2S_RX_SD_IN_DELAY 0x00000003
-#define I2S_RX_SD_IN_DELAY_S 8
-#define I2S_RX_WS_IN_DELAY 0x00000003
-#define I2S_RX_WS_IN_DELAY_S 6
-#define I2S_RX_BCK_IN_DELAY 0x00000003
-#define I2S_RX_BCK_IN_DELAY_S 4
-#define I2S_TX_WS_IN_DELAY 0x00000003
-#define I2S_TX_WS_IN_DELAY_S 2
-#define I2S_TX_BCK_IN_DELAY 0x00000003
-#define I2S_TX_BCK_IN_DELAY_S 0
-
-#define I2S_FIFO_CONF (DR_REG_I2S_BASE + 0x0020)
-#define I2S_I2S_RX_FIFO_MOD_FORCE_EN (BIT(20))
-#define I2S_I2S_RX_FIFO_MOD_FORCE_EN_S 20
-#define I2S_I2S_TX_FIFO_MOD_FORCE_EN (BIT(19))
-#define I2S_I2S_TX_FIFO_MOD_FORCE_EN_S 19
-#define I2S_I2S_RX_FIFO_MOD 0x00000007
-#define I2S_I2S_RX_FIFO_MOD_S 16
-#define I2S_I2S_TX_FIFO_MOD 0x00000007
-#define I2S_I2S_TX_FIFO_MOD_S 13
-#define I2S_I2S_DSCR_EN (BIT(12))
-#define I2S_I2S_DSCR_EN_S 12
-#define I2S_I2S_TX_DATA_NUM 0x0000003F
-#define I2S_I2S_TX_DATA_NUM_S 6
-#define I2S_I2S_RX_DATA_NUM 0x0000003F
-#define I2S_I2S_RX_DATA_NUM_S 0
-
-#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
-#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
-#define I2S_I2S_RX_EOF_NUM_S 0
-
-#define I2SCONF_SIGLE_DATA (DR_REG_I2S_BASE + 0x0028)
-#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
-#define I2S_I2S_SIGLE_DATA_S 0
-
-#define I2SCONF_CHAN (DR_REG_I2S_BASE + 0x002c)
-#define I2S_RX_CHAN_MOD 0x00000003
-#define I2S_RX_CHAN_MOD_S 3
-#define I2S_TX_CHAN_MOD 0x00000007
-#define I2S_TX_CHAN_MOD_S 0
-
-#define I2SOUT_LINK (DR_REG_I2S_BASE + 0x0030)
-#define I2S_OUTLINK_PARK (BIT(31))
-#define I2S_OUTLINK_PARK_S 31
-#define I2S_I2S_OUTLINK_RESTART (BIT(30))
-#define I2S_I2S_OUTLINK_RESTART_S 30
-#define I2S_I2S_OUTLINK_START (BIT(29))
-#define I2S_I2S_OUTLINK_START_S 29
-#define I2S_I2S_OUTLINK_STOP (BIT(28))
-#define I2S_I2S_OUTLINK_STOP_S 28
-#define I2S_I2S_OUTLINK_ADDR 0x000FFFFF
-#define I2S_I2S_OUTLINK_ADDR_S 0
-
-#define I2SIN_LINK (DR_REG_I2S_BASE + 0x0034)
-#define I2S_INLINK_PARK (BIT(31))
-#define I2S_INLINK_PARK_S 31
-#define I2S_I2S_INLINK_RESTART (BIT(30))
-#define I2S_I2S_INLINK_RESTART_S 30
-#define I2S_I2S_INLINK_START (BIT(29))
-#define I2S_I2S_INLINK_START_S 29
-#define I2S_I2S_INLINK_STOP (BIT(28))
-#define I2S_I2S_INLINK_STOP_S 28
-#define I2S_I2S_INLINK_ADDR 0x000FFFFF
-#define I2S_I2S_INLINK_ADDR_S 0
-
-#define I2S_OUT_EOF_DES_ADDR (DR_REG_I2S_BASE + 0x0038)
-#define I2S_I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF
-#define I2S_I2S_OUT_EOF_DES_ADDR_S 0
-
-#define I2S_IN_EOF_DES_ADDR (DR_REG_I2S_BASE + 0x003c)
-#define I2S_I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
-#define I2S_I2S_IN_SUC_EOF_DES_ADDR_S 0
-
-#define I2S_OUT_EOF_BFR_DES_ADDR (DR_REG_I2S_BASE + 0x0040)
-#define I2S_I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
-#define I2S_I2S_OUT_EOF_BFR_DES_ADDR_S 0
-
-#define I2S_AHB_TEST (DR_REG_I2S_BASE + 0x0044)
-#define I2S_I2S_AHB_TESTADDR 0x00000003
-#define I2S_I2S_AHB_TESTADDR_S 4
-#define I2S_I2S_AHB_TESTMODE 0x00000007
-#define I2S_I2S_AHB_TESTMODE_S 0
-
-#define I2S_INLINK_DSCR (DR_REG_I2S_BASE + 0x0048)
-#define I2S_I2S_INLINK_DSCR 0xFFFFFFFF
-#define I2S_I2S_INLINK_DSCR_S 0
-
-#define I2S_INLINK_DSCR_BF0 (DR_REG_I2S_BASE + 0x004C)
-#define I2S_I2S_INLINK_DSCR_BF0 0xFFFFFFFF
-#define I2S_I2S_INLINK_DSCR_BF0_S 0
-
-#define I2S_INLINK_DSCR_BF1 (DR_REG_I2S_BASE + 0x0050)
-#define I2S_I2S_INLINK_DSCR_BF1 0xFFFFFFFF
-#define I2S_I2S_INLINK_DSCR_BF1_S 0
-
-#define I2S_OUTLINK_DSCR (DR_REG_I2S_BASE + 0x0054)
-#define I2S_I2S_OUTLINK_DSCR 0xFFFFFFFF
-#define I2S_I2S_OUTLINK_DSCR_S 0
-
-#define I2S_OUTLINK_DSCR_BF0 (DR_REG_I2S_BASE + 0x0058)
-#define I2S_I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF
-#define I2S_I2S_OUTLINK_DSCR_BF0_S 0
-
-#define I2S_OUTLINK_DSCR_BF1 (DR_REG_I2S_BASE + 0x005C)
-#define I2S_I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF
-#define I2S_I2S_OUTLINK_DSCR_BF1_S 0
-
-#define I2S_LC_CONF (DR_REG_I2S_BASE + 0x0060)
-#define I2S_I2S_MEM_TRANS_EN (BIT(13))
-#define I2S_I2S_MEM_TRANS_EN_S 13
-#define I2S_I2S_CHECK_OWNER (BIT(12))
-#define I2S_I2S_CHECK_OWNER_S 12
-#define I2S_I2S_OUT_DATA_BURST_EN (BIT(11))
-#define I2S_I2S_OUT_DATA_BURST_EN_S 11
-#define I2S_I2S_INDSCR_BURST_EN (BIT(10))
-#define I2S_I2S_INDSCR_BURST_EN_S 10
-#define I2S_I2S_OUTDSCR_BURST_EN (BIT(9))
-#define I2S_I2S_OUTDSCR_BURST_EN_S 9
-#define I2S_I2S_OUT_EOF_MODE (BIT(8))
-#define I2S_I2S_OUT_EOF_MODE_S 8
-#define I2S_I2S_OUT_NO_RESTART_CLR (BIT(7))
-#define I2S_I2S_OUT_NO_RESTART_CLR_S 7
-#define I2S_I2S_OUT_AUTO_WRBACK (BIT(6))
-#define I2S_I2S_OUT_AUTO_WRBACK_S 6
-#define I2S_I2S_IN_LOOP_TEST (BIT(5))
-#define I2S_I2S_IN_LOOP_TEST_S 5
-#define I2S_I2S_OUT_LOOP_TEST (BIT(4))
-#define I2S_I2S_OUT_LOOP_TEST_S 4
-#define I2S_I2S_AHBM_RST (BIT(3))
-#define I2S_I2S_AHBM_RST_S 3
-#define I2S_I2S_AHBM_FIFO_RST (BIT(2))
-#define I2S_I2S_AHBM_FIFO_RST_S 2
-#define I2S_I2S_OUT_RST (BIT(1))
-#define I2S_I2S_OUT_RST_S 1
-#define I2S_I2S_IN_RST (BIT(0))
-#define I2S_I2S_IN_RST_S 0
-
-#define I2S_OUTFIFO_PUSH (DR_REG_I2S_BASE + 0x0064)
-#define I2S_I2S_OUTFIFO_PUSH (BIT(16))
-#define I2S_I2S_OUTFIFO_PUSH_S 16
-#define I2S_I2S_OUTFIFO_WDATA 0x000001FF
-#define I2S_I2S_OUTFIFO_WDATA_S 0
-
-#define I2S_INFIFO_POP (DR_REG_I2S_BASE + 0x0068)
-#define I2S_I2S_INFIFO_POP (BIT(16))
-#define I2S_I2S_INFIFO_POP_S 16
-#define I2S_I2S_INFIFO_RDATA 0x00000FFF
-#define I2S_I2S_INFIFO_RDATA_S 0
-
-#define I2S_LC_STATE0 (DR_REG_I2S_BASE + 0x006C)
-#define I2S_I2S_LC_STATE0 0xFFFFFFFF
-#define I2S_I2S_LC_STATE0_S 0
-
-#define I2S_LC_STATE1 (DR_REG_I2S_BASE + 0x0070)
-#define I2S_I2S_LC_STATE1 0xFFFFFFFF
-#define I2S_I2S_LC_STATE1_S 0
-
-#define I2S_LC_HUNG_CONF (DR_REG_I2S_BASE + 0x0074)
-#define I2S_I2S_LC_FIFO_TIMEOUT_ENA (BIT(11))
-#define I2S_I2S_LC_FIFO_TIMEOUT_ENA_S 11
-#define I2S_I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
-#define I2S_I2S_LC_FIFO_TIMEOUT_SHIFT_S 8
-#define I2S_I2S_LC_FIFO_TIMEOUT 0x000000FF
-#define I2S_I2S_LC_FIFO_TIMEOUT_S 0
-
-#define I2S_CVSD_CONF0 (DR_REG_I2S_BASE + 0x0080)
-#define I2S_I2S_CVSD_Y_MIN 0x0000FFFF
-#define I2S_I2S_CVSD_Y_MIN_S 16
-#define I2S_I2S_CVSD_Y_MAX 0x0000FFFF
-#define I2S_I2S_CVSD_Y_MAX_S 0
-
-#define I2S_CVSD_CONF1 (DR_REG_I2S_BASE + 0x0084)
-#define I2S_I2S_CVSD_SIGMA_MIN 0x0000FFFF
-#define I2S_I2S_CVSD_SIGMA_MIN_S 16
-#define I2S_I2S_CVSD_SIGMA_MAX 0x0000FFFF
-#define I2S_I2S_CVSD_SIGMA_MAX_S 0
-
-#define I2S_CVSD_CONF2 (DR_REG_I2S_BASE + 0x0088)
-#define I2S_I2S_CVSD_H 0x00000007
-#define I2S_I2S_CVSD_H_S 16
-#define I2S_I2S_CVSD_BETA 0x000003FF
-#define I2S_I2S_CVSD_BETA_S 6
-#define I2S_I2S_CVSD_J 0x00000007
-#define I2S_I2S_CVSD_J_S 3
-#define I2S_I2S_CVSD_K 0x00000007
-#define I2S_I2S_CVSD_K_S 0
-
-#define I2S_PLC_CONF0 (DR_REG_I2S_BASE + 0x008C)
-#define I2S_I2S_N_MIN_ERR 0x00000007
-#define I2S_I2S_N_MIN_ERR_S 25
-#define I2S_I2S_PACK_LEN_8K 0x0000001F
-#define I2S_I2S_PACK_LEN_8K_S 20
-#define I2S_I2S_MAX_SLIDE_SAMPLE 0x000000FF
-#define I2S_I2S_MAX_SLIDE_SAMPLE_S 12
-#define I2S_I2S_SHIFT_RATE 0x00000007
-#define I2S_I2S_SHIFT_RATE_S 9
-#define I2S_I2S_N_ERR_SEG 0x00000007
-#define I2S_I2S_N_ERR_SEG_S 6
-#define I2S_I2S_GOOD_PACK_MAX 0x0000003F
-#define I2S_I2S_GOOD_PACK_MAX_S 0
-
-#define I2S_PLC_CONF1 (DR_REG_I2S_BASE + 0x0090)
-#define I2S_I2S_SLIDE_WIN_LEN 0x000000FF
-#define I2S_I2S_SLIDE_WIN_LEN_S 24
-#define I2S_I2S_BAD_OLA_WIN2_PARA 0x000000FF
-#define I2S_I2S_BAD_OLA_WIN2_PARA_S 16
-#define I2S_I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F
-#define I2S_I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12
-#define I2S_I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F
-#define I2S_I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8
-#define I2S_I2S_BAD_CEF_ATTEN_PARA 0x000000FF
-#define I2S_I2S_BAD_CEF_ATTEN_PARA_S 0
-
-#define I2S_PLC_CONF2 (DR_REG_I2S_BASE + 0x0094)
-#define I2S_I2S_MIN_PERIOD 0x0000001F
-#define I2S_I2S_MIN_PERIOD_S 2
-#define I2S_I2S_CVSD_SEG_MOD 0x00000003
-#define I2S_I2S_CVSD_SEG_MOD_S 0
-
-#define I2S_ESCO_CONF0 (DR_REG_I2S_BASE + 0x0098)
-#define I2S_I2S_PLC2DMA_EN (BIT(12))
-#define I2S_I2S_PLC2DMA_EN_S 12
-#define I2S_I2S_PLC_EN (BIT(11))
-#define I2S_I2S_PLC_EN_S 11
-#define I2S_I2S_CVSD_DEC_RESET (BIT(10))
-#define I2S_I2S_CVSD_DEC_RESET_S 10
-#define I2S_I2S_CVSD_DEC_START (BIT(9))
-#define I2S_I2S_CVSD_DEC_START_S 9
-#define I2S_I2S_ESCO_CVSD_INF_EN (BIT(8))
-#define I2S_I2S_ESCO_CVSD_INF_EN_S 8
-#define I2S_I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F
-#define I2S_I2S_ESCO_CVSD_PACK_LEN_8K_S 3
-#define I2S_I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2))
-#define I2S_I2S_ESCO_CVSD_DEC_PACK_ERR_S 2
-#define I2S_I2S_ESCO_CHAN_MOD (BIT(1))
-#define I2S_I2S_ESCO_CHAN_MOD_S 1
-#define I2S_I2S_ESCO_EN (BIT(0))
-#define I2S_I2S_ESCO_EN_S 0
-
-#define I2S_SCO_CONF0 (DR_REG_I2S_BASE + 0x009c)
-#define I2S_I2S_CVSD_ENC_RESET (BIT(3))
-#define I2S_I2S_CVSD_ENC_RESET_S 3
-#define I2S_I2S_CVSD_ENC_START (BIT(2))
-#define I2S_I2S_CVSD_ENC_START_S 2
-#define I2S_I2S_SCO_NO_I2S_EN (BIT(1))
-#define I2S_I2S_SCO_NO_I2S_EN_S 1
-#define I2S_I2S_SCO_WITH_I2S_EN (BIT(0))
-#define I2S_I2S_SCO_WITH_I2S_EN_S 0
-
-#define I2SCONF1 (DR_REG_I2S_BASE + 0x00a0)
-#define I2S_I2S_TX_ZEROS_RM_EN (BIT(9))
-#define I2S_I2S_TX_ZEROS_RM_EN_S 9
-#define I2S_I2S_TX_STOP_EN (BIT(8))
-#define I2S_I2S_TX_STOP_EN_S 8
-#define I2S_RX_PCM_BYPASS (BIT(7))
-#define I2S_RX_PCM_BYPASS_S 7
-#define I2S_RX_PCM_CONF 0x00000007
-#define I2S_RX_PCM_CONF_S 4
-#define I2S_TX_PCM_BYPASS (BIT(3))
-#define I2S_TX_PCM_BYPASS_S 3
-#define I2S_TX_PCM_CONF 0x00000007
-#define I2S_TX_PCM_CONF_S 0
-
-#define I2S_PD_CONF (DR_REG_I2S_BASE + 0x00a4)
-#define I2S_PLC_MEM_FORCE_PU (BIT(3))
-#define I2S_PLC_MEM_FORCE_PU_S 3
-#define I2S_PLC_MEM_FORCE_PD (BIT(2))
-#define I2S_PLC_MEM_FORCE_PD_S 2
-#define I2S_I2S_FIFO_FORCE_PU (BIT(1))
-#define I2S_I2S_FIFO_FORCE_PU_S 1
-#define I2S_I2S_FIFO_FORCE_PD (BIT(0))
-#define I2S_I2S_FIFO_FORCE_PD_S 0
-
-#define I2SCONF2 (DR_REG_I2S_BASE + 0x00a8)
-#define I2S_INTER_VALID_EN (BIT(7))
-#define I2S_INTER_VALID_EN_S 7
-#define I2S_EXT_ADC_START_EN (BIT(6))
-#define I2S_EXT_ADC_START_EN_S 6
-#define I2S_LCD_EN (BIT(5))
-#define I2S_LCD_EN_S 5
-#define I2S_DATA_ENABLE (BIT(4))
-#define I2S_DATA_ENABLE_S 4
-#define I2S_DATA_ENABLE_TEST_EN (BIT(3))
-#define I2S_DATA_ENABLE_TEST_EN_S 3
-#define I2S_LCD_TX_SDX2_EN (BIT(2))
-#define I2S_LCD_TX_SDX2_EN_S 2
-#define I2S_LCD_TX_WRX2_EN (BIT(1))
-#define I2S_LCD_TX_WRX2_EN_S 1
-#define I2S_CAMERA_EN (BIT(0))
-#define I2S_CAMERA_EN_S 0
-
-#define I2S_CLKM_CONF (DR_REG_I2S_BASE + 0x00ac)
-#define I2S_CLKA_ENA (BIT(21))
-#define I2S_CLKA_ENA_S 21
-#define I2S_CLK_EN (BIT(20))
-#define I2S_CLK_EN_S 20
-#define I2S_CLKM_DIV_A 0x0000003F
-#define I2S_CLKM_DIV_A_S 14
-#define I2S_CLKM_DIV_B 0x0000003F
-#define I2S_CLKM_DIV_B_S 8
-#define I2S_CLKM_DIV_NUM 0x000000FF
-#define I2S_CLKM_DIV_NUM_S 0
-
-#define I2S_SAMPLE_RATE_CONF (DR_REG_I2S_BASE + 0x00b0)
-#define I2S_RX_BITS_MOD 0x0000003F
-#define I2S_RX_BITS_MOD_S 18
-#define I2S_TX_BITS_MOD 0x0000003F
-#define I2S_TX_BITS_MOD_S 12
-#define I2S_RX_BCK_DIV_NUM 0x0000003F
-#define I2S_RX_BCK_DIV_NUM_S 6
-#define I2S_TX_BCK_DIV_NUM 0x0000003F
-#define I2S_TX_BCK_DIV_NUM_S 0
-
-#define I2S_PDM_CONF (DR_REG_I2S_BASE + 0x00b4)
-#define I2S_TX_PDM_HP_BYPASS (BIT(25))
-#define I2S_TX_PDM_HP_BYPASS_S 25
-#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24))
-#define I2S_RX_PDM_SINC_DSR_16_EN_S 24
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22
-#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003
-#define I2S_TX_PDM_SINC_IN_SHIFT_S 20
-#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003
-#define I2S_TX_PDM_LP_IN_SHIFT_S 18
-#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003
-#define I2S_TX_PDM_HP_IN_SHIFT_S 16
-#define I2S_TX_PDM_PRESCALE 0x000000FF
-#define I2S_TX_PDM_PRESCALE_S 8
-#define I2S_TX_PDM_SINC_OSR2 0x0000000F
-#define I2S_TX_PDM_SINC_OSR2_S 4
-#define I2S_PDM2PCM_CONV_EN (BIT(3))
-#define I2S_PDM2PCM_CONV_EN_S 3
-#define I2S_PCM2PDM_CONV_EN (BIT(2))
-#define I2S_PCM2PDM_CONV_EN_S 2
-#define I2S_RX_PDM_EN (BIT(1))
-#define I2S_RX_PDM_EN_S 1
-#define I2S_TX_PDM_EN (BIT(0))
-#define I2S_TX_PDM_EN_S 0
-
-#define I2S_PDM_FREQ_CONF (DR_REG_I2S_BASE + 0x00b8)
-#define I2S_TX_PDM_FP 0x000003FF
-#define I2S_TX_PDM_FP_S 10
-#define I2S_TX_PDM_FS 0x000003FF
-#define I2S_TX_PDM_FS_S 0
-
-#define I2S_STATE (DR_REG_I2S_BASE + 0x00bc)
-#define I2S_I2S_RX_FIFO_RESET_BACK (BIT(2))
-#define I2S_I2S_RX_FIFO_RESET_BACK_S 2
-#define I2S_I2S_TX_FIFO_RESET_BACK (BIT(1))
-#define I2S_I2S_TX_FIFO_RESET_BACK_S 1
-#define I2S_I2S_TX_IDLE (BIT(0))
-#define I2S_I2S_TX_IDLE_S 0
-
-#define I2S_DATE (DR_REG_I2S_BASE + 0x00fc)
-#define I2S_I2SDATE 0xFFFFFFFF
-#define I2S_I2SDATE_S 0
-
-#endif /* _SOC_I2S_REG_H_ */
+#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))
+
+
+#define I2SCONF_REG(i) (REG_I2S_BASE(i) + 0x0008)
+/* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define I2S_SIG_LOOPBACK (BIT(18))
+#define I2S_SIG_LOOPBACK_M (BIT(18))
+#define I2S_SIG_LOOPBACK_V 0x1
+#define I2S_SIG_LOOPBACK_S 18
+/* I2S_RX_MSB_RIGHT : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: */
+#define I2S_RX_MSB_RIGHT (BIT(17))
+#define I2S_RX_MSB_RIGHT_M (BIT(17))
+#define I2S_RX_MSB_RIGHT_V 0x1
+#define I2S_RX_MSB_RIGHT_S 17
+/* I2S_TX_MSB_RIGHT : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define I2S_TX_MSB_RIGHT (BIT(16))
+#define I2S_TX_MSB_RIGHT_M (BIT(16))
+#define I2S_TX_MSB_RIGHT_V 0x1
+#define I2S_TX_MSB_RIGHT_S 16
+/* I2S_RX_MONO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_MONO (BIT(15))
+#define I2S_RX_MONO_M (BIT(15))
+#define I2S_RX_MONO_V 0x1
+#define I2S_RX_MONO_S 15
+/* I2S_TX_MONO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_MONO (BIT(14))
+#define I2S_TX_MONO_M (BIT(14))
+#define I2S_TX_MONO_V 0x1
+#define I2S_TX_MONO_S 14
+/* I2S_RX_SHORT_SYNC : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_SHORT_SYNC (BIT(13))
+#define I2S_RX_SHORT_SYNC_M (BIT(13))
+#define I2S_RX_SHORT_SYNC_V 0x1
+#define I2S_RX_SHORT_SYNC_S 13
+/* I2S_TX_SHORT_SYNC : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_SHORT_SYNC (BIT(12))
+#define I2S_TX_SHORT_SYNC_M (BIT(12))
+#define I2S_TX_SHORT_SYNC_V 0x1
+#define I2S_TX_SHORT_SYNC_S 12
+/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_MSB_SHIFT (BIT(11))
+#define I2S_RX_MSB_SHIFT_M (BIT(11))
+#define I2S_RX_MSB_SHIFT_V 0x1
+#define I2S_RX_MSB_SHIFT_S 11
+/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_MSB_SHIFT (BIT(10))
+#define I2S_TX_MSB_SHIFT_M (BIT(10))
+#define I2S_TX_MSB_SHIFT_V 0x1
+#define I2S_TX_MSB_SHIFT_S 10
+/* I2S_RX_RIGHT_FIRST : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define I2S_RX_RIGHT_FIRST (BIT(9))
+#define I2S_RX_RIGHT_FIRST_M (BIT(9))
+#define I2S_RX_RIGHT_FIRST_V 0x1
+#define I2S_RX_RIGHT_FIRST_S 9
+/* I2S_TX_RIGHT_FIRST : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define I2S_TX_RIGHT_FIRST (BIT(8))
+#define I2S_TX_RIGHT_FIRST_M (BIT(8))
+#define I2S_TX_RIGHT_FIRST_V 0x1
+#define I2S_TX_RIGHT_FIRST_S 8
+/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_SLAVE_MOD (BIT(7))
+#define I2S_RX_SLAVE_MOD_M (BIT(7))
+#define I2S_RX_SLAVE_MOD_V 0x1
+#define I2S_RX_SLAVE_MOD_S 7
+/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_SLAVE_MOD (BIT(6))
+#define I2S_TX_SLAVE_MOD_M (BIT(6))
+#define I2S_TX_SLAVE_MOD_V 0x1
+#define I2S_TX_SLAVE_MOD_S 6
+/* I2S_RX_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_START (BIT(5))
+#define I2S_RX_START_M (BIT(5))
+#define I2S_RX_START_V 0x1
+#define I2S_RX_START_S 5
+/* I2S_TX_START : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_START (BIT(4))
+#define I2S_TX_START_M (BIT(4))
+#define I2S_TX_START_V 0x1
+#define I2S_TX_START_S 4
+/* I2S_RX_FIFO_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_FIFO_RESET (BIT(3))
+#define I2S_RX_FIFO_RESET_M (BIT(3))
+#define I2S_RX_FIFO_RESET_V 0x1
+#define I2S_RX_FIFO_RESET_S 3
+/* I2S_TX_FIFO_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_FIFO_RESET (BIT(2))
+#define I2S_TX_FIFO_RESET_M (BIT(2))
+#define I2S_TX_FIFO_RESET_V 0x1
+#define I2S_TX_FIFO_RESET_S 2
+/* I2S_RX_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_RESET (BIT(1))
+#define I2S_RX_RESET_M (BIT(1))
+#define I2S_RX_RESET_V 0x1
+#define I2S_RX_RESET_S 1
+/* I2S_TX_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_RESET (BIT(0))
+#define I2S_TX_RESET_M (BIT(0))
+#define I2S_TX_RESET_V 0x1
+#define I2S_TX_RESET_S 0
+
+#define I2SINT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c)
+/* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_RAW_M (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_RAW_V 0x1
+#define I2S_OUT_TOTAL_EOF_INT_RAW_S 16
+/* I2S_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_RAW_M (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_RAW_V 0x1
+#define I2S_IN_DSCR_EMPTY_INT_RAW_S 15
+/* I2S_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DSCR_ERR_INT_RAW (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_RAW_M (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_RAW_V 0x1
+#define I2S_OUT_DSCR_ERR_INT_RAW_S 14
+/* I2S_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_ERR_INT_RAW (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_RAW_M (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_RAW_V 0x1
+#define I2S_IN_DSCR_ERR_INT_RAW_S 13
+/* I2S_OUT_EOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_EOF_INT_RAW (BIT(12))
+#define I2S_OUT_EOF_INT_RAW_M (BIT(12))
+#define I2S_OUT_EOF_INT_RAW_V 0x1
+#define I2S_OUT_EOF_INT_RAW_S 12
+/* I2S_OUT_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DONE_INT_RAW (BIT(11))
+#define I2S_OUT_DONE_INT_RAW_M (BIT(11))
+#define I2S_OUT_DONE_INT_RAW_V 0x1
+#define I2S_OUT_DONE_INT_RAW_S 11
+/* I2S_IN_ERR_EOF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_ERR_EOF_INT_RAW (BIT(10))
+#define I2S_IN_ERR_EOF_INT_RAW_M (BIT(10))
+#define I2S_IN_ERR_EOF_INT_RAW_V 0x1
+#define I2S_IN_ERR_EOF_INT_RAW_S 10
+/* I2S_IN_SUC_EOF_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_SUC_EOF_INT_RAW (BIT(9))
+#define I2S_IN_SUC_EOF_INT_RAW_M (BIT(9))
+#define I2S_IN_SUC_EOF_INT_RAW_V 0x1
+#define I2S_IN_SUC_EOF_INT_RAW_S 9
+/* I2S_IN_DONE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DONE_INT_RAW (BIT(8))
+#define I2S_IN_DONE_INT_RAW_M (BIT(8))
+#define I2S_IN_DONE_INT_RAW_V 0x1
+#define I2S_IN_DONE_INT_RAW_S 8
+/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_HUNG_INT_RAW (BIT(7))
+#define I2S_TX_HUNG_INT_RAW_M (BIT(7))
+#define I2S_TX_HUNG_INT_RAW_V 0x1
+#define I2S_TX_HUNG_INT_RAW_S 7
+/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_HUNG_INT_RAW (BIT(6))
+#define I2S_RX_HUNG_INT_RAW_M (BIT(6))
+#define I2S_RX_HUNG_INT_RAW_V 0x1
+#define I2S_RX_HUNG_INT_RAW_S 6
+/* I2S_TX_REMPTY_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_REMPTY_INT_RAW (BIT(5))
+#define I2S_TX_REMPTY_INT_RAW_M (BIT(5))
+#define I2S_TX_REMPTY_INT_RAW_V 0x1
+#define I2S_TX_REMPTY_INT_RAW_S 5
+/* I2S_TX_WFULL_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_WFULL_INT_RAW (BIT(4))
+#define I2S_TX_WFULL_INT_RAW_M (BIT(4))
+#define I2S_TX_WFULL_INT_RAW_V 0x1
+#define I2S_TX_WFULL_INT_RAW_S 4
+/* I2S_RX_REMPTY_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_REMPTY_INT_RAW (BIT(3))
+#define I2S_RX_REMPTY_INT_RAW_M (BIT(3))
+#define I2S_RX_REMPTY_INT_RAW_V 0x1
+#define I2S_RX_REMPTY_INT_RAW_S 3
+/* I2S_RX_WFULL_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_WFULL_INT_RAW (BIT(2))
+#define I2S_RX_WFULL_INT_RAW_M (BIT(2))
+#define I2S_RX_WFULL_INT_RAW_V 0x1
+#define I2S_RX_WFULL_INT_RAW_S 2
+/* I2S_TX_PUT_DATA_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_PUT_DATA_INT_RAW (BIT(1))
+#define I2S_TX_PUT_DATA_INT_RAW_M (BIT(1))
+#define I2S_TX_PUT_DATA_INT_RAW_V 0x1
+#define I2S_TX_PUT_DATA_INT_RAW_S 1
+/* I2S_RX_TAKE_DATA_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_RAW_M (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_RAW_V 0x1
+#define I2S_RX_TAKE_DATA_INT_RAW_S 0
+
+#define I2SINT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010)
+/* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_ST_M (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_ST_V 0x1
+#define I2S_OUT_TOTAL_EOF_INT_ST_S 16
+/* I2S_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_EMPTY_INT_ST (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_ST_M (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_ST_V 0x1
+#define I2S_IN_DSCR_EMPTY_INT_ST_S 15
+/* I2S_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DSCR_ERR_INT_ST (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_ST_M (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_ST_V 0x1
+#define I2S_OUT_DSCR_ERR_INT_ST_S 14
+/* I2S_IN_DSCR_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_ERR_INT_ST (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_ST_M (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_ST_V 0x1
+#define I2S_IN_DSCR_ERR_INT_ST_S 13
+/* I2S_OUT_EOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_EOF_INT_ST (BIT(12))
+#define I2S_OUT_EOF_INT_ST_M (BIT(12))
+#define I2S_OUT_EOF_INT_ST_V 0x1
+#define I2S_OUT_EOF_INT_ST_S 12
+/* I2S_OUT_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DONE_INT_ST (BIT(11))
+#define I2S_OUT_DONE_INT_ST_M (BIT(11))
+#define I2S_OUT_DONE_INT_ST_V 0x1
+#define I2S_OUT_DONE_INT_ST_S 11
+/* I2S_IN_ERR_EOF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_ERR_EOF_INT_ST (BIT(10))
+#define I2S_IN_ERR_EOF_INT_ST_M (BIT(10))
+#define I2S_IN_ERR_EOF_INT_ST_V 0x1
+#define I2S_IN_ERR_EOF_INT_ST_S 10
+/* I2S_IN_SUC_EOF_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_SUC_EOF_INT_ST (BIT(9))
+#define I2S_IN_SUC_EOF_INT_ST_M (BIT(9))
+#define I2S_IN_SUC_EOF_INT_ST_V 0x1
+#define I2S_IN_SUC_EOF_INT_ST_S 9
+/* I2S_IN_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DONE_INT_ST (BIT(8))
+#define I2S_IN_DONE_INT_ST_M (BIT(8))
+#define I2S_IN_DONE_INT_ST_V 0x1
+#define I2S_IN_DONE_INT_ST_S 8
+/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_HUNG_INT_ST (BIT(7))
+#define I2S_TX_HUNG_INT_ST_M (BIT(7))
+#define I2S_TX_HUNG_INT_ST_V 0x1
+#define I2S_TX_HUNG_INT_ST_S 7
+/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_HUNG_INT_ST (BIT(6))
+#define I2S_RX_HUNG_INT_ST_M (BIT(6))
+#define I2S_RX_HUNG_INT_ST_V 0x1
+#define I2S_RX_HUNG_INT_ST_S 6
+/* I2S_TX_REMPTY_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_REMPTY_INT_ST (BIT(5))
+#define I2S_TX_REMPTY_INT_ST_M (BIT(5))
+#define I2S_TX_REMPTY_INT_ST_V 0x1
+#define I2S_TX_REMPTY_INT_ST_S 5
+/* I2S_TX_WFULL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_WFULL_INT_ST (BIT(4))
+#define I2S_TX_WFULL_INT_ST_M (BIT(4))
+#define I2S_TX_WFULL_INT_ST_V 0x1
+#define I2S_TX_WFULL_INT_ST_S 4
+/* I2S_RX_REMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_REMPTY_INT_ST (BIT(3))
+#define I2S_RX_REMPTY_INT_ST_M (BIT(3))
+#define I2S_RX_REMPTY_INT_ST_V 0x1
+#define I2S_RX_REMPTY_INT_ST_S 3
+/* I2S_RX_WFULL_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_WFULL_INT_ST (BIT(2))
+#define I2S_RX_WFULL_INT_ST_M (BIT(2))
+#define I2S_RX_WFULL_INT_ST_V 0x1
+#define I2S_RX_WFULL_INT_ST_S 2
+/* I2S_TX_PUT_DATA_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_PUT_DATA_INT_ST (BIT(1))
+#define I2S_TX_PUT_DATA_INT_ST_M (BIT(1))
+#define I2S_TX_PUT_DATA_INT_ST_V 0x1
+#define I2S_TX_PUT_DATA_INT_ST_S 1
+/* I2S_RX_TAKE_DATA_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_TAKE_DATA_INT_ST (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_ST_M (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_ST_V 0x1
+#define I2S_RX_TAKE_DATA_INT_ST_S 0
+
+#define I2SINT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014)
+/* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_ENA_M (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_ENA_V 0x1
+#define I2S_OUT_TOTAL_EOF_INT_ENA_S 16
+/* I2S_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_ENA_M (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_ENA_V 0x1
+#define I2S_IN_DSCR_EMPTY_INT_ENA_S 15
+/* I2S_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DSCR_ERR_INT_ENA (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_ENA_M (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_ENA_V 0x1
+#define I2S_OUT_DSCR_ERR_INT_ENA_S 14
+/* I2S_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_ERR_INT_ENA (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_ENA_M (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_ENA_V 0x1
+#define I2S_IN_DSCR_ERR_INT_ENA_S 13
+/* I2S_OUT_EOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_EOF_INT_ENA (BIT(12))
+#define I2S_OUT_EOF_INT_ENA_M (BIT(12))
+#define I2S_OUT_EOF_INT_ENA_V 0x1
+#define I2S_OUT_EOF_INT_ENA_S 12
+/* I2S_OUT_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DONE_INT_ENA (BIT(11))
+#define I2S_OUT_DONE_INT_ENA_M (BIT(11))
+#define I2S_OUT_DONE_INT_ENA_V 0x1
+#define I2S_OUT_DONE_INT_ENA_S 11
+/* I2S_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_ERR_EOF_INT_ENA (BIT(10))
+#define I2S_IN_ERR_EOF_INT_ENA_M (BIT(10))
+#define I2S_IN_ERR_EOF_INT_ENA_V 0x1
+#define I2S_IN_ERR_EOF_INT_ENA_S 10
+/* I2S_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_SUC_EOF_INT_ENA (BIT(9))
+#define I2S_IN_SUC_EOF_INT_ENA_M (BIT(9))
+#define I2S_IN_SUC_EOF_INT_ENA_V 0x1
+#define I2S_IN_SUC_EOF_INT_ENA_S 9
+/* I2S_IN_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DONE_INT_ENA (BIT(8))
+#define I2S_IN_DONE_INT_ENA_M (BIT(8))
+#define I2S_IN_DONE_INT_ENA_V 0x1
+#define I2S_IN_DONE_INT_ENA_S 8
+/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_HUNG_INT_ENA (BIT(7))
+#define I2S_TX_HUNG_INT_ENA_M (BIT(7))
+#define I2S_TX_HUNG_INT_ENA_V 0x1
+#define I2S_TX_HUNG_INT_ENA_S 7
+/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_HUNG_INT_ENA (BIT(6))
+#define I2S_RX_HUNG_INT_ENA_M (BIT(6))
+#define I2S_RX_HUNG_INT_ENA_V 0x1
+#define I2S_RX_HUNG_INT_ENA_S 6
+/* I2S_TX_REMPTY_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_REMPTY_INT_ENA (BIT(5))
+#define I2S_TX_REMPTY_INT_ENA_M (BIT(5))
+#define I2S_TX_REMPTY_INT_ENA_V 0x1
+#define I2S_TX_REMPTY_INT_ENA_S 5
+/* I2S_TX_WFULL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_WFULL_INT_ENA (BIT(4))
+#define I2S_TX_WFULL_INT_ENA_M (BIT(4))
+#define I2S_TX_WFULL_INT_ENA_V 0x1
+#define I2S_TX_WFULL_INT_ENA_S 4
+/* I2S_RX_REMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_REMPTY_INT_ENA (BIT(3))
+#define I2S_RX_REMPTY_INT_ENA_M (BIT(3))
+#define I2S_RX_REMPTY_INT_ENA_V 0x1
+#define I2S_RX_REMPTY_INT_ENA_S 3
+/* I2S_RX_WFULL_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_WFULL_INT_ENA (BIT(2))
+#define I2S_RX_WFULL_INT_ENA_M (BIT(2))
+#define I2S_RX_WFULL_INT_ENA_V 0x1
+#define I2S_RX_WFULL_INT_ENA_S 2
+/* I2S_TX_PUT_DATA_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_PUT_DATA_INT_ENA (BIT(1))
+#define I2S_TX_PUT_DATA_INT_ENA_M (BIT(1))
+#define I2S_TX_PUT_DATA_INT_ENA_V 0x1
+#define I2S_TX_PUT_DATA_INT_ENA_S 1
+/* I2S_RX_TAKE_DATA_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_ENA_M (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_ENA_V 0x1
+#define I2S_RX_TAKE_DATA_INT_ENA_S 0
+
+#define I2SINT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018)
+/* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_CLR_M (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_CLR_V 0x1
+#define I2S_OUT_TOTAL_EOF_INT_CLR_S 16
+/* I2S_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_CLR_M (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_CLR_V 0x1
+#define I2S_IN_DSCR_EMPTY_INT_CLR_S 15
+/* I2S_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DSCR_ERR_INT_CLR (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_CLR_M (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_CLR_V 0x1
+#define I2S_OUT_DSCR_ERR_INT_CLR_S 14
+/* I2S_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_ERR_INT_CLR (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_CLR_M (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_CLR_V 0x1
+#define I2S_IN_DSCR_ERR_INT_CLR_S 13
+/* I2S_OUT_EOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_EOF_INT_CLR (BIT(12))
+#define I2S_OUT_EOF_INT_CLR_M (BIT(12))
+#define I2S_OUT_EOF_INT_CLR_V 0x1
+#define I2S_OUT_EOF_INT_CLR_S 12
+/* I2S_OUT_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DONE_INT_CLR (BIT(11))
+#define I2S_OUT_DONE_INT_CLR_M (BIT(11))
+#define I2S_OUT_DONE_INT_CLR_V 0x1
+#define I2S_OUT_DONE_INT_CLR_S 11
+/* I2S_IN_ERR_EOF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_ERR_EOF_INT_CLR (BIT(10))
+#define I2S_IN_ERR_EOF_INT_CLR_M (BIT(10))
+#define I2S_IN_ERR_EOF_INT_CLR_V 0x1
+#define I2S_IN_ERR_EOF_INT_CLR_S 10
+/* I2S_IN_SUC_EOF_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_SUC_EOF_INT_CLR (BIT(9))
+#define I2S_IN_SUC_EOF_INT_CLR_M (BIT(9))
+#define I2S_IN_SUC_EOF_INT_CLR_V 0x1
+#define I2S_IN_SUC_EOF_INT_CLR_S 9
+/* I2S_IN_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_DONE_INT_CLR (BIT(8))
+#define I2S_IN_DONE_INT_CLR_M (BIT(8))
+#define I2S_IN_DONE_INT_CLR_V 0x1
+#define I2S_IN_DONE_INT_CLR_S 8
+/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_HUNG_INT_CLR (BIT(7))
+#define I2S_TX_HUNG_INT_CLR_M (BIT(7))
+#define I2S_TX_HUNG_INT_CLR_V 0x1
+#define I2S_TX_HUNG_INT_CLR_S 7
+/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_HUNG_INT_CLR (BIT(6))
+#define I2S_RX_HUNG_INT_CLR_M (BIT(6))
+#define I2S_RX_HUNG_INT_CLR_V 0x1
+#define I2S_RX_HUNG_INT_CLR_S 6
+/* I2S_TX_REMPTY_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_REMPTY_INT_CLR (BIT(5))
+#define I2S_TX_REMPTY_INT_CLR_M (BIT(5))
+#define I2S_TX_REMPTY_INT_CLR_V 0x1
+#define I2S_TX_REMPTY_INT_CLR_S 5
+/* I2S_TX_WFULL_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_WFULL_INT_CLR (BIT(4))
+#define I2S_TX_WFULL_INT_CLR_M (BIT(4))
+#define I2S_TX_WFULL_INT_CLR_V 0x1
+#define I2S_TX_WFULL_INT_CLR_S 4
+/* I2S_RX_REMPTY_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_REMPTY_INT_CLR (BIT(3))
+#define I2S_RX_REMPTY_INT_CLR_M (BIT(3))
+#define I2S_RX_REMPTY_INT_CLR_V 0x1
+#define I2S_RX_REMPTY_INT_CLR_S 3
+/* I2S_RX_WFULL_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_WFULL_INT_CLR (BIT(2))
+#define I2S_RX_WFULL_INT_CLR_M (BIT(2))
+#define I2S_RX_WFULL_INT_CLR_V 0x1
+#define I2S_RX_WFULL_INT_CLR_S 2
+/* I2S_PUT_DATA_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define I2S_PUT_DATA_INT_CLR (BIT(1))
+#define I2S_PUT_DATA_INT_CLR_M (BIT(1))
+#define I2S_PUT_DATA_INT_CLR_V 0x1
+#define I2S_PUT_DATA_INT_CLR_S 1
+/* I2S_TAKE_DATA_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TAKE_DATA_INT_CLR (BIT(0))
+#define I2S_TAKE_DATA_INT_CLR_M (BIT(0))
+#define I2S_TAKE_DATA_INT_CLR_V 0x1
+#define I2S_TAKE_DATA_INT_CLR_S 0
+
+#define I2STIMING_REG(i) (REG_I2S_BASE(i) + 0x001c)
+/* I2S_TX_BCK_IN_INV : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_BCK_IN_INV (BIT(24))
+#define I2S_TX_BCK_IN_INV_M (BIT(24))
+#define I2S_TX_BCK_IN_INV_V 0x1
+#define I2S_TX_BCK_IN_INV_S 24
+/* I2S_DATA_ENABLE_DELAY : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: */
+#define I2S_DATA_ENABLE_DELAY 0x00000003
+#define I2S_DATA_ENABLE_DELAY_M ((I2S_DATA_ENABLE_DELAY_V)<<(I2S_DATA_ENABLE_DELAY_S))
+#define I2S_DATA_ENABLE_DELAY_V 0x3
+#define I2S_DATA_ENABLE_DELAY_S 22
+/* I2S_RX_DSYNC_SW : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_DSYNC_SW (BIT(21))
+#define I2S_RX_DSYNC_SW_M (BIT(21))
+#define I2S_RX_DSYNC_SW_V 0x1
+#define I2S_RX_DSYNC_SW_S 21
+/* I2S_TX_DSYNC_SW : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_DSYNC_SW (BIT(20))
+#define I2S_TX_DSYNC_SW_M (BIT(20))
+#define I2S_TX_DSYNC_SW_V 0x1
+#define I2S_TX_DSYNC_SW_S 20
+/* I2S_RX_BCK_OUT_DELAY : R/W ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: */
+#define I2S_RX_BCK_OUT_DELAY 0x00000003
+#define I2S_RX_BCK_OUT_DELAY_M ((I2S_RX_BCK_OUT_DELAY_V)<<(I2S_RX_BCK_OUT_DELAY_S))
+#define I2S_RX_BCK_OUT_DELAY_V 0x3
+#define I2S_RX_BCK_OUT_DELAY_S 18
+/* I2S_RX_WS_OUT_DELAY : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: */
+#define I2S_RX_WS_OUT_DELAY 0x00000003
+#define I2S_RX_WS_OUT_DELAY_M ((I2S_RX_WS_OUT_DELAY_V)<<(I2S_RX_WS_OUT_DELAY_S))
+#define I2S_RX_WS_OUT_DELAY_V 0x3
+#define I2S_RX_WS_OUT_DELAY_S 16
+/* I2S_TX_SD_OUT_DELAY : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: */
+#define I2S_TX_SD_OUT_DELAY 0x00000003
+#define I2S_TX_SD_OUT_DELAY_M ((I2S_TX_SD_OUT_DELAY_V)<<(I2S_TX_SD_OUT_DELAY_S))
+#define I2S_TX_SD_OUT_DELAY_V 0x3
+#define I2S_TX_SD_OUT_DELAY_S 14
+/* I2S_TX_WS_OUT_DELAY : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define I2S_TX_WS_OUT_DELAY 0x00000003
+#define I2S_TX_WS_OUT_DELAY_M ((I2S_TX_WS_OUT_DELAY_V)<<(I2S_TX_WS_OUT_DELAY_S))
+#define I2S_TX_WS_OUT_DELAY_V 0x3
+#define I2S_TX_WS_OUT_DELAY_S 12
+/* I2S_TX_BCK_OUT_DELAY : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: */
+#define I2S_TX_BCK_OUT_DELAY 0x00000003
+#define I2S_TX_BCK_OUT_DELAY_M ((I2S_TX_BCK_OUT_DELAY_V)<<(I2S_TX_BCK_OUT_DELAY_S))
+#define I2S_TX_BCK_OUT_DELAY_V 0x3
+#define I2S_TX_BCK_OUT_DELAY_S 10
+/* I2S_RX_SD_IN_DELAY : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: */
+#define I2S_RX_SD_IN_DELAY 0x00000003
+#define I2S_RX_SD_IN_DELAY_M ((I2S_RX_SD_IN_DELAY_V)<<(I2S_RX_SD_IN_DELAY_S))
+#define I2S_RX_SD_IN_DELAY_V 0x3
+#define I2S_RX_SD_IN_DELAY_S 8
+/* I2S_RX_WS_IN_DELAY : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: */
+#define I2S_RX_WS_IN_DELAY 0x00000003
+#define I2S_RX_WS_IN_DELAY_M ((I2S_RX_WS_IN_DELAY_V)<<(I2S_RX_WS_IN_DELAY_S))
+#define I2S_RX_WS_IN_DELAY_V 0x3
+#define I2S_RX_WS_IN_DELAY_S 6
+/* I2S_RX_BCK_IN_DELAY : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define I2S_RX_BCK_IN_DELAY 0x00000003
+#define I2S_RX_BCK_IN_DELAY_M ((I2S_RX_BCK_IN_DELAY_V)<<(I2S_RX_BCK_IN_DELAY_S))
+#define I2S_RX_BCK_IN_DELAY_V 0x3
+#define I2S_RX_BCK_IN_DELAY_S 4
+/* I2S_TX_WS_IN_DELAY : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define I2S_TX_WS_IN_DELAY 0x00000003
+#define I2S_TX_WS_IN_DELAY_M ((I2S_TX_WS_IN_DELAY_V)<<(I2S_TX_WS_IN_DELAY_S))
+#define I2S_TX_WS_IN_DELAY_V 0x3
+#define I2S_TX_WS_IN_DELAY_S 2
+/* I2S_TX_BCK_IN_DELAY : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define I2S_TX_BCK_IN_DELAY 0x00000003
+#define I2S_TX_BCK_IN_DELAY_M ((I2S_TX_BCK_IN_DELAY_V)<<(I2S_TX_BCK_IN_DELAY_S))
+#define I2S_TX_BCK_IN_DELAY_V 0x3
+#define I2S_TX_BCK_IN_DELAY_S 0
+
+#define I2S_FIFO_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020)
+/* I2S_RX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_FIFO_MOD_FORCE_EN (BIT(20))
+#define I2S_RX_FIFO_MOD_FORCE_EN_M (BIT(20))
+#define I2S_RX_FIFO_MOD_FORCE_EN_V 0x1
+#define I2S_RX_FIFO_MOD_FORCE_EN_S 20
+/* I2S_TX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_FIFO_MOD_FORCE_EN (BIT(19))
+#define I2S_TX_FIFO_MOD_FORCE_EN_M (BIT(19))
+#define I2S_TX_FIFO_MOD_FORCE_EN_V 0x1
+#define I2S_TX_FIFO_MOD_FORCE_EN_S 19
+/* I2S_RX_FIFO_MOD : R/W ;bitpos:[18:16] ;default: 3'b0 ; */
+/*description: */
+#define I2S_RX_FIFO_MOD 0x00000007
+#define I2S_RX_FIFO_MOD_M ((I2S_RX_FIFO_MOD_V)<<(I2S_RX_FIFO_MOD_S))
+#define I2S_RX_FIFO_MOD_V 0x7
+#define I2S_RX_FIFO_MOD_S 16
+/* I2S_TX_FIFO_MOD : R/W ;bitpos:[15:13] ;default: 3'b0 ; */
+/*description: */
+#define I2S_TX_FIFO_MOD 0x00000007
+#define I2S_TX_FIFO_MOD_M ((I2S_TX_FIFO_MOD_V)<<(I2S_TX_FIFO_MOD_S))
+#define I2S_TX_FIFO_MOD_V 0x7
+#define I2S_TX_FIFO_MOD_S 13
+/* I2S_DSCR_EN : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: */
+#define I2S_DSCR_EN (BIT(12))
+#define I2S_DSCR_EN_M (BIT(12))
+#define I2S_DSCR_EN_V 0x1
+#define I2S_DSCR_EN_S 12
+/* I2S_TX_DATA_NUM : R/W ;bitpos:[11:6] ;default: 6'd32 ; */
+/*description: */
+#define I2S_TX_DATA_NUM 0x0000003F
+#define I2S_TX_DATA_NUM_M ((I2S_TX_DATA_NUM_V)<<(I2S_TX_DATA_NUM_S))
+#define I2S_TX_DATA_NUM_V 0x3F
+#define I2S_TX_DATA_NUM_S 6
+/* I2S_RX_DATA_NUM : R/W ;bitpos:[5:0] ;default: 6'd32 ; */
+/*description: */
+#define I2S_RX_DATA_NUM 0x0000003F
+#define I2S_RX_DATA_NUM_M ((I2S_RX_DATA_NUM_V)<<(I2S_RX_DATA_NUM_S))
+#define I2S_RX_DATA_NUM_V 0x3F
+#define I2S_RX_DATA_NUM_S 0
+
+#define I2SRXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0024)
+/* I2S_RX_EOF_NUM : R/W ;bitpos:[31:0] ;default: 32'd64 ; */
+/*description: */
+#define I2S_RX_EOF_NUM 0xFFFFFFFF
+#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
+#define I2S_RX_EOF_NUM_V 0xFFFFFFFF
+#define I2S_RX_EOF_NUM_S 0
+
+#define I2SCONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0028)
+/* I2S_SIGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define I2S_SIGLE_DATA 0xFFFFFFFF
+#define I2S_SIGLE_DATA_M ((I2S_SIGLE_DATA_V)<<(I2S_SIGLE_DATA_S))
+#define I2S_SIGLE_DATA_V 0xFFFFFFFF
+#define I2S_SIGLE_DATA_S 0
+
+#define I2SCONF_CHAN_REG(i) (REG_I2S_BASE(i) + 0x002c)
+/* I2S_RX_CHAN_MOD : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: */
+#define I2S_RX_CHAN_MOD 0x00000003
+#define I2S_RX_CHAN_MOD_M ((I2S_RX_CHAN_MOD_V)<<(I2S_RX_CHAN_MOD_S))
+#define I2S_RX_CHAN_MOD_V 0x3
+#define I2S_RX_CHAN_MOD_S 3
+/* I2S_TX_CHAN_MOD : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define I2S_TX_CHAN_MOD 0x00000007
+#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S))
+#define I2S_TX_CHAN_MOD_V 0x7
+#define I2S_TX_CHAN_MOD_S 0
+
+#define I2SOUT_LINK_REG(i) (REG_I2S_BASE(i) + 0x0030)
+/* I2S_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define I2S_OUTLINK_PARK (BIT(31))
+#define I2S_OUTLINK_PARK_M (BIT(31))
+#define I2S_OUTLINK_PARK_V 0x1
+#define I2S_OUTLINK_PARK_S 31
+/* I2S_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUTLINK_RESTART (BIT(30))
+#define I2S_OUTLINK_RESTART_M (BIT(30))
+#define I2S_OUTLINK_RESTART_V 0x1
+#define I2S_OUTLINK_RESTART_S 30
+/* I2S_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUTLINK_START (BIT(29))
+#define I2S_OUTLINK_START_M (BIT(29))
+#define I2S_OUTLINK_START_V 0x1
+#define I2S_OUTLINK_START_S 29
+/* I2S_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUTLINK_STOP (BIT(28))
+#define I2S_OUTLINK_STOP_M (BIT(28))
+#define I2S_OUTLINK_STOP_V 0x1
+#define I2S_OUTLINK_STOP_S 28
+/* I2S_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define I2S_OUTLINK_ADDR 0x000FFFFF
+#define I2S_OUTLINK_ADDR_M ((I2S_OUTLINK_ADDR_V)<<(I2S_OUTLINK_ADDR_S))
+#define I2S_OUTLINK_ADDR_V 0xFFFFF
+#define I2S_OUTLINK_ADDR_S 0
+
+#define I2SIN_LINK_REG(i) (REG_I2S_BASE(i) + 0x0034)
+/* I2S_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define I2S_INLINK_PARK (BIT(31))
+#define I2S_INLINK_PARK_M (BIT(31))
+#define I2S_INLINK_PARK_V 0x1
+#define I2S_INLINK_PARK_S 31
+/* I2S_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define I2S_INLINK_RESTART (BIT(30))
+#define I2S_INLINK_RESTART_M (BIT(30))
+#define I2S_INLINK_RESTART_V 0x1
+#define I2S_INLINK_RESTART_S 30
+/* I2S_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define I2S_INLINK_START (BIT(29))
+#define I2S_INLINK_START_M (BIT(29))
+#define I2S_INLINK_START_V 0x1
+#define I2S_INLINK_START_S 29
+/* I2S_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define I2S_INLINK_STOP (BIT(28))
+#define I2S_INLINK_STOP_M (BIT(28))
+#define I2S_INLINK_STOP_V 0x1
+#define I2S_INLINK_STOP_S 28
+/* I2S_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define I2S_INLINK_ADDR 0x000FFFFF
+#define I2S_INLINK_ADDR_M ((I2S_INLINK_ADDR_V)<<(I2S_INLINK_ADDR_S))
+#define I2S_INLINK_ADDR_V 0xFFFFF
+#define I2S_INLINK_ADDR_S 0
+
+#define I2S_OUT_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0038)
+/* I2S_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF
+#define I2S_OUT_EOF_DES_ADDR_M ((I2S_OUT_EOF_DES_ADDR_V)<<(I2S_OUT_EOF_DES_ADDR_S))
+#define I2S_OUT_EOF_DES_ADDR_V 0xFFFFFFFF
+#define I2S_OUT_EOF_DES_ADDR_S 0
+
+#define I2S_IN_EOF_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x003c)
+/* I2S_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
+#define I2S_IN_SUC_EOF_DES_ADDR_M ((I2S_IN_SUC_EOF_DES_ADDR_V)<<(I2S_IN_SUC_EOF_DES_ADDR_S))
+#define I2S_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
+#define I2S_IN_SUC_EOF_DES_ADDR_S 0
+
+#define I2S_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_I2S_BASE(i) + 0x0040)
+/* I2S_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
+#define I2S_OUT_EOF_BFR_DES_ADDR_M ((I2S_OUT_EOF_BFR_DES_ADDR_V)<<(I2S_OUT_EOF_BFR_DES_ADDR_S))
+#define I2S_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF
+#define I2S_OUT_EOF_BFR_DES_ADDR_S 0
+
+#define I2S_AHB_TEST_REG(i) (REG_I2S_BASE(i) + 0x0044)
+/* I2S_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define I2S_AHB_TESTADDR 0x00000003
+#define I2S_AHB_TESTADDR_M ((I2S_AHB_TESTADDR_V)<<(I2S_AHB_TESTADDR_S))
+#define I2S_AHB_TESTADDR_V 0x3
+#define I2S_AHB_TESTADDR_S 4
+/* I2S_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define I2S_AHB_TESTMODE 0x00000007
+#define I2S_AHB_TESTMODE_M ((I2S_AHB_TESTMODE_V)<<(I2S_AHB_TESTMODE_S))
+#define I2S_AHB_TESTMODE_V 0x7
+#define I2S_AHB_TESTMODE_S 0
+
+#define I2S_INLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0048)
+/* I2S_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define I2S_INLINK_DSCR 0xFFFFFFFF
+#define I2S_INLINK_DSCR_M ((I2S_INLINK_DSCR_V)<<(I2S_INLINK_DSCR_S))
+#define I2S_INLINK_DSCR_V 0xFFFFFFFF
+#define I2S_INLINK_DSCR_S 0
+
+#define I2S_INLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x004C)
+/* I2S_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define I2S_INLINK_DSCR_BF0 0xFFFFFFFF
+#define I2S_INLINK_DSCR_BF0_M ((I2S_INLINK_DSCR_BF0_V)<<(I2S_INLINK_DSCR_BF0_S))
+#define I2S_INLINK_DSCR_BF0_V 0xFFFFFFFF
+#define I2S_INLINK_DSCR_BF0_S 0
+
+#define I2S_INLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x0050)
+/* I2S_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define I2S_INLINK_DSCR_BF1 0xFFFFFFFF
+#define I2S_INLINK_DSCR_BF1_M ((I2S_INLINK_DSCR_BF1_V)<<(I2S_INLINK_DSCR_BF1_S))
+#define I2S_INLINK_DSCR_BF1_V 0xFFFFFFFF
+#define I2S_INLINK_DSCR_BF1_S 0
+
+#define I2S_OUTLINK_DSCR_REG(i) (REG_I2S_BASE(i) + 0x0054)
+/* I2S_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define I2S_OUTLINK_DSCR 0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_M ((I2S_OUTLINK_DSCR_V)<<(I2S_OUTLINK_DSCR_S))
+#define I2S_OUTLINK_DSCR_V 0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_S 0
+
+#define I2S_OUTLINK_DSCR_BF0_REG(i) (REG_I2S_BASE(i) + 0x0058)
+/* I2S_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_BF0_M ((I2S_OUTLINK_DSCR_BF0_V)<<(I2S_OUTLINK_DSCR_BF0_S))
+#define I2S_OUTLINK_DSCR_BF0_V 0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_BF0_S 0
+
+#define I2S_OUTLINK_DSCR_BF1_REG(i) (REG_I2S_BASE(i) + 0x005C)
+/* I2S_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_BF1_M ((I2S_OUTLINK_DSCR_BF1_V)<<(I2S_OUTLINK_DSCR_BF1_S))
+#define I2S_OUTLINK_DSCR_BF1_V 0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_BF1_S 0
+
+#define I2S_LC_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060)
+/* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2S_MEM_TRANS_EN (BIT(13))
+#define I2S_MEM_TRANS_EN_M (BIT(13))
+#define I2S_MEM_TRANS_EN_V 0x1
+#define I2S_MEM_TRANS_EN_S 13
+/* I2S_CHECK_OWNER : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define I2S_CHECK_OWNER (BIT(12))
+#define I2S_CHECK_OWNER_M (BIT(12))
+#define I2S_CHECK_OWNER_V 0x1
+#define I2S_CHECK_OWNER_S 12
+/* I2S_OUT_DATA_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_DATA_BURST_EN (BIT(11))
+#define I2S_OUT_DATA_BURST_EN_M (BIT(11))
+#define I2S_OUT_DATA_BURST_EN_V 0x1
+#define I2S_OUT_DATA_BURST_EN_S 11
+/* I2S_INDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2S_INDSCR_BURST_EN (BIT(10))
+#define I2S_INDSCR_BURST_EN_M (BIT(10))
+#define I2S_INDSCR_BURST_EN_V 0x1
+#define I2S_INDSCR_BURST_EN_S 10
+/* I2S_OUTDSCR_BURST_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUTDSCR_BURST_EN (BIT(9))
+#define I2S_OUTDSCR_BURST_EN_M (BIT(9))
+#define I2S_OUTDSCR_BURST_EN_V 0x1
+#define I2S_OUTDSCR_BURST_EN_S 9
+/* I2S_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define I2S_OUT_EOF_MODE (BIT(8))
+#define I2S_OUT_EOF_MODE_M (BIT(8))
+#define I2S_OUT_EOF_MODE_V 0x1
+#define I2S_OUT_EOF_MODE_S 8
+/* I2S_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_NO_RESTART_CLR (BIT(7))
+#define I2S_OUT_NO_RESTART_CLR_M (BIT(7))
+#define I2S_OUT_NO_RESTART_CLR_V 0x1
+#define I2S_OUT_NO_RESTART_CLR_S 7
+/* I2S_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_AUTO_WRBACK (BIT(6))
+#define I2S_OUT_AUTO_WRBACK_M (BIT(6))
+#define I2S_OUT_AUTO_WRBACK_V 0x1
+#define I2S_OUT_AUTO_WRBACK_S 6
+/* I2S_IN_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_LOOP_TEST (BIT(5))
+#define I2S_IN_LOOP_TEST_M (BIT(5))
+#define I2S_IN_LOOP_TEST_V 0x1
+#define I2S_IN_LOOP_TEST_S 5
+/* I2S_OUT_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_LOOP_TEST (BIT(4))
+#define I2S_OUT_LOOP_TEST_M (BIT(4))
+#define I2S_OUT_LOOP_TEST_V 0x1
+#define I2S_OUT_LOOP_TEST_S 4
+/* I2S_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define I2S_AHBM_RST (BIT(3))
+#define I2S_AHBM_RST_M (BIT(3))
+#define I2S_AHBM_RST_V 0x1
+#define I2S_AHBM_RST_S 3
+/* I2S_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define I2S_AHBM_FIFO_RST (BIT(2))
+#define I2S_AHBM_FIFO_RST_M (BIT(2))
+#define I2S_AHBM_FIFO_RST_V 0x1
+#define I2S_AHBM_FIFO_RST_S 2
+/* I2S_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_RST (BIT(1))
+#define I2S_OUT_RST_M (BIT(1))
+#define I2S_OUT_RST_V 0x1
+#define I2S_OUT_RST_S 1
+/* I2S_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define I2S_IN_RST (BIT(0))
+#define I2S_IN_RST_M (BIT(0))
+#define I2S_IN_RST_V 0x1
+#define I2S_IN_RST_S 0
+
+#define I2S_OUTFIFO_PUSH_REG(i) (REG_I2S_BASE(i) + 0x0064)
+/* I2S_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define I2S_OUTFIFO_PUSH (BIT(16))
+#define I2S_OUTFIFO_PUSH_M (BIT(16))
+#define I2S_OUTFIFO_PUSH_V 0x1
+#define I2S_OUTFIFO_PUSH_S 16
+/* I2S_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define I2S_OUTFIFO_WDATA 0x000001FF
+#define I2S_OUTFIFO_WDATA_M ((I2S_OUTFIFO_WDATA_V)<<(I2S_OUTFIFO_WDATA_S))
+#define I2S_OUTFIFO_WDATA_V 0x1FF
+#define I2S_OUTFIFO_WDATA_S 0
+
+#define I2S_INFIFO_POP_REG(i) (REG_I2S_BASE(i) + 0x0068)
+/* I2S_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define I2S_INFIFO_POP (BIT(16))
+#define I2S_INFIFO_POP_M (BIT(16))
+#define I2S_INFIFO_POP_V 0x1
+#define I2S_INFIFO_POP_S 16
+/* I2S_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define I2S_INFIFO_RDATA 0x00000FFF
+#define I2S_INFIFO_RDATA_M ((I2S_INFIFO_RDATA_V)<<(I2S_INFIFO_RDATA_S))
+#define I2S_INFIFO_RDATA_V 0xFFF
+#define I2S_INFIFO_RDATA_S 0
+
+#define I2S_LC_STATE0_REG(i) (REG_I2S_BASE(i) + 0x006C)
+/* I2S_LC_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define I2S_LC_STATE0 0xFFFFFFFF
+#define I2S_LC_STATE0_M ((I2S_LC_STATE0_V)<<(I2S_LC_STATE0_S))
+#define I2S_LC_STATE0_V 0xFFFFFFFF
+#define I2S_LC_STATE0_S 0
+
+#define I2S_LC_STATE1_REG(i) (REG_I2S_BASE(i) + 0x0070)
+/* I2S_LC_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define I2S_LC_STATE1 0xFFFFFFFF
+#define I2S_LC_STATE1_M ((I2S_LC_STATE1_V)<<(I2S_LC_STATE1_S))
+#define I2S_LC_STATE1_V 0xFFFFFFFF
+#define I2S_LC_STATE1_S 0
+
+#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0074)
+/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1
+#define I2S_LC_FIFO_TIMEOUT_ENA_S 11
+/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: */
+#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8
+/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: */
+#define I2S_LC_FIFO_TIMEOUT 0x000000FF
+#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S))
+#define I2S_LC_FIFO_TIMEOUT_V 0xFF
+#define I2S_LC_FIFO_TIMEOUT_S 0
+
+#define I2S_CVSD_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0080)
+/* I2S_CVSD_Y_MIN : R/W ;bitpos:[31:16] ;default: 16'h8000 ; */
+/*description: */
+#define I2S_CVSD_Y_MIN 0x0000FFFF
+#define I2S_CVSD_Y_MIN_M ((I2S_CVSD_Y_MIN_V)<<(I2S_CVSD_Y_MIN_S))
+#define I2S_CVSD_Y_MIN_V 0xFFFF
+#define I2S_CVSD_Y_MIN_S 16
+/* I2S_CVSD_Y_MAX : R/W ;bitpos:[15:0] ;default: 16'h7fff ; */
+/*description: */
+#define I2S_CVSD_Y_MAX 0x0000FFFF
+#define I2S_CVSD_Y_MAX_M ((I2S_CVSD_Y_MAX_V)<<(I2S_CVSD_Y_MAX_S))
+#define I2S_CVSD_Y_MAX_V 0xFFFF
+#define I2S_CVSD_Y_MAX_S 0
+
+#define I2S_CVSD_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0084)
+/* I2S_CVSD_SIGMA_MIN : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
+/*description: */
+#define I2S_CVSD_SIGMA_MIN 0x0000FFFF
+#define I2S_CVSD_SIGMA_MIN_M ((I2S_CVSD_SIGMA_MIN_V)<<(I2S_CVSD_SIGMA_MIN_S))
+#define I2S_CVSD_SIGMA_MIN_V 0xFFFF
+#define I2S_CVSD_SIGMA_MIN_S 16
+/* I2S_CVSD_SIGMA_MAX : R/W ;bitpos:[15:0] ;default: 16'd1280 ; */
+/*description: */
+#define I2S_CVSD_SIGMA_MAX 0x0000FFFF
+#define I2S_CVSD_SIGMA_MAX_M ((I2S_CVSD_SIGMA_MAX_V)<<(I2S_CVSD_SIGMA_MAX_S))
+#define I2S_CVSD_SIGMA_MAX_V 0xFFFF
+#define I2S_CVSD_SIGMA_MAX_S 0
+
+#define I2S_CVSD_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0088)
+/* I2S_CVSD_H : R/W ;bitpos:[18:16] ;default: 3'd5 ; */
+/*description: */
+#define I2S_CVSD_H 0x00000007
+#define I2S_CVSD_H_M ((I2S_CVSD_H_V)<<(I2S_CVSD_H_S))
+#define I2S_CVSD_H_V 0x7
+#define I2S_CVSD_H_S 16
+/* I2S_CVSD_BETA : R/W ;bitpos:[15:6] ;default: 10'd10 ; */
+/*description: */
+#define I2S_CVSD_BETA 0x000003FF
+#define I2S_CVSD_BETA_M ((I2S_CVSD_BETA_V)<<(I2S_CVSD_BETA_S))
+#define I2S_CVSD_BETA_V 0x3FF
+#define I2S_CVSD_BETA_S 6
+/* I2S_CVSD_J : R/W ;bitpos:[5:3] ;default: 3'h4 ; */
+/*description: */
+#define I2S_CVSD_J 0x00000007
+#define I2S_CVSD_J_M ((I2S_CVSD_J_V)<<(I2S_CVSD_J_S))
+#define I2S_CVSD_J_V 0x7
+#define I2S_CVSD_J_S 3
+/* I2S_CVSD_K : R/W ;bitpos:[2:0] ;default: 3'h4 ; */
+/*description: */
+#define I2S_CVSD_K 0x00000007
+#define I2S_CVSD_K_M ((I2S_CVSD_K_V)<<(I2S_CVSD_K_S))
+#define I2S_CVSD_K_V 0x7
+#define I2S_CVSD_K_S 0
+
+#define I2S_PLC_CONF0_REG(i) (REG_I2S_BASE(i) + 0x008C)
+/* I2S_N_MIN_ERR : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
+/*description: */
+#define I2S_N_MIN_ERR 0x00000007
+#define I2S_N_MIN_ERR_M ((I2S_N_MIN_ERR_V)<<(I2S_N_MIN_ERR_S))
+#define I2S_N_MIN_ERR_V 0x7
+#define I2S_N_MIN_ERR_S 25
+/* I2S_PACK_LEN_8K : R/W ;bitpos:[24:20] ;default: 5'd10 ; */
+/*description: */
+#define I2S_PACK_LEN_8K 0x0000001F
+#define I2S_PACK_LEN_8K_M ((I2S_PACK_LEN_8K_V)<<(I2S_PACK_LEN_8K_S))
+#define I2S_PACK_LEN_8K_V 0x1F
+#define I2S_PACK_LEN_8K_S 20
+/* I2S_MAX_SLIDE_SAMPLE : R/W ;bitpos:[19:12] ;default: 8'd128 ; */
+/*description: */
+#define I2S_MAX_SLIDE_SAMPLE 0x000000FF
+#define I2S_MAX_SLIDE_SAMPLE_M ((I2S_MAX_SLIDE_SAMPLE_V)<<(I2S_MAX_SLIDE_SAMPLE_S))
+#define I2S_MAX_SLIDE_SAMPLE_V 0xFF
+#define I2S_MAX_SLIDE_SAMPLE_S 12
+/* I2S_SHIFT_RATE : R/W ;bitpos:[11:9] ;default: 3'h1 ; */
+/*description: */
+#define I2S_SHIFT_RATE 0x00000007
+#define I2S_SHIFT_RATE_M ((I2S_SHIFT_RATE_V)<<(I2S_SHIFT_RATE_S))
+#define I2S_SHIFT_RATE_V 0x7
+#define I2S_SHIFT_RATE_S 9
+/* I2S_N_ERR_SEG : R/W ;bitpos:[8:6] ;default: 3'h4 ; */
+/*description: */
+#define I2S_N_ERR_SEG 0x00000007
+#define I2S_N_ERR_SEG_M ((I2S_N_ERR_SEG_V)<<(I2S_N_ERR_SEG_S))
+#define I2S_N_ERR_SEG_V 0x7
+#define I2S_N_ERR_SEG_S 6
+/* I2S_GOOD_PACK_MAX : R/W ;bitpos:[5:0] ;default: 6'h39 ; */
+/*description: */
+#define I2S_GOOD_PACK_MAX 0x0000003F
+#define I2S_GOOD_PACK_MAX_M ((I2S_GOOD_PACK_MAX_V)<<(I2S_GOOD_PACK_MAX_S))
+#define I2S_GOOD_PACK_MAX_V 0x3F
+#define I2S_GOOD_PACK_MAX_S 0
+
+#define I2S_PLC_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0090)
+/* I2S_SLIDE_WIN_LEN : R/W ;bitpos:[31:24] ;default: 8'd160 ; */
+/*description: */
+#define I2S_SLIDE_WIN_LEN 0x000000FF
+#define I2S_SLIDE_WIN_LEN_M ((I2S_SLIDE_WIN_LEN_V)<<(I2S_SLIDE_WIN_LEN_S))
+#define I2S_SLIDE_WIN_LEN_V 0xFF
+#define I2S_SLIDE_WIN_LEN_S 24
+/* I2S_BAD_OLA_WIN2_PARA : R/W ;bitpos:[23:16] ;default: 8'd23 ; */
+/*description: */
+#define I2S_BAD_OLA_WIN2_PARA 0x000000FF
+#define I2S_BAD_OLA_WIN2_PARA_M ((I2S_BAD_OLA_WIN2_PARA_V)<<(I2S_BAD_OLA_WIN2_PARA_S))
+#define I2S_BAD_OLA_WIN2_PARA_V 0xFF
+#define I2S_BAD_OLA_WIN2_PARA_S 16
+/* I2S_BAD_OLA_WIN2_PARA_SHIFT : R/W ;bitpos:[15:12] ;default: 4'd8 ; */
+/*description: */
+#define I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F
+#define I2S_BAD_OLA_WIN2_PARA_SHIFT_M ((I2S_BAD_OLA_WIN2_PARA_SHIFT_V)<<(I2S_BAD_OLA_WIN2_PARA_SHIFT_S))
+#define I2S_BAD_OLA_WIN2_PARA_SHIFT_V 0xF
+#define I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12
+/* I2S_BAD_CEF_ATTEN_PARA_SHIFT : R/W ;bitpos:[11:8] ;default: 4'd10 ; */
+/*description: */
+#define I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F
+#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_M ((I2S_BAD_CEF_ATTEN_PARA_SHIFT_V)<<(I2S_BAD_CEF_ATTEN_PARA_SHIFT_S))
+#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_V 0xF
+#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8
+/* I2S_BAD_CEF_ATTEN_PARA : R/W ;bitpos:[7:0] ;default: 8'd5 ; */
+/*description: */
+#define I2S_BAD_CEF_ATTEN_PARA 0x000000FF
+#define I2S_BAD_CEF_ATTEN_PARA_M ((I2S_BAD_CEF_ATTEN_PARA_V)<<(I2S_BAD_CEF_ATTEN_PARA_S))
+#define I2S_BAD_CEF_ATTEN_PARA_V 0xFF
+#define I2S_BAD_CEF_ATTEN_PARA_S 0
+
+#define I2S_PLC_CONF2_REG(i) (REG_I2S_BASE(i) + 0x0094)
+/* I2S_MIN_PERIOD : R/W ;bitpos:[6:2] ;default: 5'd10 ; */
+/*description: */
+#define I2S_MIN_PERIOD 0x0000001F
+#define I2S_MIN_PERIOD_M ((I2S_MIN_PERIOD_V)<<(I2S_MIN_PERIOD_S))
+#define I2S_MIN_PERIOD_V 0x1F
+#define I2S_MIN_PERIOD_S 2
+/* I2S_CVSD_SEG_MOD : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define I2S_CVSD_SEG_MOD 0x00000003
+#define I2S_CVSD_SEG_MOD_M ((I2S_CVSD_SEG_MOD_V)<<(I2S_CVSD_SEG_MOD_S))
+#define I2S_CVSD_SEG_MOD_V 0x3
+#define I2S_CVSD_SEG_MOD_S 0
+
+#define I2S_ESCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x0098)
+/* I2S_PLC2DMA_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define I2S_PLC2DMA_EN (BIT(12))
+#define I2S_PLC2DMA_EN_M (BIT(12))
+#define I2S_PLC2DMA_EN_V 0x1
+#define I2S_PLC2DMA_EN_S 12
+/* I2S_PLC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define I2S_PLC_EN (BIT(11))
+#define I2S_PLC_EN_M (BIT(11))
+#define I2S_PLC_EN_V 0x1
+#define I2S_PLC_EN_S 11
+/* I2S_CVSD_DEC_RESET : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2S_CVSD_DEC_RESET (BIT(10))
+#define I2S_CVSD_DEC_RESET_M (BIT(10))
+#define I2S_CVSD_DEC_RESET_V 0x1
+#define I2S_CVSD_DEC_RESET_S 10
+/* I2S_CVSD_DEC_START : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define I2S_CVSD_DEC_START (BIT(9))
+#define I2S_CVSD_DEC_START_M (BIT(9))
+#define I2S_CVSD_DEC_START_V 0x1
+#define I2S_CVSD_DEC_START_S 9
+/* I2S_ESCO_CVSD_INF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define I2S_ESCO_CVSD_INF_EN (BIT(8))
+#define I2S_ESCO_CVSD_INF_EN_M (BIT(8))
+#define I2S_ESCO_CVSD_INF_EN_V 0x1
+#define I2S_ESCO_CVSD_INF_EN_S 8
+/* I2S_ESCO_CVSD_PACK_LEN_8K : R/W ;bitpos:[7:3] ;default: 5'b0 ; */
+/*description: */
+#define I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F
+#define I2S_ESCO_CVSD_PACK_LEN_8K_M ((I2S_ESCO_CVSD_PACK_LEN_8K_V)<<(I2S_ESCO_CVSD_PACK_LEN_8K_S))
+#define I2S_ESCO_CVSD_PACK_LEN_8K_V 0x1F
+#define I2S_ESCO_CVSD_PACK_LEN_8K_S 3
+/* I2S_ESCO_CVSD_DEC_PACK_ERR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2))
+#define I2S_ESCO_CVSD_DEC_PACK_ERR_M (BIT(2))
+#define I2S_ESCO_CVSD_DEC_PACK_ERR_V 0x1
+#define I2S_ESCO_CVSD_DEC_PACK_ERR_S 2
+/* I2S_ESCO_CHAN_MOD : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define I2S_ESCO_CHAN_MOD (BIT(1))
+#define I2S_ESCO_CHAN_MOD_M (BIT(1))
+#define I2S_ESCO_CHAN_MOD_V 0x1
+#define I2S_ESCO_CHAN_MOD_S 1
+/* I2S_ESCO_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define I2S_ESCO_EN (BIT(0))
+#define I2S_ESCO_EN_M (BIT(0))
+#define I2S_ESCO_EN_V 0x1
+#define I2S_ESCO_EN_S 0
+
+#define I2S_SCO_CONF0_REG(i) (REG_I2S_BASE(i) + 0x009c)
+/* I2S_CVSD_ENC_RESET : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: */
+#define I2S_CVSD_ENC_RESET (BIT(3))
+#define I2S_CVSD_ENC_RESET_M (BIT(3))
+#define I2S_CVSD_ENC_RESET_V 0x1
+#define I2S_CVSD_ENC_RESET_S 3
+/* I2S_CVSD_ENC_START : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: */
+#define I2S_CVSD_ENC_START (BIT(2))
+#define I2S_CVSD_ENC_START_M (BIT(2))
+#define I2S_CVSD_ENC_START_V 0x1
+#define I2S_CVSD_ENC_START_S 2
+/* I2S_SCO_NO_I2S_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define I2S_SCO_NO_I2S_EN (BIT(1))
+#define I2S_SCO_NO_I2S_EN_M (BIT(1))
+#define I2S_SCO_NO_I2S_EN_V 0x1
+#define I2S_SCO_NO_I2S_EN_S 1
+/* I2S_SCO_WITH_I2S_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define I2S_SCO_WITH_I2S_EN (BIT(0))
+#define I2S_SCO_WITH_I2S_EN_M (BIT(0))
+#define I2S_SCO_WITH_I2S_EN_V 0x1
+#define I2S_SCO_WITH_I2S_EN_S 0
+
+#define I2SCONF1_REG(i) (REG_I2S_BASE(i) + 0x00a0)
+/* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: */
+#define I2S_TX_ZEROS_RM_EN (BIT(9))
+#define I2S_TX_ZEROS_RM_EN_M (BIT(9))
+#define I2S_TX_ZEROS_RM_EN_V 0x1
+#define I2S_TX_ZEROS_RM_EN_S 9
+/* I2S_TX_STOP_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: */
+#define I2S_TX_STOP_EN (BIT(8))
+#define I2S_TX_STOP_EN_M (BIT(8))
+#define I2S_TX_STOP_EN_V 0x1
+#define I2S_TX_STOP_EN_S 8
+/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[7] ;default: 1'h1 ; */
+/*description: */
+#define I2S_RX_PCM_BYPASS (BIT(7))
+#define I2S_RX_PCM_BYPASS_M (BIT(7))
+#define I2S_RX_PCM_BYPASS_V 0x1
+#define I2S_RX_PCM_BYPASS_S 7
+/* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: */
+#define I2S_RX_PCM_CONF 0x00000007
+#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
+#define I2S_RX_PCM_CONF_V 0x7
+#define I2S_RX_PCM_CONF_S 4
+/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: */
+#define I2S_TX_PCM_BYPASS (BIT(3))
+#define I2S_TX_PCM_BYPASS_M (BIT(3))
+#define I2S_TX_PCM_BYPASS_V 0x1
+#define I2S_TX_PCM_BYPASS_S 3
+/* I2S_TX_PCM_CONF : R/W ;bitpos:[2:0] ;default: 3'h1 ; */
+/*description: */
+#define I2S_TX_PCM_CONF 0x00000007
+#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
+#define I2S_TX_PCM_CONF_V 0x7
+#define I2S_TX_PCM_CONF_S 0
+
+#define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4)
+/* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: */
+#define I2S_PLC_MEM_FORCE_PU (BIT(3))
+#define I2S_PLC_MEM_FORCE_PU_M (BIT(3))
+#define I2S_PLC_MEM_FORCE_PU_V 0x1
+#define I2S_PLC_MEM_FORCE_PU_S 3
+/* I2S_PLC_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define I2S_PLC_MEM_FORCE_PD (BIT(2))
+#define I2S_PLC_MEM_FORCE_PD_M (BIT(2))
+#define I2S_PLC_MEM_FORCE_PD_V 0x1
+#define I2S_PLC_MEM_FORCE_PD_S 2
+/* I2S_FIFO_FORCE_PU : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: */
+#define I2S_FIFO_FORCE_PU (BIT(1))
+#define I2S_FIFO_FORCE_PU_M (BIT(1))
+#define I2S_FIFO_FORCE_PU_V 0x1
+#define I2S_FIFO_FORCE_PU_S 1
+/* I2S_FIFO_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define I2S_FIFO_FORCE_PD (BIT(0))
+#define I2S_FIFO_FORCE_PD_M (BIT(0))
+#define I2S_FIFO_FORCE_PD_V 0x1
+#define I2S_FIFO_FORCE_PD_S 0
+
+#define I2SCONF2_REG(i) (REG_I2S_BASE(i) + 0x00a8)
+/* I2S_INTER_VALID_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define I2S_INTER_VALID_EN (BIT(7))
+#define I2S_INTER_VALID_EN_M (BIT(7))
+#define I2S_INTER_VALID_EN_V 0x1
+#define I2S_INTER_VALID_EN_S 7
+/* I2S_EXT_ADC_START_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define I2S_EXT_ADC_START_EN (BIT(6))
+#define I2S_EXT_ADC_START_EN_M (BIT(6))
+#define I2S_EXT_ADC_START_EN_V 0x1
+#define I2S_EXT_ADC_START_EN_S 6
+/* I2S_LCD_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define I2S_LCD_EN (BIT(5))
+#define I2S_LCD_EN_M (BIT(5))
+#define I2S_LCD_EN_V 0x1
+#define I2S_LCD_EN_S 5
+/* I2S_DATA_ENABLE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: */
+#define I2S_DATA_ENABLE (BIT(4))
+#define I2S_DATA_ENABLE_M (BIT(4))
+#define I2S_DATA_ENABLE_V 0x1
+#define I2S_DATA_ENABLE_S 4
+/* I2S_DATA_ENABLE_TEST_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define I2S_DATA_ENABLE_TEST_EN (BIT(3))
+#define I2S_DATA_ENABLE_TEST_EN_M (BIT(3))
+#define I2S_DATA_ENABLE_TEST_EN_V 0x1
+#define I2S_DATA_ENABLE_TEST_EN_S 3
+/* I2S_LCD_TX_SDX2_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define I2S_LCD_TX_SDX2_EN (BIT(2))
+#define I2S_LCD_TX_SDX2_EN_M (BIT(2))
+#define I2S_LCD_TX_SDX2_EN_V 0x1
+#define I2S_LCD_TX_SDX2_EN_S 2
+/* I2S_LCD_TX_WRX2_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define I2S_LCD_TX_WRX2_EN (BIT(1))
+#define I2S_LCD_TX_WRX2_EN_M (BIT(1))
+#define I2S_LCD_TX_WRX2_EN_V 0x1
+#define I2S_LCD_TX_WRX2_EN_S 1
+/* I2S_CAMERA_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define I2S_CAMERA_EN (BIT(0))
+#define I2S_CAMERA_EN_M (BIT(0))
+#define I2S_CAMERA_EN_V 0x1
+#define I2S_CAMERA_EN_S 0
+
+#define I2S_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00ac)
+/* I2S_CLKA_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define I2S_CLKA_ENA (BIT(21))
+#define I2S_CLKA_ENA_M (BIT(21))
+#define I2S_CLKA_ENA_V 0x1
+#define I2S_CLKA_ENA_S 21
+/* I2S_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define I2S_CLK_EN (BIT(20))
+#define I2S_CLK_EN_M (BIT(20))
+#define I2S_CLK_EN_V 0x1
+#define I2S_CLK_EN_S 20
+/* I2S_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
+/*description: */
+#define I2S_CLKM_DIV_A 0x0000003F
+#define I2S_CLKM_DIV_A_M ((I2S_CLKM_DIV_A_V)<<(I2S_CLKM_DIV_A_S))
+#define I2S_CLKM_DIV_A_V 0x3F
+#define I2S_CLKM_DIV_A_S 14
+/* I2S_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
+/*description: */
+#define I2S_CLKM_DIV_B 0x0000003F
+#define I2S_CLKM_DIV_B_M ((I2S_CLKM_DIV_B_V)<<(I2S_CLKM_DIV_B_S))
+#define I2S_CLKM_DIV_B_V 0x3F
+#define I2S_CLKM_DIV_B_S 8
+/* I2S_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
+/*description: */
+#define I2S_CLKM_DIV_NUM 0x000000FF
+#define I2S_CLKM_DIV_NUM_M ((I2S_CLKM_DIV_NUM_V)<<(I2S_CLKM_DIV_NUM_S))
+#define I2S_CLKM_DIV_NUM_V 0xFF
+#define I2S_CLKM_DIV_NUM_S 0
+
+#define I2S_SAMPLE_RATE_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b0)
+/* I2S_RX_BITS_MOD : R/W ;bitpos:[23:18] ;default: 6'd16 ; */
+/*description: */
+#define I2S_RX_BITS_MOD 0x0000003F
+#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
+#define I2S_RX_BITS_MOD_V 0x3F
+#define I2S_RX_BITS_MOD_S 18
+/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:12] ;default: 6'd16 ; */
+/*description: */
+#define I2S_TX_BITS_MOD 0x0000003F
+#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S))
+#define I2S_TX_BITS_MOD_V 0x3F
+#define I2S_TX_BITS_MOD_S 12
+/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[11:6] ;default: 6'd6 ; */
+/*description: */
+#define I2S_RX_BCK_DIV_NUM 0x0000003F
+#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S))
+#define I2S_RX_BCK_DIV_NUM_V 0x3F
+#define I2S_RX_BCK_DIV_NUM_S 6
+/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[5:0] ;default: 6'd6 ; */
+/*description: */
+#define I2S_TX_BCK_DIV_NUM 0x0000003F
+#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S))
+#define I2S_TX_BCK_DIV_NUM_V 0x3F
+#define I2S_TX_BCK_DIV_NUM_S 0
+
+#define I2S_PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b4)
+/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define I2S_TX_PDM_HP_BYPASS (BIT(25))
+#define I2S_TX_PDM_HP_BYPASS_M (BIT(25))
+#define I2S_TX_PDM_HP_BYPASS_V 0x1
+#define I2S_TX_PDM_HP_BYPASS_S 25
+/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[24] ;default: 1'h1 ; */
+/*description: */
+#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24))
+#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(24))
+#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1
+#define I2S_RX_PDM_SINC_DSR_16_EN_S 24
+/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[23:22] ;default: 2'h1 ; */
+/*description: */
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22
+/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[21:20] ;default: 2'h1 ; */
+/*description: */
+#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003
+#define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
+#define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3
+#define I2S_TX_PDM_SINC_IN_SHIFT_S 20
+/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[19:18] ;default: 2'h1 ; */
+/*description: */
+#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003
+#define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
+#define I2S_TX_PDM_LP_IN_SHIFT_V 0x3
+#define I2S_TX_PDM_LP_IN_SHIFT_S 18
+/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[17:16] ;default: 2'h1 ; */
+/*description: */
+#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003
+#define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
+#define I2S_TX_PDM_HP_IN_SHIFT_V 0x3
+#define I2S_TX_PDM_HP_IN_SHIFT_S 16
+/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define I2S_TX_PDM_PRESCALE 0x000000FF
+#define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
+#define I2S_TX_PDM_PRESCALE_V 0xFF
+#define I2S_TX_PDM_PRESCALE_S 8
+/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[7:4] ;default: 4'h2 ; */
+/*description: */
+#define I2S_TX_PDM_SINC_OSR2 0x0000000F
+#define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
+#define I2S_TX_PDM_SINC_OSR2_V 0xF
+#define I2S_TX_PDM_SINC_OSR2_S 4
+/* I2S_PDM2PCM_CONV_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define I2S_PDM2PCM_CONV_EN (BIT(3))
+#define I2S_PDM2PCM_CONV_EN_M (BIT(3))
+#define I2S_PDM2PCM_CONV_EN_V 0x1
+#define I2S_PDM2PCM_CONV_EN_S 3
+/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define I2S_PCM2PDM_CONV_EN (BIT(2))
+#define I2S_PCM2PDM_CONV_EN_M (BIT(2))
+#define I2S_PCM2PDM_CONV_EN_V 0x1
+#define I2S_PCM2PDM_CONV_EN_S 2
+/* I2S_RX_PDM_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define I2S_RX_PDM_EN (BIT(1))
+#define I2S_RX_PDM_EN_M (BIT(1))
+#define I2S_RX_PDM_EN_V 0x1
+#define I2S_RX_PDM_EN_S 1
+/* I2S_TX_PDM_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define I2S_TX_PDM_EN (BIT(0))
+#define I2S_TX_PDM_EN_M (BIT(0))
+#define I2S_TX_PDM_EN_V 0x1
+#define I2S_TX_PDM_EN_S 0
+
+#define I2S_PDM_FREQ_CONF_REG(i) (REG_I2S_BASE(i) + 0x00b8)
+/* I2S_TX_PDM_FP : R/W ;bitpos:[19:10] ;default: 10'd960 ; */
+/*description: */
+#define I2S_TX_PDM_FP 0x000003FF
+#define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
+#define I2S_TX_PDM_FP_V 0x3FF
+#define I2S_TX_PDM_FP_S 10
+/* I2S_TX_PDM_FS : R/W ;bitpos:[9:0] ;default: 10'd480 ; */
+/*description: */
+#define I2S_TX_PDM_FS 0x000003FF
+#define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
+#define I2S_TX_PDM_FS_V 0x3FF
+#define I2S_TX_PDM_FS_S 0
+
+#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x00bc)
+/* I2S_RX_FIFO_RESET_BACK : RO ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define I2S_RX_FIFO_RESET_BACK (BIT(2))
+#define I2S_RX_FIFO_RESET_BACK_M (BIT(2))
+#define I2S_RX_FIFO_RESET_BACK_V 0x1
+#define I2S_RX_FIFO_RESET_BACK_S 2
+/* I2S_TX_FIFO_RESET_BACK : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define I2S_TX_FIFO_RESET_BACK (BIT(1))
+#define I2S_TX_FIFO_RESET_BACK_M (BIT(1))
+#define I2S_TX_FIFO_RESET_BACK_V 0x1
+#define I2S_TX_FIFO_RESET_BACK_S 1
+/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define I2S_TX_IDLE (BIT(0))
+#define I2S_TX_IDLE_M (BIT(0))
+#define I2S_TX_IDLE_V 0x1
+#define I2S_TX_IDLE_S 0
+
+#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x00fc)
+/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h1604201 ; */
+/*description: */
+#define I2S_I2SDATE 0xFFFFFFFF
+#define I2S_I2SDATE_M ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S))
+#define I2S_I2SDATE_V 0xFFFFFFFF
+#define I2S_I2SDATE_S 0
+
+
+
+
+#endif /*_SOC_I2S_REG_H_ */
+
+
#define MCU_SEL 0x7
#define MCU_SEL_S 12
-
+#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef _SOC_LEDC_REG_H_\r
+#define _SOC_LEDC_REG_H_\r
+\r
+\r
+#include "soc.h"\r
+#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)\r
+/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */\r
+/*description: This bit is clock gating control signal. when software config\r
+ LED_PWM internal registers it controls the register clock.*/\r
+#define LEDC_CLK_EN (BIT(31))\r
+#define LEDC_CLK_EN_M (BIT(31))\r
+#define LEDC_CLK_EN_V 0x1\r
+#define LEDC_CLK_EN_S 31\r
+/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when high speed channel0 is off.*/\r
+#define LEDC_IDLE_LV_HSCH0 (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH0_M (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH0_V 0x1\r
+#define LEDC_IDLE_LV_HSCH0_S 3\r
+/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for high speed channel0*/\r
+#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH0_V 0x1\r
+#define LEDC_SIG_OUT_EN_HSCH0_S 2\r
+/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four high speed timers the two bits are used to select\r
+ one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
+#define LEDC_TIMER_SEL_HSCH0 0x00000003\r
+#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S))\r
+#define LEDC_TIMER_SEL_HSCH0_V 0x3\r
+#define LEDC_TIMER_SEL_HSCH0_S 0\r
+\r
+#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004)\r
+/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
+ by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/\r
+#define LEDC_HPOINT_HSCH0 0x000FFFFF\r
+#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S))\r
+#define LEDC_HPOINT_HSCH0_V 0xFFFFF\r
+#define LEDC_HPOINT_HSCH0_S 0\r
+\r
+#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008)\r
+/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When hstimerx(x=[0\r
+ 3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_HSCH0 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))\r
+#define LEDC_DUTY_HSCH0_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH0_S 0\r
+\r
+#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C)\r
+/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_HSCH0 (BIT(31))\r
+#define LEDC_DUTY_START_HSCH0_M (BIT(31))\r
+#define LEDC_DUTY_START_HSCH0_V 0x1\r
+#define LEDC_DUTY_START_HSCH0_S 31\r
+/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for high speed channel0.*/\r
+#define LEDC_DUTY_INC_HSCH0 (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH0_M (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH0_V 0x1\r
+#define LEDC_DUTY_INC_HSCH0_S 30\r
+/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for high speed channel0.*/\r
+#define LEDC_DUTY_NUM_HSCH0 0x000003FF\r
+#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S))\r
+#define LEDC_DUTY_NUM_HSCH0_V 0x3FF\r
+#define LEDC_DUTY_NUM_HSCH0_S 20\r
+/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_hsch0 cycles for high speed channel0.*/\r
+#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF\r
+#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S))\r
+#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_HSCH0_S 10\r
+/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ high speed channel0.*/\r
+#define LEDC_DUTY_SCALE_HSCH0 0x000003FF\r
+#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S))\r
+#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF\r
+#define LEDC_DUTY_SCALE_HSCH0_S 0\r
+\r
+#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010)\r
+/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for high speed channel0.*/\r
+#define LEDC_DUTY_HSCH0 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))\r
+#define LEDC_DUTY_HSCH0_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH0_S 0\r
+\r
+#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014)\r
+/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when high speed channel1 is off.*/\r
+#define LEDC_IDLE_LV_HSCH1 (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH1_M (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH1_V 0x1\r
+#define LEDC_IDLE_LV_HSCH1_S 3\r
+/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for high speed channel1*/\r
+#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH1_V 0x1\r
+#define LEDC_SIG_OUT_EN_HSCH1_S 2\r
+/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four high speed timers the two bits are used to select\r
+ one of them for high speed channel1. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
+#define LEDC_TIMER_SEL_HSCH1 0x00000003\r
+#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S))\r
+#define LEDC_TIMER_SEL_HSCH1_V 0x3\r
+#define LEDC_TIMER_SEL_HSCH1_S 0\r
+\r
+#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018)\r
+/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
+ by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/\r
+#define LEDC_HPOINT_HSCH1 0x000FFFFF\r
+#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S))\r
+#define LEDC_HPOINT_HSCH1_V 0xFFFFF\r
+#define LEDC_HPOINT_HSCH1_S 0\r
+\r
+#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C)\r
+/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When hstimerx(x=[0\r
+ 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_HSCH1 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))\r
+#define LEDC_DUTY_HSCH1_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH1_S 0\r
+\r
+#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020)\r
+/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_HSCH1 (BIT(31))\r
+#define LEDC_DUTY_START_HSCH1_M (BIT(31))\r
+#define LEDC_DUTY_START_HSCH1_V 0x1\r
+#define LEDC_DUTY_START_HSCH1_S 31\r
+/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for high speed channel1.*/\r
+#define LEDC_DUTY_INC_HSCH1 (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH1_M (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH1_V 0x1\r
+#define LEDC_DUTY_INC_HSCH1_S 30\r
+/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for high speed channel1.*/\r
+#define LEDC_DUTY_NUM_HSCH1 0x000003FF\r
+#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S))\r
+#define LEDC_DUTY_NUM_HSCH1_V 0x3FF\r
+#define LEDC_DUTY_NUM_HSCH1_S 20\r
+/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_hsch1 cycles for high speed channel1.*/\r
+#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF\r
+#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S))\r
+#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_HSCH1_S 10\r
+/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ high speed channel1.*/\r
+#define LEDC_DUTY_SCALE_HSCH1 0x000003FF\r
+#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S))\r
+#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF\r
+#define LEDC_DUTY_SCALE_HSCH1_S 0\r
+\r
+#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024)\r
+/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for high speed channel1.*/\r
+#define LEDC_DUTY_HSCH1 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))\r
+#define LEDC_DUTY_HSCH1_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH1_S 0\r
+\r
+#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028)\r
+/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when high speed channel2 is off.*/\r
+#define LEDC_IDLE_LV_HSCH2 (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH2_M (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH2_V 0x1\r
+#define LEDC_IDLE_LV_HSCH2_S 3\r
+/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for high speed channel2*/\r
+#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH2_V 0x1\r
+#define LEDC_SIG_OUT_EN_HSCH2_S 2\r
+/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four high speed timers the two bits are used to select\r
+ one of them for high speed channel2. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
+#define LEDC_TIMER_SEL_HSCH2 0x00000003\r
+#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S))\r
+#define LEDC_TIMER_SEL_HSCH2_V 0x3\r
+#define LEDC_TIMER_SEL_HSCH2_S 0\r
+\r
+#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C)\r
+/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
+ by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/\r
+#define LEDC_HPOINT_HSCH2 0x000FFFFF\r
+#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S))\r
+#define LEDC_HPOINT_HSCH2_V 0xFFFFF\r
+#define LEDC_HPOINT_HSCH2_S 0\r
+\r
+#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030)\r
+/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When hstimerx(x=[0\r
+ 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_HSCH2 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))\r
+#define LEDC_DUTY_HSCH2_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH2_S 0\r
+\r
+#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034)\r
+/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_HSCH2 (BIT(31))\r
+#define LEDC_DUTY_START_HSCH2_M (BIT(31))\r
+#define LEDC_DUTY_START_HSCH2_V 0x1\r
+#define LEDC_DUTY_START_HSCH2_S 31\r
+/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for high speed channel2.*/\r
+#define LEDC_DUTY_INC_HSCH2 (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH2_M (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH2_V 0x1\r
+#define LEDC_DUTY_INC_HSCH2_S 30\r
+/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for high speed channel2.*/\r
+#define LEDC_DUTY_NUM_HSCH2 0x000003FF\r
+#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S))\r
+#define LEDC_DUTY_NUM_HSCH2_V 0x3FF\r
+#define LEDC_DUTY_NUM_HSCH2_S 20\r
+/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_hsch2 cycles for high speed channel2.*/\r
+#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF\r
+#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S))\r
+#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_HSCH2_S 10\r
+/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ high speed channel2.*/\r
+#define LEDC_DUTY_SCALE_HSCH2 0x000003FF\r
+#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S))\r
+#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF\r
+#define LEDC_DUTY_SCALE_HSCH2_S 0\r
+\r
+#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038)\r
+/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for high speed channel2.*/\r
+#define LEDC_DUTY_HSCH2 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))\r
+#define LEDC_DUTY_HSCH2_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH2_S 0\r
+\r
+#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C)\r
+/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when high speed channel3 is off.*/\r
+#define LEDC_IDLE_LV_HSCH3 (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH3_M (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH3_V 0x1\r
+#define LEDC_IDLE_LV_HSCH3_S 3\r
+/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for high speed channel3*/\r
+#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH3_V 0x1\r
+#define LEDC_SIG_OUT_EN_HSCH3_S 2\r
+/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four high speed timers the two bits are used to select\r
+ one of them for high speed channel3. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
+#define LEDC_TIMER_SEL_HSCH3 0x00000003\r
+#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S))\r
+#define LEDC_TIMER_SEL_HSCH3_V 0x3\r
+#define LEDC_TIMER_SEL_HSCH3_S 0\r
+\r
+#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040)\r
+/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
+ by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/\r
+#define LEDC_HPOINT_HSCH3 0x000FFFFF\r
+#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S))\r
+#define LEDC_HPOINT_HSCH3_V 0xFFFFF\r
+#define LEDC_HPOINT_HSCH3_S 0\r
+\r
+#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044)\r
+/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When hstimerx(x=[0\r
+ 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_HSCH3 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))\r
+#define LEDC_DUTY_HSCH3_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH3_S 0\r
+\r
+#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048)\r
+/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_HSCH3 (BIT(31))\r
+#define LEDC_DUTY_START_HSCH3_M (BIT(31))\r
+#define LEDC_DUTY_START_HSCH3_V 0x1\r
+#define LEDC_DUTY_START_HSCH3_S 31\r
+/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for high speed channel3.*/\r
+#define LEDC_DUTY_INC_HSCH3 (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH3_M (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH3_V 0x1\r
+#define LEDC_DUTY_INC_HSCH3_S 30\r
+/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for high speed channel3.*/\r
+#define LEDC_DUTY_NUM_HSCH3 0x000003FF\r
+#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S))\r
+#define LEDC_DUTY_NUM_HSCH3_V 0x3FF\r
+#define LEDC_DUTY_NUM_HSCH3_S 20\r
+/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_hsch3 cycles for high speed channel3.*/\r
+#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF\r
+#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S))\r
+#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_HSCH3_S 10\r
+/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ high speed channel3.*/\r
+#define LEDC_DUTY_SCALE_HSCH3 0x000003FF\r
+#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S))\r
+#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF\r
+#define LEDC_DUTY_SCALE_HSCH3_S 0\r
+\r
+#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C)\r
+/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for high speed channel3.*/\r
+#define LEDC_DUTY_HSCH3 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))\r
+#define LEDC_DUTY_HSCH3_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH3_S 0\r
+\r
+#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050)\r
+/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when high speed channel4 is off.*/\r
+#define LEDC_IDLE_LV_HSCH4 (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH4_M (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH4_V 0x1\r
+#define LEDC_IDLE_LV_HSCH4_S 3\r
+/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for high speed channel4*/\r
+#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH4_V 0x1\r
+#define LEDC_SIG_OUT_EN_HSCH4_S 2\r
+/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four high speed timers the two bits are used to select\r
+ one of them for high speed channel4. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
+#define LEDC_TIMER_SEL_HSCH4 0x00000003\r
+#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S))\r
+#define LEDC_TIMER_SEL_HSCH4_V 0x3\r
+#define LEDC_TIMER_SEL_HSCH4_S 0\r
+\r
+#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054)\r
+/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
+ by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/\r
+#define LEDC_HPOINT_HSCH4 0x000FFFFF\r
+#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S))\r
+#define LEDC_HPOINT_HSCH4_V 0xFFFFF\r
+#define LEDC_HPOINT_HSCH4_S 0\r
+\r
+#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058)\r
+/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When hstimerx(x=[0\r
+ 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_HSCH4 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))\r
+#define LEDC_DUTY_HSCH4_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH4_S 0\r
+\r
+#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C)\r
+/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_HSCH4 (BIT(31))\r
+#define LEDC_DUTY_START_HSCH4_M (BIT(31))\r
+#define LEDC_DUTY_START_HSCH4_V 0x1\r
+#define LEDC_DUTY_START_HSCH4_S 31\r
+/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for high speed channel4.*/\r
+#define LEDC_DUTY_INC_HSCH4 (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH4_M (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH4_V 0x1\r
+#define LEDC_DUTY_INC_HSCH4_S 30\r
+/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for high speed channel1.*/\r
+#define LEDC_DUTY_NUM_HSCH4 0x000003FF\r
+#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S))\r
+#define LEDC_DUTY_NUM_HSCH4_V 0x3FF\r
+#define LEDC_DUTY_NUM_HSCH4_S 20\r
+/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_hsch4 cycles for high speed channel4.*/\r
+#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF\r
+#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S))\r
+#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_HSCH4_S 10\r
+/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ high speed channel4.*/\r
+#define LEDC_DUTY_SCALE_HSCH4 0x000003FF\r
+#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S))\r
+#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF\r
+#define LEDC_DUTY_SCALE_HSCH4_S 0\r
+\r
+#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060)\r
+/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for high speed channel4.*/\r
+#define LEDC_DUTY_HSCH4 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))\r
+#define LEDC_DUTY_HSCH4_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH4_S 0\r
+\r
+#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064)\r
+/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when high speed channel5 is off.*/\r
+#define LEDC_IDLE_LV_HSCH5 (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH5_M (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH5_V 0x1\r
+#define LEDC_IDLE_LV_HSCH5_S 3\r
+/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for high speed channel5.*/\r
+#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH5_V 0x1\r
+#define LEDC_SIG_OUT_EN_HSCH5_S 2\r
+/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four high speed timers the two bits are used to select\r
+ one of them for high speed channel5. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
+#define LEDC_TIMER_SEL_HSCH5 0x00000003\r
+#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S))\r
+#define LEDC_TIMER_SEL_HSCH5_V 0x3\r
+#define LEDC_TIMER_SEL_HSCH5_S 0\r
+\r
+#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068)\r
+/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
+ by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/\r
+#define LEDC_HPOINT_HSCH5 0x000FFFFF\r
+#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S))\r
+#define LEDC_HPOINT_HSCH5_V 0xFFFFF\r
+#define LEDC_HPOINT_HSCH5_S 0\r
+\r
+#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C)\r
+/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When hstimerx(x=[0\r
+ 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_HSCH5 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))\r
+#define LEDC_DUTY_HSCH5_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH5_S 0\r
+\r
+#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070)\r
+/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_HSCH5 (BIT(31))\r
+#define LEDC_DUTY_START_HSCH5_M (BIT(31))\r
+#define LEDC_DUTY_START_HSCH5_V 0x1\r
+#define LEDC_DUTY_START_HSCH5_S 31\r
+/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for high speed channel5.*/\r
+#define LEDC_DUTY_INC_HSCH5 (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH5_M (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH5_V 0x1\r
+#define LEDC_DUTY_INC_HSCH5_S 30\r
+/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for high speed channel5.*/\r
+#define LEDC_DUTY_NUM_HSCH5 0x000003FF\r
+#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S))\r
+#define LEDC_DUTY_NUM_HSCH5_V 0x3FF\r
+#define LEDC_DUTY_NUM_HSCH5_S 20\r
+/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_hsch5 cycles for high speed channel5.*/\r
+#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF\r
+#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S))\r
+#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_HSCH5_S 10\r
+/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ high speed channel5.*/\r
+#define LEDC_DUTY_SCALE_HSCH5 0x000003FF\r
+#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S))\r
+#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF\r
+#define LEDC_DUTY_SCALE_HSCH5_S 0\r
+\r
+#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074)\r
+/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for high speed channel5.*/\r
+#define LEDC_DUTY_HSCH5 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))\r
+#define LEDC_DUTY_HSCH5_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH5_S 0\r
+\r
+#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078)\r
+/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when high speed channel6 is off.*/\r
+#define LEDC_IDLE_LV_HSCH6 (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH6_M (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH6_V 0x1\r
+#define LEDC_IDLE_LV_HSCH6_S 3\r
+/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for high speed channel6*/\r
+#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH6_V 0x1\r
+#define LEDC_SIG_OUT_EN_HSCH6_S 2\r
+/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four high speed timers the two bits are used to select\r
+ one of them for high speed channel6. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
+#define LEDC_TIMER_SEL_HSCH6 0x00000003\r
+#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S))\r
+#define LEDC_TIMER_SEL_HSCH6_V 0x3\r
+#define LEDC_TIMER_SEL_HSCH6_S 0\r
+\r
+#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C)\r
+/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
+ by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/\r
+#define LEDC_HPOINT_HSCH6 0x000FFFFF\r
+#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S))\r
+#define LEDC_HPOINT_HSCH6_V 0xFFFFF\r
+#define LEDC_HPOINT_HSCH6_S 0\r
+\r
+#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080)\r
+/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When hstimerx(x=[0\r
+ 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_HSCH6 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))\r
+#define LEDC_DUTY_HSCH6_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH6_S 0\r
+\r
+#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084)\r
+/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_HSCH6 (BIT(31))\r
+#define LEDC_DUTY_START_HSCH6_M (BIT(31))\r
+#define LEDC_DUTY_START_HSCH6_V 0x1\r
+#define LEDC_DUTY_START_HSCH6_S 31\r
+/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for high speed channel6.*/\r
+#define LEDC_DUTY_INC_HSCH6 (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH6_M (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH6_V 0x1\r
+#define LEDC_DUTY_INC_HSCH6_S 30\r
+/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for high speed channel6.*/\r
+#define LEDC_DUTY_NUM_HSCH6 0x000003FF\r
+#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S))\r
+#define LEDC_DUTY_NUM_HSCH6_V 0x3FF\r
+#define LEDC_DUTY_NUM_HSCH6_S 20\r
+/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_hsch6 cycles for high speed channel6.*/\r
+#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF\r
+#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S))\r
+#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_HSCH6_S 10\r
+/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ high speed channel6.*/\r
+#define LEDC_DUTY_SCALE_HSCH6 0x000003FF\r
+#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S))\r
+#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF\r
+#define LEDC_DUTY_SCALE_HSCH6_S 0\r
+\r
+#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088)\r
+/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for high speed channel6.*/\r
+#define LEDC_DUTY_HSCH6 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))\r
+#define LEDC_DUTY_HSCH6_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH6_S 0\r
+\r
+#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C)\r
+/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when high speed channel7 is off.*/\r
+#define LEDC_IDLE_LV_HSCH7 (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH7_M (BIT(3))\r
+#define LEDC_IDLE_LV_HSCH7_V 0x1\r
+#define LEDC_IDLE_LV_HSCH7_S 3\r
+/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for high speed channel7.*/\r
+#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_HSCH7_V 0x1\r
+#define LEDC_SIG_OUT_EN_HSCH7_S 2\r
+/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four high speed timers the two bits are used to select\r
+ one of them for high speed channel7. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/\r
+#define LEDC_TIMER_SEL_HSCH7 0x00000003\r
+#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S))\r
+#define LEDC_TIMER_SEL_HSCH7_V 0x3\r
+#define LEDC_TIMER_SEL_HSCH7_S 0\r
+\r
+#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090)\r
+/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when htimerx(x=[0 3]) selected\r
+ by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/\r
+#define LEDC_HPOINT_HSCH7 0x000FFFFF\r
+#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S))\r
+#define LEDC_HPOINT_HSCH7_V 0xFFFFF\r
+#define LEDC_HPOINT_HSCH7_S 0\r
+\r
+#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094)\r
+/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When hstimerx(x=[0\r
+ 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_HSCH7 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))\r
+#define LEDC_DUTY_HSCH7_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH7_S 0\r
+\r
+#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098)\r
+/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_HSCH7 (BIT(31))\r
+#define LEDC_DUTY_START_HSCH7_M (BIT(31))\r
+#define LEDC_DUTY_START_HSCH7_V 0x1\r
+#define LEDC_DUTY_START_HSCH7_S 31\r
+/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for high speed channel6.*/\r
+#define LEDC_DUTY_INC_HSCH7 (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH7_M (BIT(30))\r
+#define LEDC_DUTY_INC_HSCH7_V 0x1\r
+#define LEDC_DUTY_INC_HSCH7_S 30\r
+/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for high speed channel6.*/\r
+#define LEDC_DUTY_NUM_HSCH7 0x000003FF\r
+#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S))\r
+#define LEDC_DUTY_NUM_HSCH7_V 0x3FF\r
+#define LEDC_DUTY_NUM_HSCH7_S 20\r
+/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_hsch7 cycles for high speed channel7.*/\r
+#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF\r
+#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S))\r
+#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_HSCH7_S 10\r
+/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ high speed channel7.*/\r
+#define LEDC_DUTY_SCALE_HSCH7 0x000003FF\r
+#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S))\r
+#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF\r
+#define LEDC_DUTY_SCALE_HSCH7_S 0\r
+\r
+#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C)\r
+/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for high speed channel7.*/\r
+#define LEDC_DUTY_HSCH7 0x01FFFFFF\r
+#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))\r
+#define LEDC_DUTY_HSCH7_V 0x1FFFFFF\r
+#define LEDC_DUTY_HSCH7_S 0\r
+\r
+#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0)\r
+/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY\r
+ for low speed channel0.*/\r
+#define LEDC_PARA_UP_LSCH0 (BIT(4))\r
+#define LEDC_PARA_UP_LSCH0_M (BIT(4))\r
+#define LEDC_PARA_UP_LSCH0_V 0x1\r
+#define LEDC_PARA_UP_LSCH0_S 4\r
+/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when low speed channel0 is off.*/\r
+#define LEDC_IDLE_LV_LSCH0 (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH0_M (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH0_V 0x1\r
+#define LEDC_IDLE_LV_LSCH0_S 3\r
+/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for low speed channel0.*/\r
+#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH0_V 0x1\r
+#define LEDC_SIG_OUT_EN_LSCH0_S 2\r
+/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four low speed timers the two bits are used to select\r
+ one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
+#define LEDC_TIMER_SEL_LSCH0 0x00000003\r
+#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))\r
+#define LEDC_TIMER_SEL_LSCH0_V 0x3\r
+#define LEDC_TIMER_SEL_LSCH0_S 0\r
+\r
+#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4)\r
+/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
+ by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/\r
+#define LEDC_HPOINT_LSCH0 0x000FFFFF\r
+#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))\r
+#define LEDC_HPOINT_LSCH0_V 0xFFFFF\r
+#define LEDC_HPOINT_LSCH0_S 0\r
+\r
+#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8)\r
+/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When lstimerx(x=[0\r
+ 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_LSCH0 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))\r
+#define LEDC_DUTY_LSCH0_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH0_S 0\r
+\r
+#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC)\r
+/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_LSCH0 (BIT(31))\r
+#define LEDC_DUTY_START_LSCH0_M (BIT(31))\r
+#define LEDC_DUTY_START_LSCH0_V 0x1\r
+#define LEDC_DUTY_START_LSCH0_S 31\r
+/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for low speed channel6.*/\r
+#define LEDC_DUTY_INC_LSCH0 (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH0_M (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH0_V 0x1\r
+#define LEDC_DUTY_INC_LSCH0_S 30\r
+/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for low speed channel6.*/\r
+#define LEDC_DUTY_NUM_LSCH0 0x000003FF\r
+#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))\r
+#define LEDC_DUTY_NUM_LSCH0_V 0x3FF\r
+#define LEDC_DUTY_NUM_LSCH0_S 20\r
+/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_lsch0 cycles for low speed channel0.*/\r
+#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF\r
+#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))\r
+#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_LSCH0_S 10\r
+/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ low speed channel0.*/\r
+#define LEDC_DUTY_SCALE_LSCH0 0x000003FF\r
+#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))\r
+#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF\r
+#define LEDC_DUTY_SCALE_LSCH0_S 0\r
+\r
+#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0)\r
+/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for low speed channel0.*/\r
+#define LEDC_DUTY_LSCH0 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))\r
+#define LEDC_DUTY_LSCH0_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH0_S 0\r
+\r
+#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4)\r
+/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY\r
+ for low speed channel1.*/\r
+#define LEDC_PARA_UP_LSCH1 (BIT(4))\r
+#define LEDC_PARA_UP_LSCH1_M (BIT(4))\r
+#define LEDC_PARA_UP_LSCH1_V 0x1\r
+#define LEDC_PARA_UP_LSCH1_S 4\r
+/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when low speed channel1 is off.*/\r
+#define LEDC_IDLE_LV_LSCH1 (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH1_M (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH1_V 0x1\r
+#define LEDC_IDLE_LV_LSCH1_S 3\r
+/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for low speed channel1.*/\r
+#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH1_V 0x1\r
+#define LEDC_SIG_OUT_EN_LSCH1_S 2\r
+/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four low speed timers the two bits are used to select\r
+ one of them for low speed channel1. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
+#define LEDC_TIMER_SEL_LSCH1 0x00000003\r
+#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))\r
+#define LEDC_TIMER_SEL_LSCH1_V 0x3\r
+#define LEDC_TIMER_SEL_LSCH1_S 0\r
+\r
+#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8)\r
+/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
+ by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/\r
+#define LEDC_HPOINT_LSCH1 0x000FFFFF\r
+#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))\r
+#define LEDC_HPOINT_LSCH1_V 0xFFFFF\r
+#define LEDC_HPOINT_LSCH1_S 0\r
+\r
+#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC)\r
+/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When lstimerx(x=[0\r
+ 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_LSCH1 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))\r
+#define LEDC_DUTY_LSCH1_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH1_S 0\r
+\r
+#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0)\r
+/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_LSCH1 (BIT(31))\r
+#define LEDC_DUTY_START_LSCH1_M (BIT(31))\r
+#define LEDC_DUTY_START_LSCH1_V 0x1\r
+#define LEDC_DUTY_START_LSCH1_S 31\r
+/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for low speed channel1.*/\r
+#define LEDC_DUTY_INC_LSCH1 (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH1_M (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH1_V 0x1\r
+#define LEDC_DUTY_INC_LSCH1_S 30\r
+/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for low speed channel1.*/\r
+#define LEDC_DUTY_NUM_LSCH1 0x000003FF\r
+#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))\r
+#define LEDC_DUTY_NUM_LSCH1_V 0x3FF\r
+#define LEDC_DUTY_NUM_LSCH1_S 20\r
+/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_lsch1 cycles for low speed channel1.*/\r
+#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF\r
+#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))\r
+#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_LSCH1_S 10\r
+/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ low speed channel1.*/\r
+#define LEDC_DUTY_SCALE_LSCH1 0x000003FF\r
+#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))\r
+#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF\r
+#define LEDC_DUTY_SCALE_LSCH1_S 0\r
+\r
+#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4)\r
+/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for low speed channel1.*/\r
+#define LEDC_DUTY_LSCH1 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))\r
+#define LEDC_DUTY_LSCH1_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH1_S 0\r
+\r
+#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8)\r
+/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY\r
+ for low speed channel2.*/\r
+#define LEDC_PARA_UP_LSCH2 (BIT(4))\r
+#define LEDC_PARA_UP_LSCH2_M (BIT(4))\r
+#define LEDC_PARA_UP_LSCH2_V 0x1\r
+#define LEDC_PARA_UP_LSCH2_S 4\r
+/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when low speed channel2 is off.*/\r
+#define LEDC_IDLE_LV_LSCH2 (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH2_M (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH2_V 0x1\r
+#define LEDC_IDLE_LV_LSCH2_S 3\r
+/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for low speed channel2.*/\r
+#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH2_V 0x1\r
+#define LEDC_SIG_OUT_EN_LSCH2_S 2\r
+/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four low speed timers the two bits are used to select\r
+ one of them for low speed channel2. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
+#define LEDC_TIMER_SEL_LSCH2 0x00000003\r
+#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))\r
+#define LEDC_TIMER_SEL_LSCH2_V 0x3\r
+#define LEDC_TIMER_SEL_LSCH2_S 0\r
+\r
+#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC)\r
+/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
+ by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/\r
+#define LEDC_HPOINT_LSCH2 0x000FFFFF\r
+#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))\r
+#define LEDC_HPOINT_LSCH2_V 0xFFFFF\r
+#define LEDC_HPOINT_LSCH2_S 0\r
+\r
+#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0)\r
+/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When lstimerx(x=[0\r
+ 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_LSCH2 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))\r
+#define LEDC_DUTY_LSCH2_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH2_S 0\r
+\r
+#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4)\r
+/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_LSCH2 (BIT(31))\r
+#define LEDC_DUTY_START_LSCH2_M (BIT(31))\r
+#define LEDC_DUTY_START_LSCH2_V 0x1\r
+#define LEDC_DUTY_START_LSCH2_S 31\r
+/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for low speed channel2.*/\r
+#define LEDC_DUTY_INC_LSCH2 (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH2_M (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH2_V 0x1\r
+#define LEDC_DUTY_INC_LSCH2_S 30\r
+/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for low speed channel2.*/\r
+#define LEDC_DUTY_NUM_LSCH2 0x000003FF\r
+#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))\r
+#define LEDC_DUTY_NUM_LSCH2_V 0x3FF\r
+#define LEDC_DUTY_NUM_LSCH2_S 20\r
+/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_lsch2 cycles for low speed channel2.*/\r
+#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF\r
+#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))\r
+#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_LSCH2_S 10\r
+/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ low speed channel2.*/\r
+#define LEDC_DUTY_SCALE_LSCH2 0x000003FF\r
+#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))\r
+#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF\r
+#define LEDC_DUTY_SCALE_LSCH2_S 0\r
+\r
+#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8)\r
+/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for low speed channel2.*/\r
+#define LEDC_DUTY_LSCH2 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))\r
+#define LEDC_DUTY_LSCH2_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH2_S 0\r
+\r
+#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC)\r
+/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY\r
+ for low speed channel3.*/\r
+#define LEDC_PARA_UP_LSCH3 (BIT(4))\r
+#define LEDC_PARA_UP_LSCH3_M (BIT(4))\r
+#define LEDC_PARA_UP_LSCH3_V 0x1\r
+#define LEDC_PARA_UP_LSCH3_S 4\r
+/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when low speed channel3 is off.*/\r
+#define LEDC_IDLE_LV_LSCH3 (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH3_M (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH3_V 0x1\r
+#define LEDC_IDLE_LV_LSCH3_S 3\r
+/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for low speed channel3.*/\r
+#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH3_V 0x1\r
+#define LEDC_SIG_OUT_EN_LSCH3_S 2\r
+/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four low speed timers the two bits are used to select\r
+ one of them for low speed channel3. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
+#define LEDC_TIMER_SEL_LSCH3 0x00000003\r
+#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))\r
+#define LEDC_TIMER_SEL_LSCH3_V 0x3\r
+#define LEDC_TIMER_SEL_LSCH3_S 0\r
+\r
+#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0)\r
+/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
+ by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/\r
+#define LEDC_HPOINT_LSCH3 0x000FFFFF\r
+#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))\r
+#define LEDC_HPOINT_LSCH3_V 0xFFFFF\r
+#define LEDC_HPOINT_LSCH3_S 0\r
+\r
+#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4)\r
+/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When lstimerx(x=[0\r
+ 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_LSCH3 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))\r
+#define LEDC_DUTY_LSCH3_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH3_S 0\r
+\r
+#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8)\r
+/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_LSCH3 (BIT(31))\r
+#define LEDC_DUTY_START_LSCH3_M (BIT(31))\r
+#define LEDC_DUTY_START_LSCH3_V 0x1\r
+#define LEDC_DUTY_START_LSCH3_S 31\r
+/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for low speed channel3.*/\r
+#define LEDC_DUTY_INC_LSCH3 (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH3_M (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH3_V 0x1\r
+#define LEDC_DUTY_INC_LSCH3_S 30\r
+/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for low speed channel3.*/\r
+#define LEDC_DUTY_NUM_LSCH3 0x000003FF\r
+#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))\r
+#define LEDC_DUTY_NUM_LSCH3_V 0x3FF\r
+#define LEDC_DUTY_NUM_LSCH3_S 20\r
+/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_lsch3 cycles for low speed channel3.*/\r
+#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF\r
+#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))\r
+#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_LSCH3_S 10\r
+/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ low speed channel3.*/\r
+#define LEDC_DUTY_SCALE_LSCH3 0x000003FF\r
+#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))\r
+#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF\r
+#define LEDC_DUTY_SCALE_LSCH3_S 0\r
+\r
+#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC)\r
+/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for low speed channel3.*/\r
+#define LEDC_DUTY_LSCH3 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))\r
+#define LEDC_DUTY_LSCH3_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH3_S 0\r
+\r
+#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0)\r
+/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY\r
+ for low speed channel4.*/\r
+#define LEDC_PARA_UP_LSCH4 (BIT(4))\r
+#define LEDC_PARA_UP_LSCH4_M (BIT(4))\r
+#define LEDC_PARA_UP_LSCH4_V 0x1\r
+#define LEDC_PARA_UP_LSCH4_S 4\r
+/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when low speed channel4 is off.*/\r
+#define LEDC_IDLE_LV_LSCH4 (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH4_M (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH4_V 0x1\r
+#define LEDC_IDLE_LV_LSCH4_S 3\r
+/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for low speed channel4.*/\r
+#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH4_V 0x1\r
+#define LEDC_SIG_OUT_EN_LSCH4_S 2\r
+/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four low speed timers the two bits are used to select\r
+ one of them for low speed channel4. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
+#define LEDC_TIMER_SEL_LSCH4 0x00000003\r
+#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))\r
+#define LEDC_TIMER_SEL_LSCH4_V 0x3\r
+#define LEDC_TIMER_SEL_LSCH4_S 0\r
+\r
+#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4)\r
+/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
+ by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/\r
+#define LEDC_HPOINT_LSCH4 0x000FFFFF\r
+#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))\r
+#define LEDC_HPOINT_LSCH4_V 0xFFFFF\r
+#define LEDC_HPOINT_LSCH4_S 0\r
+\r
+#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8)\r
+/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When lstimerx(x=[0\r
+ 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_LSCH4 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))\r
+#define LEDC_DUTY_LSCH4_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH4_S 0\r
+\r
+#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC)\r
+/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_LSCH4 (BIT(31))\r
+#define LEDC_DUTY_START_LSCH4_M (BIT(31))\r
+#define LEDC_DUTY_START_LSCH4_V 0x1\r
+#define LEDC_DUTY_START_LSCH4_S 31\r
+/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for low speed channel4.*/\r
+#define LEDC_DUTY_INC_LSCH4 (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH4_M (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH4_V 0x1\r
+#define LEDC_DUTY_INC_LSCH4_S 30\r
+/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for low speed channel4.*/\r
+#define LEDC_DUTY_NUM_LSCH4 0x000003FF\r
+#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))\r
+#define LEDC_DUTY_NUM_LSCH4_V 0x3FF\r
+#define LEDC_DUTY_NUM_LSCH4_S 20\r
+/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_lsch4 cycles for low speed channel4.*/\r
+#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF\r
+#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))\r
+#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_LSCH4_S 10\r
+/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ low speed channel4.*/\r
+#define LEDC_DUTY_SCALE_LSCH4 0x000003FF\r
+#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))\r
+#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF\r
+#define LEDC_DUTY_SCALE_LSCH4_S 0\r
+\r
+#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100)\r
+/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for low speed channel4.*/\r
+#define LEDC_DUTY_LSCH4 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))\r
+#define LEDC_DUTY_LSCH4_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH4_S 0\r
+\r
+#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104)\r
+/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY\r
+ for low speed channel5.*/\r
+#define LEDC_PARA_UP_LSCH5 (BIT(4))\r
+#define LEDC_PARA_UP_LSCH5_M (BIT(4))\r
+#define LEDC_PARA_UP_LSCH5_V 0x1\r
+#define LEDC_PARA_UP_LSCH5_S 4\r
+/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when low speed channel5 is off.*/\r
+#define LEDC_IDLE_LV_LSCH5 (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH5_M (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH5_V 0x1\r
+#define LEDC_IDLE_LV_LSCH5_S 3\r
+/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for low speed channel5.*/\r
+#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH5_V 0x1\r
+#define LEDC_SIG_OUT_EN_LSCH5_S 2\r
+/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four low speed timers the two bits are used to select\r
+ one of them for low speed channel5. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
+#define LEDC_TIMER_SEL_LSCH5 0x00000003\r
+#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))\r
+#define LEDC_TIMER_SEL_LSCH5_V 0x3\r
+#define LEDC_TIMER_SEL_LSCH5_S 0\r
+\r
+#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108)\r
+/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
+ by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/\r
+#define LEDC_HPOINT_LSCH5 0x000FFFFF\r
+#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))\r
+#define LEDC_HPOINT_LSCH5_V 0xFFFFF\r
+#define LEDC_HPOINT_LSCH5_S 0\r
+\r
+#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C)\r
+/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When lstimerx(x=[0\r
+ 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_LSCH5 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))\r
+#define LEDC_DUTY_LSCH5_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH5_S 0\r
+\r
+#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110)\r
+/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_LSCH5 (BIT(31))\r
+#define LEDC_DUTY_START_LSCH5_M (BIT(31))\r
+#define LEDC_DUTY_START_LSCH5_V 0x1\r
+#define LEDC_DUTY_START_LSCH5_S 31\r
+/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for low speed channel5.*/\r
+#define LEDC_DUTY_INC_LSCH5 (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH5_M (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH5_V 0x1\r
+#define LEDC_DUTY_INC_LSCH5_S 30\r
+/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for low speed channel5.*/\r
+#define LEDC_DUTY_NUM_LSCH5 0x000003FF\r
+#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))\r
+#define LEDC_DUTY_NUM_LSCH5_V 0x3FF\r
+#define LEDC_DUTY_NUM_LSCH5_S 20\r
+/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_lsch5 cycles for low speed channel4.*/\r
+#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF\r
+#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))\r
+#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_LSCH5_S 10\r
+/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ low speed channel5.*/\r
+#define LEDC_DUTY_SCALE_LSCH5 0x000003FF\r
+#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))\r
+#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF\r
+#define LEDC_DUTY_SCALE_LSCH5_S 0\r
+\r
+#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114)\r
+/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for low speed channel5.*/\r
+#define LEDC_DUTY_LSCH5 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))\r
+#define LEDC_DUTY_LSCH5_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH5_S 0\r
+\r
+#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118)\r
+/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY\r
+ for low speed channel6.*/\r
+#define LEDC_PARA_UP_LSCH6 (BIT(4))\r
+#define LEDC_PARA_UP_LSCH6_M (BIT(4))\r
+#define LEDC_PARA_UP_LSCH6_V 0x1\r
+#define LEDC_PARA_UP_LSCH6_S 4\r
+/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when low speed channel6 is off.*/\r
+#define LEDC_IDLE_LV_LSCH6 (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH6_M (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH6_V 0x1\r
+#define LEDC_IDLE_LV_LSCH6_S 3\r
+/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for low speed channel6.*/\r
+#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH6_V 0x1\r
+#define LEDC_SIG_OUT_EN_LSCH6_S 2\r
+/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four low speed timers the two bits are used to select\r
+ one of them for low speed channel6. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
+#define LEDC_TIMER_SEL_LSCH6 0x00000003\r
+#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S))\r
+#define LEDC_TIMER_SEL_LSCH6_V 0x3\r
+#define LEDC_TIMER_SEL_LSCH6_S 0\r
+\r
+#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C)\r
+/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
+ by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/\r
+#define LEDC_HPOINT_LSCH6 0x000FFFFF\r
+#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S))\r
+#define LEDC_HPOINT_LSCH6_V 0xFFFFF\r
+#define LEDC_HPOINT_LSCH6_S 0\r
+\r
+#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120)\r
+/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When lstimerx(x=[0\r
+ 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_LSCH6 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))\r
+#define LEDC_DUTY_LSCH6_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH6_S 0\r
+\r
+#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124)\r
+/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6 and reg_duty_scale_hsch6\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_LSCH6 (BIT(31))\r
+#define LEDC_DUTY_START_LSCH6_M (BIT(31))\r
+#define LEDC_DUTY_START_LSCH6_V 0x1\r
+#define LEDC_DUTY_START_LSCH6_S 31\r
+/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for low speed channel6.*/\r
+#define LEDC_DUTY_INC_LSCH6 (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH6_M (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH6_V 0x1\r
+#define LEDC_DUTY_INC_LSCH6_S 30\r
+/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for low speed channel6.*/\r
+#define LEDC_DUTY_NUM_LSCH6 0x000003FF\r
+#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S))\r
+#define LEDC_DUTY_NUM_LSCH6_V 0x3FF\r
+#define LEDC_DUTY_NUM_LSCH6_S 20\r
+/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_lsch6 cycles for low speed channel6.*/\r
+#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF\r
+#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S))\r
+#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_LSCH6_S 10\r
+/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ low speed channel6.*/\r
+#define LEDC_DUTY_SCALE_LSCH6 0x000003FF\r
+#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S))\r
+#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF\r
+#define LEDC_DUTY_SCALE_LSCH6_S 0\r
+\r
+#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128)\r
+/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for low speed channel6.*/\r
+#define LEDC_DUTY_LSCH6 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))\r
+#define LEDC_DUTY_LSCH6_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH6_S 0\r
+\r
+#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C)\r
+/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY\r
+ for low speed channel7.*/\r
+#define LEDC_PARA_UP_LSCH7 (BIT(4))\r
+#define LEDC_PARA_UP_LSCH7_M (BIT(4))\r
+#define LEDC_PARA_UP_LSCH7_V 0x1\r
+#define LEDC_PARA_UP_LSCH7_S 4\r
+/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This bit is used to control the output value when low speed channel7 is off.*/\r
+#define LEDC_IDLE_LV_LSCH7 (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH7_M (BIT(3))\r
+#define LEDC_IDLE_LV_LSCH7_V 0x1\r
+#define LEDC_IDLE_LV_LSCH7_S 3\r
+/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for low speed channel7.*/\r
+#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2))\r
+#define LEDC_SIG_OUT_EN_LSCH7_V 0x1\r
+#define LEDC_SIG_OUT_EN_LSCH7_S 2\r
+/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */\r
+/*description: There are four low speed timers the two bits are used to select\r
+ one of them for low speed channel7. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/\r
+#define LEDC_TIMER_SEL_LSCH7 0x00000003\r
+#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S))\r
+#define LEDC_TIMER_SEL_LSCH7_V 0x3\r
+#define LEDC_TIMER_SEL_LSCH7_S 0\r
+\r
+#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130)\r
+/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected\r
+ by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/\r
+#define LEDC_HPOINT_LSCH7 0x000FFFFF\r
+#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S))\r
+#define LEDC_HPOINT_LSCH7_V 0xFFFFF\r
+#define LEDC_HPOINT_LSCH7_S 0\r
+\r
+#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134)\r
+/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: The register is used to control output duty. When lstimerx(x=[0\r
+ 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/\r
+#define LEDC_DUTY_LSCH7 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))\r
+#define LEDC_DUTY_LSCH7_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH7_S 0\r
+\r
+#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138)\r
+/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4 and reg_duty_scale_hsch4\r
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/\r
+#define LEDC_DUTY_START_LSCH7 (BIT(31))\r
+#define LEDC_DUTY_START_LSCH7_M (BIT(31))\r
+#define LEDC_DUTY_START_LSCH7_V 0x1\r
+#define LEDC_DUTY_START_LSCH7_S 31\r
+/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */\r
+/*description: This register is used to increase the duty of output signal or\r
+ decrease the duty of output signal for low speed channel4.*/\r
+#define LEDC_DUTY_INC_LSCH7 (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH7_M (BIT(30))\r
+#define LEDC_DUTY_INC_LSCH7_V 0x1\r
+#define LEDC_DUTY_INC_LSCH7_S 30\r
+/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */\r
+/*description: This register is used to control the num of increased or decreased\r
+ times for low speed channel4.*/\r
+#define LEDC_DUTY_NUM_LSCH7 0x000003FF\r
+#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S))\r
+#define LEDC_DUTY_NUM_LSCH7_V 0x3FF\r
+#define LEDC_DUTY_NUM_LSCH7_S 20\r
+/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */\r
+/*description: This register is used to increase or decrease the duty every\r
+ reg_duty_cycle_lsch7 cycles for low speed channel7.*/\r
+#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF\r
+#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S))\r
+#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF\r
+#define LEDC_DUTY_CYCLE_LSCH7_S 10\r
+/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register controls the increase or decrease step scale for\r
+ low speed channel7.*/\r
+#define LEDC_DUTY_SCALE_LSCH7 0x000003FF\r
+#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S))\r
+#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF\r
+#define LEDC_DUTY_SCALE_LSCH7_S 0\r
+\r
+#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C)\r
+/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */\r
+/*description: This register represents the current duty of the output signal\r
+ for low speed channel7.*/\r
+#define LEDC_DUTY_LSCH7 0x01FFFFFF\r
+#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))\r
+#define LEDC_DUTY_LSCH7_V 0x1FFFFFF\r
+#define LEDC_DUTY_LSCH7_S 0\r
+\r
+#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140)\r
+/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: This bit is used to choose apb_clk or ref_tick for high speed\r
+ timer0. 1'b1:apb_clk 0:ref_tick*/\r
+#define LEDC_TICK_SEL_HSTIMER0 (BIT(25))\r
+#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25))\r
+#define LEDC_TICK_SEL_HSTIMER0_V 0x1\r
+#define LEDC_TICK_SEL_HSTIMER0_S 25\r
+/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/\r
+#define LEDC_HSTIMER0_RST (BIT(24))\r
+#define LEDC_HSTIMER0_RST_M (BIT(24))\r
+#define LEDC_HSTIMER0_RST_V 0x1\r
+#define LEDC_HSTIMER0_RST_S 24\r
+/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This bit is used to pause the counter in high speed timer0*/\r
+#define LEDC_HSTIMER0_PAUSE (BIT(23))\r
+#define LEDC_HSTIMER0_PAUSE_M (BIT(23))\r
+#define LEDC_HSTIMER0_PAUSE_V 0x1\r
+#define LEDC_HSTIMER0_PAUSE_S 23\r
+/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
+/*description: This register is used to configure parameter for divider in high\r
+ speed timer0 the least significant eight bits represent the decimal part.*/\r
+#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF\r
+#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S))\r
+#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF\r
+#define LEDC_DIV_NUM_HSTIMER0_S 5\r
+/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
+/*description: This register controls the range of the counter in high speed\r
+ timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/\r
+#define LEDC_HSTIMER0_LIM 0x0000001F\r
+#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S))\r
+#define LEDC_HSTIMER0_LIM_V 0x1F\r
+#define LEDC_HSTIMER0_LIM_S 0\r
+\r
+#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144)\r
+/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: software can read this register to get the current counter value\r
+ in high speed timer0*/\r
+#define LEDC_HSTIMER0_CNT 0x000FFFFF\r
+#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S))\r
+#define LEDC_HSTIMER0_CNT_V 0xFFFFF\r
+#define LEDC_HSTIMER0_CNT_S 0\r
+\r
+#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148)\r
+/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: This bit is used to choose apb_clk or ref_tick for high speed\r
+ timer1. 1'b1:apb_clk 0:ref_tick*/\r
+#define LEDC_TICK_SEL_HSTIMER1 (BIT(25))\r
+#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25))\r
+#define LEDC_TICK_SEL_HSTIMER1_V 0x1\r
+#define LEDC_TICK_SEL_HSTIMER1_S 25\r
+/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/\r
+#define LEDC_HSTIMER1_RST (BIT(24))\r
+#define LEDC_HSTIMER1_RST_M (BIT(24))\r
+#define LEDC_HSTIMER1_RST_V 0x1\r
+#define LEDC_HSTIMER1_RST_S 24\r
+/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This bit is used to pause the counter in high speed timer1*/\r
+#define LEDC_HSTIMER1_PAUSE (BIT(23))\r
+#define LEDC_HSTIMER1_PAUSE_M (BIT(23))\r
+#define LEDC_HSTIMER1_PAUSE_V 0x1\r
+#define LEDC_HSTIMER1_PAUSE_S 23\r
+/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
+/*description: This register is used to configure parameter for divider in high\r
+ speed timer1 the least significant eight bits represent the decimal part.*/\r
+#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF\r
+#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S))\r
+#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF\r
+#define LEDC_DIV_NUM_HSTIMER1_S 5\r
+/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
+/*description: This register controls the range of the counter in high speed\r
+ timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/\r
+#define LEDC_HSTIMER1_LIM 0x0000001F\r
+#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S))\r
+#define LEDC_HSTIMER1_LIM_V 0x1F\r
+#define LEDC_HSTIMER1_LIM_S 0\r
+\r
+#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C)\r
+/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: software can read this register to get the current counter value\r
+ in high speed timer1.*/\r
+#define LEDC_HSTIMER1_CNT 0x000FFFFF\r
+#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S))\r
+#define LEDC_HSTIMER1_CNT_V 0xFFFFF\r
+#define LEDC_HSTIMER1_CNT_S 0\r
+\r
+#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150)\r
+/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: This bit is used to choose apb_clk or ref_tick for high speed\r
+ timer2. 1'b1:apb_clk 0:ref_tick*/\r
+#define LEDC_TICK_SEL_HSTIMER2 (BIT(25))\r
+#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25))\r
+#define LEDC_TICK_SEL_HSTIMER2_V 0x1\r
+#define LEDC_TICK_SEL_HSTIMER2_S 25\r
+/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/\r
+#define LEDC_HSTIMER2_RST (BIT(24))\r
+#define LEDC_HSTIMER2_RST_M (BIT(24))\r
+#define LEDC_HSTIMER2_RST_V 0x1\r
+#define LEDC_HSTIMER2_RST_S 24\r
+/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This bit is used to pause the counter in high speed timer2*/\r
+#define LEDC_HSTIMER2_PAUSE (BIT(23))\r
+#define LEDC_HSTIMER2_PAUSE_M (BIT(23))\r
+#define LEDC_HSTIMER2_PAUSE_V 0x1\r
+#define LEDC_HSTIMER2_PAUSE_S 23\r
+/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
+/*description: This register is used to configure parameter for divider in high\r
+ speed timer2 the least significant eight bits represent the decimal part.*/\r
+#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF\r
+#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S))\r
+#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF\r
+#define LEDC_DIV_NUM_HSTIMER2_S 5\r
+/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
+/*description: This register controls the range of the counter in high speed\r
+ timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/\r
+#define LEDC_HSTIMER2_LIM 0x0000001F\r
+#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S))\r
+#define LEDC_HSTIMER2_LIM_V 0x1F\r
+#define LEDC_HSTIMER2_LIM_S 0\r
+\r
+#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154)\r
+/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: software can read this register to get the current counter value\r
+ in high speed timer2*/\r
+#define LEDC_HSTIMER2_CNT 0x000FFFFF\r
+#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S))\r
+#define LEDC_HSTIMER2_CNT_V 0xFFFFF\r
+#define LEDC_HSTIMER2_CNT_S 0\r
+\r
+#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158)\r
+/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: This bit is used to choose apb_clk or ref_tick for high speed\r
+ timer3. 1'b1:apb_clk 0:ref_tick*/\r
+#define LEDC_TICK_SEL_HSTIMER3 (BIT(25))\r
+#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25))\r
+#define LEDC_TICK_SEL_HSTIMER3_V 0x1\r
+#define LEDC_TICK_SEL_HSTIMER3_S 25\r
+/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/\r
+#define LEDC_HSTIMER3_RST (BIT(24))\r
+#define LEDC_HSTIMER3_RST_M (BIT(24))\r
+#define LEDC_HSTIMER3_RST_V 0x1\r
+#define LEDC_HSTIMER3_RST_S 24\r
+/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This bit is used to pause the counter in high speed timer3*/\r
+#define LEDC_HSTIMER3_PAUSE (BIT(23))\r
+#define LEDC_HSTIMER3_PAUSE_M (BIT(23))\r
+#define LEDC_HSTIMER3_PAUSE_V 0x1\r
+#define LEDC_HSTIMER3_PAUSE_S 23\r
+/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
+/*description: This register is used to configure parameter for divider in high\r
+ speed timer3 the least significant eight bits represent the decimal part.*/\r
+#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF\r
+#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S))\r
+#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF\r
+#define LEDC_DIV_NUM_HSTIMER3_S 5\r
+/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
+/*description: This register controls the range of the counter in high speed\r
+ timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/\r
+#define LEDC_HSTIMER3_LIM 0x0000001F\r
+#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S))\r
+#define LEDC_HSTIMER3_LIM_V 0x1F\r
+#define LEDC_HSTIMER3_LIM_S 0\r
+\r
+#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C)\r
+/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: software can read this register to get the current counter value\r
+ in high speed timer3*/\r
+#define LEDC_HSTIMER3_CNT 0x000FFFFF\r
+#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S))\r
+#define LEDC_HSTIMER3_CNT_V 0xFFFFF\r
+#define LEDC_HSTIMER3_CNT_S 0\r
+\r
+#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160)\r
+/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */\r
+/*description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/\r
+#define LEDC_LSTIMER0_PARA_UP (BIT(26))\r
+#define LEDC_LSTIMER0_PARA_UP_M (BIT(26))\r
+#define LEDC_LSTIMER0_PARA_UP_V 0x1\r
+#define LEDC_LSTIMER0_PARA_UP_S 26\r
+/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: This bit is used to choose slow_clk or ref_tick for low speed\r
+ timer0. 1'b1:slow_clk 0:ref_tick*/\r
+#define LEDC_TICK_SEL_LSTIMER0 (BIT(25))\r
+#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25))\r
+#define LEDC_TICK_SEL_LSTIMER0_V 0x1\r
+#define LEDC_TICK_SEL_LSTIMER0_S 25\r
+/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/\r
+#define LEDC_LSTIMER0_RST (BIT(24))\r
+#define LEDC_LSTIMER0_RST_M (BIT(24))\r
+#define LEDC_LSTIMER0_RST_V 0x1\r
+#define LEDC_LSTIMER0_RST_S 24\r
+/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This bit is used to pause the counter in low speed timer0.*/\r
+#define LEDC_LSTIMER0_PAUSE (BIT(23))\r
+#define LEDC_LSTIMER0_PAUSE_M (BIT(23))\r
+#define LEDC_LSTIMER0_PAUSE_V 0x1\r
+#define LEDC_LSTIMER0_PAUSE_S 23\r
+/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
+/*description: This register is used to configure parameter for divider in low\r
+ speed timer0 the least significant eight bits represent the decimal part.*/\r
+#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF\r
+#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S))\r
+#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF\r
+#define LEDC_DIV_NUM_LSTIMER0_S 5\r
+/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
+/*description: This register controls the range of the counter in low speed\r
+ timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/\r
+#define LEDC_LSTIMER0_LIM 0x0000001F\r
+#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S))\r
+#define LEDC_LSTIMER0_LIM_V 0x1F\r
+#define LEDC_LSTIMER0_LIM_S 0\r
+\r
+#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164)\r
+/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: software can read this register to get the current counter value\r
+ in low speed timer0.*/\r
+#define LEDC_LSTIMER0_CNT 0x000FFFFF\r
+#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))\r
+#define LEDC_LSTIMER0_CNT_V 0xFFFFF\r
+#define LEDC_LSTIMER0_CNT_S 0\r
+\r
+#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168)\r
+/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */\r
+/*description: Set this bit to update reg_div_num_lstime1 and reg_lstimer1_lim.*/\r
+#define LEDC_LSTIMER1_PARA_UP (BIT(26))\r
+#define LEDC_LSTIMER1_PARA_UP_M (BIT(26))\r
+#define LEDC_LSTIMER1_PARA_UP_V 0x1\r
+#define LEDC_LSTIMER1_PARA_UP_S 26\r
+/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: This bit is used to choose slow_clk or ref_tick for low speed\r
+ timer1. 1'b1:slow_clk 0:ref_tick*/\r
+#define LEDC_TICK_SEL_LSTIMER1 (BIT(25))\r
+#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25))\r
+#define LEDC_TICK_SEL_LSTIMER1_V 0x1\r
+#define LEDC_TICK_SEL_LSTIMER1_S 25\r
+/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/\r
+#define LEDC_LSTIMER1_RST (BIT(24))\r
+#define LEDC_LSTIMER1_RST_M (BIT(24))\r
+#define LEDC_LSTIMER1_RST_V 0x1\r
+#define LEDC_LSTIMER1_RST_S 24\r
+/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This bit is used to pause the counter in low speed timer1.*/\r
+#define LEDC_LSTIMER1_PAUSE (BIT(23))\r
+#define LEDC_LSTIMER1_PAUSE_M (BIT(23))\r
+#define LEDC_LSTIMER1_PAUSE_V 0x1\r
+#define LEDC_LSTIMER1_PAUSE_S 23\r
+/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
+/*description: This register is used to configure parameter for divider in low\r
+ speed timer1 the least significant eight bits represent the decimal part.*/\r
+#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF\r
+#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S))\r
+#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF\r
+#define LEDC_DIV_NUM_LSTIMER1_S 5\r
+/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
+/*description: This register controls the range of the counter in low speed\r
+ timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/\r
+#define LEDC_LSTIMER1_LIM 0x0000001F\r
+#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S))\r
+#define LEDC_LSTIMER1_LIM_V 0x1F\r
+#define LEDC_LSTIMER1_LIM_S 0\r
+\r
+#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C)\r
+/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: software can read this register to get the current counter value\r
+ in low speed timer1.*/\r
+#define LEDC_LSTIMER1_CNT 0x000FFFFF\r
+#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))\r
+#define LEDC_LSTIMER1_CNT_V 0xFFFFF\r
+#define LEDC_LSTIMER1_CNT_S 0\r
+\r
+#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170)\r
+/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */\r
+/*description: Set this bit to update reg_div_num_lstime2 and reg_lstimer2_lim.*/\r
+#define LEDC_LSTIMER2_PARA_UP (BIT(26))\r
+#define LEDC_LSTIMER2_PARA_UP_M (BIT(26))\r
+#define LEDC_LSTIMER2_PARA_UP_V 0x1\r
+#define LEDC_LSTIMER2_PARA_UP_S 26\r
+/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: This bit is used to choose slow_clk or ref_tick for low speed\r
+ timer2. 1'b1:slow_clk 0:ref_tick*/\r
+#define LEDC_TICK_SEL_LSTIMER2 (BIT(25))\r
+#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25))\r
+#define LEDC_TICK_SEL_LSTIMER2_V 0x1\r
+#define LEDC_TICK_SEL_LSTIMER2_S 25\r
+/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/\r
+#define LEDC_LSTIMER2_RST (BIT(24))\r
+#define LEDC_LSTIMER2_RST_M (BIT(24))\r
+#define LEDC_LSTIMER2_RST_V 0x1\r
+#define LEDC_LSTIMER2_RST_S 24\r
+/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This bit is used to pause the counter in low speed timer2.*/\r
+#define LEDC_LSTIMER2_PAUSE (BIT(23))\r
+#define LEDC_LSTIMER2_PAUSE_M (BIT(23))\r
+#define LEDC_LSTIMER2_PAUSE_V 0x1\r
+#define LEDC_LSTIMER2_PAUSE_S 23\r
+/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
+/*description: This register is used to configure parameter for divider in low\r
+ speed timer2 the least significant eight bits represent the decimal part.*/\r
+#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF\r
+#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S))\r
+#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF\r
+#define LEDC_DIV_NUM_LSTIMER2_S 5\r
+/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
+/*description: This register controls the range of the counter in low speed\r
+ timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/\r
+#define LEDC_LSTIMER2_LIM 0x0000001F\r
+#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S))\r
+#define LEDC_LSTIMER2_LIM_V 0x1F\r
+#define LEDC_LSTIMER2_LIM_S 0\r
+\r
+#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174)\r
+/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: software can read this register to get the current counter value\r
+ in low speed timer2.*/\r
+#define LEDC_LSTIMER2_CNT 0x000FFFFF\r
+#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))\r
+#define LEDC_LSTIMER2_CNT_V 0xFFFFF\r
+#define LEDC_LSTIMER2_CNT_S 0\r
+\r
+#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178)\r
+/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */\r
+/*description: Set this bit to update reg_div_num_lstime3 and reg_lstimer3_lim.*/\r
+#define LEDC_LSTIMER3_PARA_UP (BIT(26))\r
+#define LEDC_LSTIMER3_PARA_UP_M (BIT(26))\r
+#define LEDC_LSTIMER3_PARA_UP_V 0x1\r
+#define LEDC_LSTIMER3_PARA_UP_S 26\r
+/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: This bit is used to choose slow_clk or ref_tick for low speed\r
+ timer3. 1'b1:slow_clk 0:ref_tick*/\r
+#define LEDC_TICK_SEL_LSTIMER3 (BIT(25))\r
+#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25))\r
+#define LEDC_TICK_SEL_LSTIMER3_V 0x1\r
+#define LEDC_TICK_SEL_LSTIMER3_S 25\r
+/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/\r
+#define LEDC_LSTIMER3_RST (BIT(24))\r
+#define LEDC_LSTIMER3_RST_M (BIT(24))\r
+#define LEDC_LSTIMER3_RST_V 0x1\r
+#define LEDC_LSTIMER3_RST_S 24\r
+/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This bit is used to pause the counter in low speed timer3.*/\r
+#define LEDC_LSTIMER3_PAUSE (BIT(23))\r
+#define LEDC_LSTIMER3_PAUSE_M (BIT(23))\r
+#define LEDC_LSTIMER3_PAUSE_V 0x1\r
+#define LEDC_LSTIMER3_PAUSE_S 23\r
+/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */\r
+/*description: This register is used to configure parameter for divider in low\r
+ speed timer3 the least significant eight bits represent the decimal part.*/\r
+#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF\r
+#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S))\r
+#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF\r
+#define LEDC_DIV_NUM_LSTIMER3_S 5\r
+/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */\r
+/*description: This register controls the range of the counter in low speed\r
+ timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/\r
+#define LEDC_LSTIMER3_LIM 0x0000001F\r
+#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S))\r
+#define LEDC_LSTIMER3_LIM_V 0x1F\r
+#define LEDC_LSTIMER3_LIM_S 0\r
+\r
+#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C)\r
+/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */\r
+/*description: software can read this register to get the current counter value\r
+ in low speed timer3.*/\r
+#define LEDC_LSTIMER3_CNT 0x000FFFFF\r
+#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))\r
+#define LEDC_LSTIMER3_CNT_V 0xFFFFF\r
+#define LEDC_LSTIMER3_CNT_S 0\r
+\r
+#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180)\r
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel 7 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23))\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23))\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23\r
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel 6 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22))\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22))\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22\r
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel 5 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21))\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21))\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21\r
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel 4 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20))\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20))\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20\r
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel 3 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19))\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19))\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19\r
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel 2 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18))\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18))\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18\r
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel 1 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17))\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17))\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17\r
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel 0 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16))\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16))\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16\r
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel 7 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15))\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15))\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15\r
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel 6 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14))\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14))\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14\r
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel 5 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13))\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13))\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13\r
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel 4 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12))\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12))\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12\r
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel 3 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11))\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11))\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11\r
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel 2 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10))\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10))\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10\r
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel 1 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9))\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9))\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9\r
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel 0 duty change done.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8))\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8))\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8\r
+/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel3 counter overflow.*/\r
+#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7))\r
+#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7))\r
+#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1\r
+#define LEDC_LSTIMER3_OVF_INT_RAW_S 7\r
+/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel2 counter overflow.*/\r
+#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6))\r
+#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6))\r
+#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1\r
+#define LEDC_LSTIMER2_OVF_INT_RAW_S 6\r
+/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel1 counter overflow.*/\r
+#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5))\r
+#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5))\r
+#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1\r
+#define LEDC_LSTIMER1_OVF_INT_RAW_S 5\r
+/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for low speed channel0 counter overflow.*/\r
+#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4))\r
+#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4))\r
+#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1\r
+#define LEDC_LSTIMER0_OVF_INT_RAW_S 4\r
+/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel3 counter overflow.*/\r
+#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3))\r
+#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3))\r
+#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1\r
+#define LEDC_HSTIMER3_OVF_INT_RAW_S 3\r
+/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel2 counter overflow.*/\r
+#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2))\r
+#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2))\r
+#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1\r
+#define LEDC_HSTIMER2_OVF_INT_RAW_S 2\r
+/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel1 counter overflow.*/\r
+#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1))\r
+#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1))\r
+#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1\r
+#define LEDC_HSTIMER1_OVF_INT_RAW_S 1\r
+/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for high speed channel0 counter overflow.*/\r
+#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0))\r
+#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0))\r
+#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1\r
+#define LEDC_HSTIMER0_OVF_INT_RAW_S 0\r
+\r
+#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184)\r
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */\r
+/*description: The interrupt status bit for low speed channel 7 duty change done event*/\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23))\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23))\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23\r
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel 6 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22))\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22))\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22\r
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel 5 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21))\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21))\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21\r
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel 4 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20))\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20))\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20\r
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel 3 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19))\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19))\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19\r
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel 2 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18))\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18))\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18\r
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel 1 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17))\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17))\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17\r
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel 0 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16))\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16))\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16\r
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel 7 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15))\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15))\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15\r
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel 6 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14))\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14))\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14\r
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel 5 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13))\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13))\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13\r
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel 4 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12))\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12))\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12\r
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel 3 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11))\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11))\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11\r
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel 2 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10))\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10))\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10\r
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel 1 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9))\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9))\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9\r
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel 0 duty change done event.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8))\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8))\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8\r
+/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel3 counter overflow event.*/\r
+#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7))\r
+#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7))\r
+#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1\r
+#define LEDC_LSTIMER3_OVF_INT_ST_S 7\r
+/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel2 counter overflow event.*/\r
+#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6))\r
+#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6))\r
+#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1\r
+#define LEDC_LSTIMER2_OVF_INT_ST_S 6\r
+/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel1 counter overflow event.*/\r
+#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5))\r
+#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5))\r
+#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1\r
+#define LEDC_LSTIMER1_OVF_INT_ST_S 5\r
+/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for low speed channel0 counter overflow event.*/\r
+#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4))\r
+#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4))\r
+#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1\r
+#define LEDC_LSTIMER0_OVF_INT_ST_S 4\r
+/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel3 counter overflow event.*/\r
+#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3))\r
+#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3))\r
+#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1\r
+#define LEDC_HSTIMER3_OVF_INT_ST_S 3\r
+/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel2 counter overflow event.*/\r
+#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2))\r
+#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2))\r
+#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1\r
+#define LEDC_HSTIMER2_OVF_INT_ST_S 2\r
+/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel1 counter overflow event.*/\r
+#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1))\r
+#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1))\r
+#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1\r
+#define LEDC_HSTIMER1_OVF_INT_ST_S 1\r
+/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The interrupt status bit for high speed channel0 counter overflow event.*/\r
+#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0))\r
+#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0))\r
+#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1\r
+#define LEDC_HSTIMER0_OVF_INT_ST_S 0\r
+\r
+#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188)\r
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */\r
+/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23))\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23))\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23\r
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22))\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22))\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22\r
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21))\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21))\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21\r
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20))\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20))\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20\r
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19))\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19))\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19\r
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18))\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18))\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18\r
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17))\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17))\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17\r
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16))\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16))\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16\r
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15))\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15))\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15\r
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14))\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14))\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14\r
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13))\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13))\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13\r
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12))\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12))\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12\r
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11))\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11))\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11\r
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10))\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10))\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10\r
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9))\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9))\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9\r
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8))\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8))\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8\r
+/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel3 counter overflow interrupt.*/\r
+#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7))\r
+#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7))\r
+#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1\r
+#define LEDC_LSTIMER3_OVF_INT_ENA_S 7\r
+/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel2 counter overflow interrupt.*/\r
+#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6))\r
+#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6))\r
+#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1\r
+#define LEDC_LSTIMER2_OVF_INT_ENA_S 6\r
+/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel1 counter overflow interrupt.*/\r
+#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5))\r
+#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5))\r
+#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1\r
+#define LEDC_LSTIMER1_OVF_INT_ENA_S 5\r
+/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for low speed channel0 counter overflow interrupt.*/\r
+#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4))\r
+#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4))\r
+#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1\r
+#define LEDC_LSTIMER0_OVF_INT_ENA_S 4\r
+/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel3 counter overflow interrupt.*/\r
+#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3))\r
+#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3))\r
+#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1\r
+#define LEDC_HSTIMER3_OVF_INT_ENA_S 3\r
+/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel2 counter overflow interrupt.*/\r
+#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2))\r
+#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2))\r
+#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1\r
+#define LEDC_HSTIMER2_OVF_INT_ENA_S 2\r
+/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel1 counter overflow interrupt.*/\r
+#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1))\r
+#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1))\r
+#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1\r
+#define LEDC_HSTIMER1_OVF_INT_ENA_S 1\r
+/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The interrupt enable bit for high speed channel0 counter overflow interrupt.*/\r
+#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0))\r
+#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0))\r
+#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1\r
+#define LEDC_HSTIMER0_OVF_INT_ENA_S 0\r
+\r
+#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C)\r
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */\r
+/*description: Set this bit to clear low speed channel 7 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23))\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23))\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23\r
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel 6 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22))\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22))\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22\r
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel 5 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21))\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21))\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21\r
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel 4 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20))\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20))\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20\r
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel 3 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19))\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19))\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19\r
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel 2 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18))\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18))\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18\r
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel 1 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17))\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17))\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17\r
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel 0 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16))\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16))\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16\r
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel 7 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15))\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15))\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15\r
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel 6 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14))\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14))\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14\r
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel 5 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13))\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13))\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13\r
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel 4 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12))\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12))\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12\r
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel 3 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11))\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11))\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11\r
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel 2 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10))\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10))\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10\r
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel 1 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9))\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9))\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9\r
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel 0 duty change done interrupt.*/\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8))\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8))\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1\r
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8\r
+/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel3 counter overflow interrupt.*/\r
+#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7))\r
+#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7))\r
+#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1\r
+#define LEDC_LSTIMER3_OVF_INT_CLR_S 7\r
+/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel2 counter overflow interrupt.*/\r
+#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6))\r
+#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6))\r
+#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1\r
+#define LEDC_LSTIMER2_OVF_INT_CLR_S 6\r
+/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel1 counter overflow interrupt.*/\r
+#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5))\r
+#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5))\r
+#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1\r
+#define LEDC_LSTIMER1_OVF_INT_CLR_S 5\r
+/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear low speed channel0 counter overflow interrupt.*/\r
+#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4))\r
+#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4))\r
+#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1\r
+#define LEDC_LSTIMER0_OVF_INT_CLR_S 4\r
+/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel3 counter overflow interrupt.*/\r
+#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3))\r
+#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3))\r
+#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1\r
+#define LEDC_HSTIMER3_OVF_INT_CLR_S 3\r
+/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel2 counter overflow interrupt.*/\r
+#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2))\r
+#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2))\r
+#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1\r
+#define LEDC_HSTIMER2_OVF_INT_CLR_S 2\r
+/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel1 counter overflow interrupt.*/\r
+#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1))\r
+#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1))\r
+#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1\r
+#define LEDC_HSTIMER1_OVF_INT_CLR_S 1\r
+/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear high speed channel0 counter overflow interrupt.*/\r
+#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0))\r
+#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0))\r
+#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1\r
+#define LEDC_HSTIMER0_OVF_INT_CLR_S 0\r
+\r
+#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190)\r
+/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/\r
+#define LEDC_APB_CLK_SEL (BIT(0))\r
+#define LEDC_APB_CLK_SEL_M (BIT(0))\r
+#define LEDC_APB_CLK_SEL_V 0x1\r
+#define LEDC_APB_CLK_SEL_S 0\r
+\r
+#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC)\r
+/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */\r
+/*description: This register represents the version .*/\r
+#define LEDC_DATE 0xFFFFFFFF\r
+#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S))\r
+#define LEDC_DATE_V 0xFFFFFFFF\r
+#define LEDC_DATE_S 0\r
+\r
+\r
+\r
+\r
+#endif /*_SOC_LEDC_REG_H_ */\r
+\r
+\r
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef _SOC_PCNT_REG_H_\r
+#define _SOC_PCNT_REG_H_\r
+\r
+\r
+#include "soc.h"\r
+#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000)\r
+/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's low control\r
+ signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_LCTRL_MODE_U0 0x00000003\r
+#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S))\r
+#define PCNT_CH1_LCTRL_MODE_U0_V 0x3\r
+#define PCNT_CH1_LCTRL_MODE_U0_S 30\r
+/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's high\r
+ control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_HCTRL_MODE_U0 0x00000003\r
+#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S))\r
+#define PCNT_CH1_HCTRL_MODE_U0_V 0x3\r
+#define PCNT_CH1_HCTRL_MODE_U0_S 28\r
+/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH1_POS_MODE_U0 0x00000003\r
+#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S))\r
+#define PCNT_CH1_POS_MODE_U0_V 0x3\r
+#define PCNT_CH1_POS_MODE_U0_S 26\r
+/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH1_NEG_MODE_U0 0x00000003\r
+#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S))\r
+#define PCNT_CH1_NEG_MODE_U0_V 0x3\r
+#define PCNT_CH1_NEG_MODE_U0_S 24\r
+/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's low control\r
+ signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_LCTRL_MODE_U0 0x00000003\r
+#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S))\r
+#define PCNT_CH0_LCTRL_MODE_U0_V 0x3\r
+#define PCNT_CH0_LCTRL_MODE_U0_S 22\r
+/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's high\r
+ control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_HCTRL_MODE_U0 0x00000003\r
+#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S))\r
+#define PCNT_CH0_HCTRL_MODE_U0_V 0x3\r
+#define PCNT_CH0_HCTRL_MODE_U0_S 20\r
+/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH0_POS_MODE_U0 0x00000003\r
+#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S))\r
+#define PCNT_CH0_POS_MODE_U0_V 0x3\r
+#define PCNT_CH0_POS_MODE_U0_S 18\r
+/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH0_NEG_MODE_U0 0x00000003\r
+#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S))\r
+#define PCNT_CH0_NEG_MODE_U0_V 0x3\r
+#define PCNT_CH0_NEG_MODE_U0_S 16\r
+/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit0's count with thres1 value .*/\r
+#define PCNT_THR_THRES1_EN_U0 (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U0_M (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U0_V 0x1\r
+#define PCNT_THR_THRES1_EN_U0_S 15\r
+/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit0's count with thres0 value.*/\r
+#define PCNT_THR_THRES0_EN_U0 (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U0_M (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U0_V 0x1\r
+#define PCNT_THR_THRES0_EN_U0_S 14\r
+/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit0's count with thr_l_lim value.*/\r
+#define PCNT_THR_L_LIM_EN_U0 (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U0_M (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U0_V 0x1\r
+#define PCNT_THR_L_LIM_EN_U0_S 13\r
+/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit0's count with thr_h_lim value.*/\r
+#define PCNT_THR_H_LIM_EN_U0 (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U0_M (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U0_V 0x1\r
+#define PCNT_THR_H_LIM_EN_U0_S 12\r
+/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit0's count with 0 value.*/\r
+#define PCNT_THR_ZERO_EN_U0 (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U0_M (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U0_V 0x1\r
+#define PCNT_THR_ZERO_EN_U0_S 11\r
+/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for filtering input signals for unit0.*/\r
+#define PCNT_FILTER_EN_U0 (BIT(10))\r
+#define PCNT_FILTER_EN_U0_M (BIT(10))\r
+#define PCNT_FILTER_EN_U0_V 0x1\r
+#define PCNT_FILTER_EN_U0_S 10\r
+/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
+/*description: This register is used to filter pluse whose width is smaller\r
+ than this value for unit0.*/\r
+#define PCNT_FILTER_THRES_U0 0x000003FF\r
+#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S))\r
+#define PCNT_FILTER_THRES_U0_V 0x3FF\r
+#define PCNT_FILTER_THRES_U0_S 0\r
+\r
+#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004)\r
+/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres1 value for unit0.*/\r
+#define PCNT_CNT_THRES1_U0 0x0000FFFF\r
+#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S))\r
+#define PCNT_CNT_THRES1_U0_V 0xFFFF\r
+#define PCNT_CNT_THRES1_U0_S 16\r
+/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres0 value for unit0.*/\r
+#define PCNT_CNT_THRES0_U0 0x0000FFFF\r
+#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S))\r
+#define PCNT_CNT_THRES0_U0_V 0xFFFF\r
+#define PCNT_CNT_THRES0_U0_S 0\r
+\r
+#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008)\r
+/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to confiugre thr_l_lim value for unit0.*/\r
+#define PCNT_CNT_L_LIM_U0 0x0000FFFF\r
+#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S))\r
+#define PCNT_CNT_L_LIM_U0_V 0xFFFF\r
+#define PCNT_CNT_L_LIM_U0_S 16\r
+/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thr_h_lim value for unit0.*/\r
+#define PCNT_CNT_H_LIM_U0 0x0000FFFF\r
+#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S))\r
+#define PCNT_CNT_H_LIM_U0_V 0xFFFF\r
+#define PCNT_CNT_H_LIM_U0_S 0\r
+\r
+#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c)\r
+/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's low control\r
+ signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_LCTRL_MODE_U1 0x00000003\r
+#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S))\r
+#define PCNT_CH1_LCTRL_MODE_U1_V 0x3\r
+#define PCNT_CH1_LCTRL_MODE_U1_S 30\r
+/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's high\r
+ control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_HCTRL_MODE_U1 0x00000003\r
+#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S))\r
+#define PCNT_CH1_HCTRL_MODE_U1_V 0x3\r
+#define PCNT_CH1_HCTRL_MODE_U1_S 28\r
+/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH1_POS_MODE_U1 0x00000003\r
+#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S))\r
+#define PCNT_CH1_POS_MODE_U1_V 0x3\r
+#define PCNT_CH1_POS_MODE_U1_S 26\r
+/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH1_NEG_MODE_U1 0x00000003\r
+#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S))\r
+#define PCNT_CH1_NEG_MODE_U1_V 0x3\r
+#define PCNT_CH1_NEG_MODE_U1_S 24\r
+/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's low control\r
+ signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_LCTRL_MODE_U1 0x00000003\r
+#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S))\r
+#define PCNT_CH0_LCTRL_MODE_U1_V 0x3\r
+#define PCNT_CH0_LCTRL_MODE_U1_S 22\r
+/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's high\r
+ control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_HCTRL_MODE_U1 0x00000003\r
+#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S))\r
+#define PCNT_CH0_HCTRL_MODE_U1_V 0x3\r
+#define PCNT_CH0_HCTRL_MODE_U1_S 20\r
+/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH0_POS_MODE_U1 0x00000003\r
+#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S))\r
+#define PCNT_CH0_POS_MODE_U1_V 0x3\r
+#define PCNT_CH0_POS_MODE_U1_S 18\r
+/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH0_NEG_MODE_U1 0x00000003\r
+#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S))\r
+#define PCNT_CH0_NEG_MODE_U1_V 0x3\r
+#define PCNT_CH0_NEG_MODE_U1_S 16\r
+/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit1's count with thres1 value .*/\r
+#define PCNT_THR_THRES1_EN_U1 (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U1_M (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U1_V 0x1\r
+#define PCNT_THR_THRES1_EN_U1_S 15\r
+/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit1's count with thres0 value.*/\r
+#define PCNT_THR_THRES0_EN_U1 (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U1_M (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U1_V 0x1\r
+#define PCNT_THR_THRES0_EN_U1_S 14\r
+/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit1's count with thr_l_lim value.*/\r
+#define PCNT_THR_L_LIM_EN_U1 (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U1_M (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U1_V 0x1\r
+#define PCNT_THR_L_LIM_EN_U1_S 13\r
+/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit1's count with thr_h_lim value.*/\r
+#define PCNT_THR_H_LIM_EN_U1 (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U1_M (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U1_V 0x1\r
+#define PCNT_THR_H_LIM_EN_U1_S 12\r
+/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit1's count with 0 value.*/\r
+#define PCNT_THR_ZERO_EN_U1 (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U1_M (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U1_V 0x1\r
+#define PCNT_THR_ZERO_EN_U1_S 11\r
+/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for filtering input signals for unit1.*/\r
+#define PCNT_FILTER_EN_U1 (BIT(10))\r
+#define PCNT_FILTER_EN_U1_M (BIT(10))\r
+#define PCNT_FILTER_EN_U1_V 0x1\r
+#define PCNT_FILTER_EN_U1_S 10\r
+/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
+/*description: This register is used to filter pluse whose width is smaller\r
+ than this value for unit1.*/\r
+#define PCNT_FILTER_THRES_U1 0x000003FF\r
+#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S))\r
+#define PCNT_FILTER_THRES_U1_V 0x3FF\r
+#define PCNT_FILTER_THRES_U1_S 0\r
+\r
+#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010)\r
+/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres1 value for unit1.*/\r
+#define PCNT_CNT_THRES1_U1 0x0000FFFF\r
+#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S))\r
+#define PCNT_CNT_THRES1_U1_V 0xFFFF\r
+#define PCNT_CNT_THRES1_U1_S 16\r
+/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres0 value for unit1.*/\r
+#define PCNT_CNT_THRES0_U1 0x0000FFFF\r
+#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S))\r
+#define PCNT_CNT_THRES0_U1_V 0xFFFF\r
+#define PCNT_CNT_THRES0_U1_S 0\r
+\r
+#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014)\r
+/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to confiugre thr_l_lim value for unit1.*/\r
+#define PCNT_CNT_L_LIM_U1 0x0000FFFF\r
+#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S))\r
+#define PCNT_CNT_L_LIM_U1_V 0xFFFF\r
+#define PCNT_CNT_L_LIM_U1_S 16\r
+/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thr_h_lim value for unit1.*/\r
+#define PCNT_CNT_H_LIM_U1 0x0000FFFF\r
+#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S))\r
+#define PCNT_CNT_H_LIM_U1_V 0xFFFF\r
+#define PCNT_CNT_H_LIM_U1_S 0\r
+\r
+#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018)\r
+/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's low control\r
+ signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_LCTRL_MODE_U2 0x00000003\r
+#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S))\r
+#define PCNT_CH1_LCTRL_MODE_U2_V 0x3\r
+#define PCNT_CH1_LCTRL_MODE_U2_S 30\r
+/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's high\r
+ control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_HCTRL_MODE_U2 0x00000003\r
+#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S))\r
+#define PCNT_CH1_HCTRL_MODE_U2_V 0x3\r
+#define PCNT_CH1_HCTRL_MODE_U2_S 28\r
+/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH1_POS_MODE_U2 0x00000003\r
+#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S))\r
+#define PCNT_CH1_POS_MODE_U2_V 0x3\r
+#define PCNT_CH1_POS_MODE_U2_S 26\r
+/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH1_NEG_MODE_U2 0x00000003\r
+#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S))\r
+#define PCNT_CH1_NEG_MODE_U2_V 0x3\r
+#define PCNT_CH1_NEG_MODE_U2_S 24\r
+/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's low control\r
+ signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_LCTRL_MODE_U2 0x00000003\r
+#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S))\r
+#define PCNT_CH0_LCTRL_MODE_U2_V 0x3\r
+#define PCNT_CH0_LCTRL_MODE_U2_S 22\r
+/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's high\r
+ control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_HCTRL_MODE_U2 0x00000003\r
+#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S))\r
+#define PCNT_CH0_HCTRL_MODE_U2_V 0x3\r
+#define PCNT_CH0_HCTRL_MODE_U2_S 20\r
+/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH0_POS_MODE_U2 0x00000003\r
+#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S))\r
+#define PCNT_CH0_POS_MODE_U2_V 0x3\r
+#define PCNT_CH0_POS_MODE_U2_S 18\r
+/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH0_NEG_MODE_U2 0x00000003\r
+#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S))\r
+#define PCNT_CH0_NEG_MODE_U2_V 0x3\r
+#define PCNT_CH0_NEG_MODE_U2_S 16\r
+/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit2's count with thres1 value .*/\r
+#define PCNT_THR_THRES1_EN_U2 (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U2_M (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U2_V 0x1\r
+#define PCNT_THR_THRES1_EN_U2_S 15\r
+/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit2's count with thres0 value.*/\r
+#define PCNT_THR_THRES0_EN_U2 (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U2_M (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U2_V 0x1\r
+#define PCNT_THR_THRES0_EN_U2_S 14\r
+/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit2's count with thr_l_lim value.*/\r
+#define PCNT_THR_L_LIM_EN_U2 (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U2_M (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U2_V 0x1\r
+#define PCNT_THR_L_LIM_EN_U2_S 13\r
+/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit2's count with thr_h_lim value.*/\r
+#define PCNT_THR_H_LIM_EN_U2 (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U2_M (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U2_V 0x1\r
+#define PCNT_THR_H_LIM_EN_U2_S 12\r
+/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit2's count with 0 value.*/\r
+#define PCNT_THR_ZERO_EN_U2 (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U2_M (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U2_V 0x1\r
+#define PCNT_THR_ZERO_EN_U2_S 11\r
+/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for filtering input signals for unit2.*/\r
+#define PCNT_FILTER_EN_U2 (BIT(10))\r
+#define PCNT_FILTER_EN_U2_M (BIT(10))\r
+#define PCNT_FILTER_EN_U2_V 0x1\r
+#define PCNT_FILTER_EN_U2_S 10\r
+/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
+/*description: This register is used to filter pluse whose width is smaller\r
+ than this value for unit2.*/\r
+#define PCNT_FILTER_THRES_U2 0x000003FF\r
+#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S))\r
+#define PCNT_FILTER_THRES_U2_V 0x3FF\r
+#define PCNT_FILTER_THRES_U2_S 0\r
+\r
+#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c)\r
+/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres1 value for unit2.*/\r
+#define PCNT_CNT_THRES1_U2 0x0000FFFF\r
+#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S))\r
+#define PCNT_CNT_THRES1_U2_V 0xFFFF\r
+#define PCNT_CNT_THRES1_U2_S 16\r
+/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres0 value for unit2.*/\r
+#define PCNT_CNT_THRES0_U2 0x0000FFFF\r
+#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S))\r
+#define PCNT_CNT_THRES0_U2_V 0xFFFF\r
+#define PCNT_CNT_THRES0_U2_S 0\r
+\r
+#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020)\r
+/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to confiugre thr_l_lim value for unit2.*/\r
+#define PCNT_CNT_L_LIM_U2 0x0000FFFF\r
+#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S))\r
+#define PCNT_CNT_L_LIM_U2_V 0xFFFF\r
+#define PCNT_CNT_L_LIM_U2_S 16\r
+/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thr_h_lim value for unit2.*/\r
+#define PCNT_CNT_H_LIM_U2 0x0000FFFF\r
+#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S))\r
+#define PCNT_CNT_H_LIM_U2_V 0xFFFF\r
+#define PCNT_CNT_H_LIM_U2_S 0\r
+\r
+#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024)\r
+/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's low control\r
+ signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_LCTRL_MODE_U3 0x00000003\r
+#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S))\r
+#define PCNT_CH1_LCTRL_MODE_U3_V 0x3\r
+#define PCNT_CH1_LCTRL_MODE_U3_S 30\r
+/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's high\r
+ control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_HCTRL_MODE_U3 0x00000003\r
+#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S))\r
+#define PCNT_CH1_HCTRL_MODE_U3_V 0x3\r
+#define PCNT_CH1_HCTRL_MODE_U3_S 28\r
+/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH1_POS_MODE_U3 0x00000003\r
+#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S))\r
+#define PCNT_CH1_POS_MODE_U3_V 0x3\r
+#define PCNT_CH1_POS_MODE_U3_S 26\r
+/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH1_NEG_MODE_U3 0x00000003\r
+#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S))\r
+#define PCNT_CH1_NEG_MODE_U3_V 0x3\r
+#define PCNT_CH1_NEG_MODE_U3_S 24\r
+/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's low control\r
+ signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_LCTRL_MODE_U3 0x00000003\r
+#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S))\r
+#define PCNT_CH0_LCTRL_MODE_U3_V 0x3\r
+#define PCNT_CH0_LCTRL_MODE_U3_S 22\r
+/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's high\r
+ control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_HCTRL_MODE_U3 0x00000003\r
+#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S))\r
+#define PCNT_CH0_HCTRL_MODE_U3_V 0x3\r
+#define PCNT_CH0_HCTRL_MODE_U3_S 20\r
+/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH0_POS_MODE_U3 0x00000003\r
+#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S))\r
+#define PCNT_CH0_POS_MODE_U3_V 0x3\r
+#define PCNT_CH0_POS_MODE_U3_S 18\r
+/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH0_NEG_MODE_U3 0x00000003\r
+#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S))\r
+#define PCNT_CH0_NEG_MODE_U3_V 0x3\r
+#define PCNT_CH0_NEG_MODE_U3_S 16\r
+/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit3's count with thres1 value .*/\r
+#define PCNT_THR_THRES1_EN_U3 (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U3_M (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U3_V 0x1\r
+#define PCNT_THR_THRES1_EN_U3_S 15\r
+/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit3's count with thres0 value.*/\r
+#define PCNT_THR_THRES0_EN_U3 (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U3_M (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U3_V 0x1\r
+#define PCNT_THR_THRES0_EN_U3_S 14\r
+/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit3's count with thr_l_lim value.*/\r
+#define PCNT_THR_L_LIM_EN_U3 (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U3_M (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U3_V 0x1\r
+#define PCNT_THR_L_LIM_EN_U3_S 13\r
+/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit3's count with thr_h_lim value.*/\r
+#define PCNT_THR_H_LIM_EN_U3 (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U3_M (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U3_V 0x1\r
+#define PCNT_THR_H_LIM_EN_U3_S 12\r
+/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit3's count with 0 value.*/\r
+#define PCNT_THR_ZERO_EN_U3 (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U3_M (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U3_V 0x1\r
+#define PCNT_THR_ZERO_EN_U3_S 11\r
+/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for filtering input signals for unit3.*/\r
+#define PCNT_FILTER_EN_U3 (BIT(10))\r
+#define PCNT_FILTER_EN_U3_M (BIT(10))\r
+#define PCNT_FILTER_EN_U3_V 0x1\r
+#define PCNT_FILTER_EN_U3_S 10\r
+/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
+/*description: This register is used to filter pluse whose width is smaller\r
+ than this value for unit3.*/\r
+#define PCNT_FILTER_THRES_U3 0x000003FF\r
+#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S))\r
+#define PCNT_FILTER_THRES_U3_V 0x3FF\r
+#define PCNT_FILTER_THRES_U3_S 0\r
+\r
+#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028)\r
+/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres1 value for unit3.*/\r
+#define PCNT_CNT_THRES1_U3 0x0000FFFF\r
+#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S))\r
+#define PCNT_CNT_THRES1_U3_V 0xFFFF\r
+#define PCNT_CNT_THRES1_U3_S 16\r
+/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres0 value for unit3.*/\r
+#define PCNT_CNT_THRES0_U3 0x0000FFFF\r
+#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S))\r
+#define PCNT_CNT_THRES0_U3_V 0xFFFF\r
+#define PCNT_CNT_THRES0_U3_S 0\r
+\r
+#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c)\r
+/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to confiugre thr_l_lim value for unit3.*/\r
+#define PCNT_CNT_L_LIM_U3 0x0000FFFF\r
+#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S))\r
+#define PCNT_CNT_L_LIM_U3_V 0xFFFF\r
+#define PCNT_CNT_L_LIM_U3_S 16\r
+/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thr_h_lim value for unit3.*/\r
+#define PCNT_CNT_H_LIM_U3 0x0000FFFF\r
+#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S))\r
+#define PCNT_CNT_H_LIM_U3_V 0xFFFF\r
+#define PCNT_CNT_H_LIM_U3_S 0\r
+\r
+#define PCNT_U4_CONF0_REG (DR_REG_PCNT_BASE + 0x0030)\r
+/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's low control\r
+ signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_LCTRL_MODE_U4 0x00000003\r
+#define PCNT_CH1_LCTRL_MODE_U4_M ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S))\r
+#define PCNT_CH1_LCTRL_MODE_U4_V 0x3\r
+#define PCNT_CH1_LCTRL_MODE_U4_S 30\r
+/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's high\r
+ control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_HCTRL_MODE_U4 0x00000003\r
+#define PCNT_CH1_HCTRL_MODE_U4_M ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S))\r
+#define PCNT_CH1_HCTRL_MODE_U4_V 0x3\r
+#define PCNT_CH1_HCTRL_MODE_U4_S 28\r
+/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH1_POS_MODE_U4 0x00000003\r
+#define PCNT_CH1_POS_MODE_U4_M ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S))\r
+#define PCNT_CH1_POS_MODE_U4_V 0x3\r
+#define PCNT_CH1_POS_MODE_U4_S 26\r
+/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH1_NEG_MODE_U4 0x00000003\r
+#define PCNT_CH1_NEG_MODE_U4_M ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S))\r
+#define PCNT_CH1_NEG_MODE_U4_V 0x3\r
+#define PCNT_CH1_NEG_MODE_U4_S 24\r
+/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's low control\r
+ signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_LCTRL_MODE_U4 0x00000003\r
+#define PCNT_CH0_LCTRL_MODE_U4_M ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S))\r
+#define PCNT_CH0_LCTRL_MODE_U4_V 0x3\r
+#define PCNT_CH0_LCTRL_MODE_U4_S 22\r
+/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's high\r
+ control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_HCTRL_MODE_U4 0x00000003\r
+#define PCNT_CH0_HCTRL_MODE_U4_M ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S))\r
+#define PCNT_CH0_HCTRL_MODE_U4_V 0x3\r
+#define PCNT_CH0_HCTRL_MODE_U4_S 20\r
+/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH0_POS_MODE_U4 0x00000003\r
+#define PCNT_CH0_POS_MODE_U4_M ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S))\r
+#define PCNT_CH0_POS_MODE_U4_V 0x3\r
+#define PCNT_CH0_POS_MODE_U4_S 18\r
+/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH0_NEG_MODE_U4 0x00000003\r
+#define PCNT_CH0_NEG_MODE_U4_M ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S))\r
+#define PCNT_CH0_NEG_MODE_U4_V 0x3\r
+#define PCNT_CH0_NEG_MODE_U4_S 16\r
+/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit4's count with thres1 value .*/\r
+#define PCNT_THR_THRES1_EN_U4 (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U4_M (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U4_V 0x1\r
+#define PCNT_THR_THRES1_EN_U4_S 15\r
+/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit4's count with thres0 value.*/\r
+#define PCNT_THR_THRES0_EN_U4 (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U4_M (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U4_V 0x1\r
+#define PCNT_THR_THRES0_EN_U4_S 14\r
+/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit4's count with thr_l_lim value.*/\r
+#define PCNT_THR_L_LIM_EN_U4 (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U4_M (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U4_V 0x1\r
+#define PCNT_THR_L_LIM_EN_U4_S 13\r
+/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit4's count with thr_h_lim value.*/\r
+#define PCNT_THR_H_LIM_EN_U4 (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U4_M (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U4_V 0x1\r
+#define PCNT_THR_H_LIM_EN_U4_S 12\r
+/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit4's count with 0 value.*/\r
+#define PCNT_THR_ZERO_EN_U4 (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U4_M (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U4_V 0x1\r
+#define PCNT_THR_ZERO_EN_U4_S 11\r
+/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for filtering input signals for unit4.*/\r
+#define PCNT_FILTER_EN_U4 (BIT(10))\r
+#define PCNT_FILTER_EN_U4_M (BIT(10))\r
+#define PCNT_FILTER_EN_U4_V 0x1\r
+#define PCNT_FILTER_EN_U4_S 10\r
+/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
+/*description: This register is used to filter pluse whose width is smaller\r
+ than this value for unit4.*/\r
+#define PCNT_FILTER_THRES_U4 0x000003FF\r
+#define PCNT_FILTER_THRES_U4_M ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S))\r
+#define PCNT_FILTER_THRES_U4_V 0x3FF\r
+#define PCNT_FILTER_THRES_U4_S 0\r
+\r
+#define PCNT_U4_CONF1_REG (DR_REG_PCNT_BASE + 0x0034)\r
+/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres1 value for unit4.*/\r
+#define PCNT_CNT_THRES1_U4 0x0000FFFF\r
+#define PCNT_CNT_THRES1_U4_M ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S))\r
+#define PCNT_CNT_THRES1_U4_V 0xFFFF\r
+#define PCNT_CNT_THRES1_U4_S 16\r
+/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres0 value for unit4.*/\r
+#define PCNT_CNT_THRES0_U4 0x0000FFFF\r
+#define PCNT_CNT_THRES0_U4_M ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S))\r
+#define PCNT_CNT_THRES0_U4_V 0xFFFF\r
+#define PCNT_CNT_THRES0_U4_S 0\r
+\r
+#define PCNT_U4_CONF2_REG (DR_REG_PCNT_BASE + 0x0038)\r
+/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to confiugre thr_l_lim value for unit4.*/\r
+#define PCNT_CNT_L_LIM_U4 0x0000FFFF\r
+#define PCNT_CNT_L_LIM_U4_M ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S))\r
+#define PCNT_CNT_L_LIM_U4_V 0xFFFF\r
+#define PCNT_CNT_L_LIM_U4_S 16\r
+/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thr_h_lim value for unit4.*/\r
+#define PCNT_CNT_H_LIM_U4 0x0000FFFF\r
+#define PCNT_CNT_H_LIM_U4_M ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S))\r
+#define PCNT_CNT_H_LIM_U4_V 0xFFFF\r
+#define PCNT_CNT_H_LIM_U4_S 0\r
+\r
+#define PCNT_U5_CONF0_REG (DR_REG_PCNT_BASE + 0x003c)\r
+/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's low control\r
+ signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_LCTRL_MODE_U5 0x00000003\r
+#define PCNT_CH1_LCTRL_MODE_U5_M ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S))\r
+#define PCNT_CH1_LCTRL_MODE_U5_V 0x3\r
+#define PCNT_CH1_LCTRL_MODE_U5_S 30\r
+/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's high\r
+ control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_HCTRL_MODE_U5 0x00000003\r
+#define PCNT_CH1_HCTRL_MODE_U5_M ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S))\r
+#define PCNT_CH1_HCTRL_MODE_U5_V 0x3\r
+#define PCNT_CH1_HCTRL_MODE_U5_S 28\r
+/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH1_POS_MODE_U5 0x00000003\r
+#define PCNT_CH1_POS_MODE_U5_M ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S))\r
+#define PCNT_CH1_POS_MODE_U5_V 0x3\r
+#define PCNT_CH1_POS_MODE_U5_S 26\r
+/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH1_NEG_MODE_U5 0x00000003\r
+#define PCNT_CH1_NEG_MODE_U5_M ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S))\r
+#define PCNT_CH1_NEG_MODE_U5_V 0x3\r
+#define PCNT_CH1_NEG_MODE_U5_S 24\r
+/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's low control\r
+ signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_LCTRL_MODE_U5 0x00000003\r
+#define PCNT_CH0_LCTRL_MODE_U5_M ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S))\r
+#define PCNT_CH0_LCTRL_MODE_U5_V 0x3\r
+#define PCNT_CH0_LCTRL_MODE_U5_S 22\r
+/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's high\r
+ control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_HCTRL_MODE_U5 0x00000003\r
+#define PCNT_CH0_HCTRL_MODE_U5_M ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S))\r
+#define PCNT_CH0_HCTRL_MODE_U5_V 0x3\r
+#define PCNT_CH0_HCTRL_MODE_U5_S 20\r
+/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH0_POS_MODE_U5 0x00000003\r
+#define PCNT_CH0_POS_MODE_U5_M ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S))\r
+#define PCNT_CH0_POS_MODE_U5_V 0x3\r
+#define PCNT_CH0_POS_MODE_U5_S 18\r
+/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH0_NEG_MODE_U5 0x00000003\r
+#define PCNT_CH0_NEG_MODE_U5_M ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S))\r
+#define PCNT_CH0_NEG_MODE_U5_V 0x3\r
+#define PCNT_CH0_NEG_MODE_U5_S 16\r
+/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit5's count with thres1 value .*/\r
+#define PCNT_THR_THRES1_EN_U5 (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U5_M (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U5_V 0x1\r
+#define PCNT_THR_THRES1_EN_U5_S 15\r
+/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit5's count with thres0 value.*/\r
+#define PCNT_THR_THRES0_EN_U5 (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U5_M (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U5_V 0x1\r
+#define PCNT_THR_THRES0_EN_U5_S 14\r
+/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit5's count with thr_l_lim value.*/\r
+#define PCNT_THR_L_LIM_EN_U5 (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U5_M (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U5_V 0x1\r
+#define PCNT_THR_L_LIM_EN_U5_S 13\r
+/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit5's count with thr_h_lim value.*/\r
+#define PCNT_THR_H_LIM_EN_U5 (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U5_M (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U5_V 0x1\r
+#define PCNT_THR_H_LIM_EN_U5_S 12\r
+/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit5's count with 0 value.*/\r
+#define PCNT_THR_ZERO_EN_U5 (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U5_M (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U5_V 0x1\r
+#define PCNT_THR_ZERO_EN_U5_S 11\r
+/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for filtering input signals for unit5.*/\r
+#define PCNT_FILTER_EN_U5 (BIT(10))\r
+#define PCNT_FILTER_EN_U5_M (BIT(10))\r
+#define PCNT_FILTER_EN_U5_V 0x1\r
+#define PCNT_FILTER_EN_U5_S 10\r
+/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
+/*description: This register is used to filter pluse whose width is smaller\r
+ than this value for unit5.*/\r
+#define PCNT_FILTER_THRES_U5 0x000003FF\r
+#define PCNT_FILTER_THRES_U5_M ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S))\r
+#define PCNT_FILTER_THRES_U5_V 0x3FF\r
+#define PCNT_FILTER_THRES_U5_S 0\r
+\r
+#define PCNT_U5_CONF1_REG (DR_REG_PCNT_BASE + 0x0040)\r
+/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres1 value for unit5.*/\r
+#define PCNT_CNT_THRES1_U5 0x0000FFFF\r
+#define PCNT_CNT_THRES1_U5_M ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S))\r
+#define PCNT_CNT_THRES1_U5_V 0xFFFF\r
+#define PCNT_CNT_THRES1_U5_S 16\r
+/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres0 value for unit5.*/\r
+#define PCNT_CNT_THRES0_U5 0x0000FFFF\r
+#define PCNT_CNT_THRES0_U5_M ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S))\r
+#define PCNT_CNT_THRES0_U5_V 0xFFFF\r
+#define PCNT_CNT_THRES0_U5_S 0\r
+\r
+#define PCNT_U5_CONF2_REG (DR_REG_PCNT_BASE + 0x0044)\r
+/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to confiugre thr_l_lim value for unit5.*/\r
+#define PCNT_CNT_L_LIM_U5 0x0000FFFF\r
+#define PCNT_CNT_L_LIM_U5_M ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S))\r
+#define PCNT_CNT_L_LIM_U5_V 0xFFFF\r
+#define PCNT_CNT_L_LIM_U5_S 16\r
+/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thr_h_lim value for unit5.*/\r
+#define PCNT_CNT_H_LIM_U5 0x0000FFFF\r
+#define PCNT_CNT_H_LIM_U5_M ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S))\r
+#define PCNT_CNT_H_LIM_U5_V 0xFFFF\r
+#define PCNT_CNT_H_LIM_U5_S 0\r
+\r
+#define PCNT_U6_CONF0_REG (DR_REG_PCNT_BASE + 0x0048)\r
+/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's low control\r
+ signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_LCTRL_MODE_U6 0x00000003\r
+#define PCNT_CH1_LCTRL_MODE_U6_M ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S))\r
+#define PCNT_CH1_LCTRL_MODE_U6_V 0x3\r
+#define PCNT_CH1_LCTRL_MODE_U6_S 30\r
+/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's high\r
+ control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_HCTRL_MODE_U6 0x00000003\r
+#define PCNT_CH1_HCTRL_MODE_U6_M ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S))\r
+#define PCNT_CH1_HCTRL_MODE_U6_V 0x3\r
+#define PCNT_CH1_HCTRL_MODE_U6_S 28\r
+/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH1_POS_MODE_U6 0x00000003\r
+#define PCNT_CH1_POS_MODE_U6_M ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S))\r
+#define PCNT_CH1_POS_MODE_U6_V 0x3\r
+#define PCNT_CH1_POS_MODE_U6_S 26\r
+/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH1_NEG_MODE_U6 0x00000003\r
+#define PCNT_CH1_NEG_MODE_U6_M ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S))\r
+#define PCNT_CH1_NEG_MODE_U6_V 0x3\r
+#define PCNT_CH1_NEG_MODE_U6_S 24\r
+/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's low control\r
+ signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_LCTRL_MODE_U6 0x00000003\r
+#define PCNT_CH0_LCTRL_MODE_U6_M ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S))\r
+#define PCNT_CH0_LCTRL_MODE_U6_V 0x3\r
+#define PCNT_CH0_LCTRL_MODE_U6_S 22\r
+/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's high\r
+ control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_HCTRL_MODE_U6 0x00000003\r
+#define PCNT_CH0_HCTRL_MODE_U6_M ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S))\r
+#define PCNT_CH0_HCTRL_MODE_U6_V 0x3\r
+#define PCNT_CH0_HCTRL_MODE_U6_S 20\r
+/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH0_POS_MODE_U6 0x00000003\r
+#define PCNT_CH0_POS_MODE_U6_M ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S))\r
+#define PCNT_CH0_POS_MODE_U6_V 0x3\r
+#define PCNT_CH0_POS_MODE_U6_S 18\r
+/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH0_NEG_MODE_U6 0x00000003\r
+#define PCNT_CH0_NEG_MODE_U6_M ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S))\r
+#define PCNT_CH0_NEG_MODE_U6_V 0x3\r
+#define PCNT_CH0_NEG_MODE_U6_S 16\r
+/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit6's count with thres1 value .*/\r
+#define PCNT_THR_THRES1_EN_U6 (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U6_M (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U6_V 0x1\r
+#define PCNT_THR_THRES1_EN_U6_S 15\r
+/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit6's count with thres0 value.*/\r
+#define PCNT_THR_THRES0_EN_U6 (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U6_M (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U6_V 0x1\r
+#define PCNT_THR_THRES0_EN_U6_S 14\r
+/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit6's count with thr_l_lim value.*/\r
+#define PCNT_THR_L_LIM_EN_U6 (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U6_M (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U6_V 0x1\r
+#define PCNT_THR_L_LIM_EN_U6_S 13\r
+/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit6's count with thr_h_lim value.*/\r
+#define PCNT_THR_H_LIM_EN_U6 (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U6_M (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U6_V 0x1\r
+#define PCNT_THR_H_LIM_EN_U6_S 12\r
+/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit6's count with 0 value.*/\r
+#define PCNT_THR_ZERO_EN_U6 (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U6_M (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U6_V 0x1\r
+#define PCNT_THR_ZERO_EN_U6_S 11\r
+/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for filtering input signals for unit6.*/\r
+#define PCNT_FILTER_EN_U6 (BIT(10))\r
+#define PCNT_FILTER_EN_U6_M (BIT(10))\r
+#define PCNT_FILTER_EN_U6_V 0x1\r
+#define PCNT_FILTER_EN_U6_S 10\r
+/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
+/*description: This register is used to filter pluse whose width is smaller\r
+ than this value for unit6.*/\r
+#define PCNT_FILTER_THRES_U6 0x000003FF\r
+#define PCNT_FILTER_THRES_U6_M ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S))\r
+#define PCNT_FILTER_THRES_U6_V 0x3FF\r
+#define PCNT_FILTER_THRES_U6_S 0\r
+\r
+#define PCNT_U6_CONF1_REG (DR_REG_PCNT_BASE + 0x004c)\r
+/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres1 value for unit6.*/\r
+#define PCNT_CNT_THRES1_U6 0x0000FFFF\r
+#define PCNT_CNT_THRES1_U6_M ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S))\r
+#define PCNT_CNT_THRES1_U6_V 0xFFFF\r
+#define PCNT_CNT_THRES1_U6_S 16\r
+/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres0 value for unit6.*/\r
+#define PCNT_CNT_THRES0_U6 0x0000FFFF\r
+#define PCNT_CNT_THRES0_U6_M ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S))\r
+#define PCNT_CNT_THRES0_U6_V 0xFFFF\r
+#define PCNT_CNT_THRES0_U6_S 0\r
+\r
+#define PCNT_U6_CONF2_REG (DR_REG_PCNT_BASE + 0x0050)\r
+/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to confiugre thr_l_lim value for unit6.*/\r
+#define PCNT_CNT_L_LIM_U6 0x0000FFFF\r
+#define PCNT_CNT_L_LIM_U6_M ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S))\r
+#define PCNT_CNT_L_LIM_U6_V 0xFFFF\r
+#define PCNT_CNT_L_LIM_U6_S 16\r
+/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thr_h_lim value for unit6.*/\r
+#define PCNT_CNT_H_LIM_U6 0x0000FFFF\r
+#define PCNT_CNT_H_LIM_U6_M ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S))\r
+#define PCNT_CNT_H_LIM_U6_V 0xFFFF\r
+#define PCNT_CNT_H_LIM_U6_S 0\r
+\r
+#define PCNT_U7_CONF0_REG (DR_REG_PCNT_BASE + 0x0054)\r
+/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's low control\r
+ signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_LCTRL_MODE_U7 0x00000003\r
+#define PCNT_CH1_LCTRL_MODE_U7_M ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S))\r
+#define PCNT_CH1_LCTRL_MODE_U7_V 0x3\r
+#define PCNT_CH1_LCTRL_MODE_U7_S 30\r
+/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's high\r
+ control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH1_HCTRL_MODE_U7 0x00000003\r
+#define PCNT_CH1_HCTRL_MODE_U7_M ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S))\r
+#define PCNT_CH1_HCTRL_MODE_U7_V 0x3\r
+#define PCNT_CH1_HCTRL_MODE_U7_S 28\r
+/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH1_POS_MODE_U7 0x00000003\r
+#define PCNT_CH1_POS_MODE_U7_M ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S))\r
+#define PCNT_CH1_POS_MODE_U7_V 0x3\r
+#define PCNT_CH1_POS_MODE_U7_S 26\r
+/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel1's input\r
+ negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH1_NEG_MODE_U7 0x00000003\r
+#define PCNT_CH1_NEG_MODE_U7_M ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S))\r
+#define PCNT_CH1_NEG_MODE_U7_V 0x3\r
+#define PCNT_CH1_NEG_MODE_U7_S 24\r
+/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's low control\r
+ signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_LCTRL_MODE_U7 0x00000003\r
+#define PCNT_CH0_LCTRL_MODE_U7_M ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S))\r
+#define PCNT_CH0_LCTRL_MODE_U7_V 0x3\r
+#define PCNT_CH0_LCTRL_MODE_U7_S 22\r
+/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's high\r
+ control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden*/\r
+#define PCNT_CH0_HCTRL_MODE_U7 0x00000003\r
+#define PCNT_CH0_HCTRL_MODE_U7_M ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S))\r
+#define PCNT_CH0_HCTRL_MODE_U7_V 0x3\r
+#define PCNT_CH0_HCTRL_MODE_U7_S 20\r
+/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/\r
+#define PCNT_CH0_POS_MODE_U7 0x00000003\r
+#define PCNT_CH0_POS_MODE_U7_M ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S))\r
+#define PCNT_CH0_POS_MODE_U7_V 0x3\r
+#define PCNT_CH0_POS_MODE_U7_S 18\r
+/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: This register is used to control the mode of channel0's input\r
+ negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/\r
+#define PCNT_CH0_NEG_MODE_U7 0x00000003\r
+#define PCNT_CH0_NEG_MODE_U7_M ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S))\r
+#define PCNT_CH0_NEG_MODE_U7_V 0x3\r
+#define PCNT_CH0_NEG_MODE_U7_S 16\r
+/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit7's count with thres1 value .*/\r
+#define PCNT_THR_THRES1_EN_U7 (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U7_M (BIT(15))\r
+#define PCNT_THR_THRES1_EN_U7_V 0x1\r
+#define PCNT_THR_THRES1_EN_U7_S 15\r
+/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for comparing unit7's count with thres0 value.*/\r
+#define PCNT_THR_THRES0_EN_U7 (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U7_M (BIT(14))\r
+#define PCNT_THR_THRES0_EN_U7_V 0x1\r
+#define PCNT_THR_THRES0_EN_U7_S 14\r
+/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit7's count with thr_l_lim value.*/\r
+#define PCNT_THR_L_LIM_EN_U7 (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U7_M (BIT(13))\r
+#define PCNT_THR_L_LIM_EN_U7_V 0x1\r
+#define PCNT_THR_L_LIM_EN_U7_S 13\r
+/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit7's count with thr_h_lim value.*/\r
+#define PCNT_THR_H_LIM_EN_U7 (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U7_M (BIT(12))\r
+#define PCNT_THR_H_LIM_EN_U7_V 0x1\r
+#define PCNT_THR_H_LIM_EN_U7_S 12\r
+/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for comparing unit7's count with 0 value.*/\r
+#define PCNT_THR_ZERO_EN_U7 (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U7_M (BIT(11))\r
+#define PCNT_THR_ZERO_EN_U7_V 0x1\r
+#define PCNT_THR_ZERO_EN_U7_S 11\r
+/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: This is the enable bit for filtering input signals for unit7.*/\r
+#define PCNT_FILTER_EN_U7 (BIT(10))\r
+#define PCNT_FILTER_EN_U7_M (BIT(10))\r
+#define PCNT_FILTER_EN_U7_V 0x1\r
+#define PCNT_FILTER_EN_U7_S 10\r
+/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */\r
+/*description: This register is used to filter pluse whose width is smaller\r
+ than this value for unit7.*/\r
+#define PCNT_FILTER_THRES_U7 0x000003FF\r
+#define PCNT_FILTER_THRES_U7_M ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S))\r
+#define PCNT_FILTER_THRES_U7_V 0x3FF\r
+#define PCNT_FILTER_THRES_U7_S 0\r
+\r
+#define PCNT_U7_CONF1_REG (DR_REG_PCNT_BASE + 0x0058)\r
+/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres1 value for unit7.*/\r
+#define PCNT_CNT_THRES1_U7 0x0000FFFF\r
+#define PCNT_CNT_THRES1_U7_M ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S))\r
+#define PCNT_CNT_THRES1_U7_V 0xFFFF\r
+#define PCNT_CNT_THRES1_U7_S 16\r
+/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thres0 value for unit7.*/\r
+#define PCNT_CNT_THRES0_U7 0x0000FFFF\r
+#define PCNT_CNT_THRES0_U7_M ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S))\r
+#define PCNT_CNT_THRES0_U7_V 0xFFFF\r
+#define PCNT_CNT_THRES0_U7_S 0\r
+\r
+#define PCNT_U7_CONF2_REG (DR_REG_PCNT_BASE + 0x005c)\r
+/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */\r
+/*description: This register is used to confiugre thr_l_lim value for unit7.*/\r
+#define PCNT_CNT_L_LIM_U7 0x0000FFFF\r
+#define PCNT_CNT_L_LIM_U7_M ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S))\r
+#define PCNT_CNT_L_LIM_U7_V 0xFFFF\r
+#define PCNT_CNT_L_LIM_U7_S 16\r
+/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */\r
+/*description: This register is used to configure thr_h_lim value for unit7.*/\r
+#define PCNT_CNT_H_LIM_U7 0x0000FFFF\r
+#define PCNT_CNT_H_LIM_U7_M ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S))\r
+#define PCNT_CNT_H_LIM_U7_V 0xFFFF\r
+#define PCNT_CNT_H_LIM_U7_S 0\r
+\r
+#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0060)\r
+/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: This register stores the current pulse count value for unit0.*/\r
+#define PCNT_PLUS_CNT_U0 0x0000FFFF\r
+#define PCNT_PLUS_CNT_U0_M ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S))\r
+#define PCNT_PLUS_CNT_U0_V 0xFFFF\r
+#define PCNT_PLUS_CNT_U0_S 0\r
+\r
+#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0064)\r
+/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: This register stores the current pulse count value for unit1.*/\r
+#define PCNT_PLUS_CNT_U1 0x0000FFFF\r
+#define PCNT_PLUS_CNT_U1_M ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S))\r
+#define PCNT_PLUS_CNT_U1_V 0xFFFF\r
+#define PCNT_PLUS_CNT_U1_S 0\r
+\r
+#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0068)\r
+/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: This register stores the current pulse count value for unit2.*/\r
+#define PCNT_PLUS_CNT_U2 0x0000FFFF\r
+#define PCNT_PLUS_CNT_U2_M ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S))\r
+#define PCNT_PLUS_CNT_U2_V 0xFFFF\r
+#define PCNT_PLUS_CNT_U2_S 0\r
+\r
+#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x006c)\r
+/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: This register stores the current pulse count value for unit3.*/\r
+#define PCNT_PLUS_CNT_U3 0x0000FFFF\r
+#define PCNT_PLUS_CNT_U3_M ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S))\r
+#define PCNT_PLUS_CNT_U3_V 0xFFFF\r
+#define PCNT_PLUS_CNT_U3_S 0\r
+\r
+#define PCNT_U4_CNT_REG (DR_REG_PCNT_BASE + 0x0070)\r
+/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: This register stores the current pulse count value for unit4.*/\r
+#define PCNT_PLUS_CNT_U4 0x0000FFFF\r
+#define PCNT_PLUS_CNT_U4_M ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S))\r
+#define PCNT_PLUS_CNT_U4_V 0xFFFF\r
+#define PCNT_PLUS_CNT_U4_S 0\r
+\r
+#define PCNT_U5_CNT_REG (DR_REG_PCNT_BASE + 0x0074)\r
+/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: This register stores the current pulse count value for unit5.*/\r
+#define PCNT_PLUS_CNT_U5 0x0000FFFF\r
+#define PCNT_PLUS_CNT_U5_M ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S))\r
+#define PCNT_PLUS_CNT_U5_V 0xFFFF\r
+#define PCNT_PLUS_CNT_U5_S 0\r
+\r
+#define PCNT_U6_CNT_REG (DR_REG_PCNT_BASE + 0x0078)\r
+/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: This register stores the current pulse count value for unit6.*/\r
+#define PCNT_PLUS_CNT_U6 0x0000FFFF\r
+#define PCNT_PLUS_CNT_U6_M ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S))\r
+#define PCNT_PLUS_CNT_U6_V 0xFFFF\r
+#define PCNT_PLUS_CNT_U6_S 0\r
+\r
+#define PCNT_U7_CNT_REG (DR_REG_PCNT_BASE + 0x007c)\r
+/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: This register stores the current pulse count value for unit7.*/\r
+#define PCNT_PLUS_CNT_U7 0x0000FFFF\r
+#define PCNT_PLUS_CNT_U7_M ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S))\r
+#define PCNT_PLUS_CNT_U7_V 0xFFFF\r
+#define PCNT_PLUS_CNT_U7_S 0\r
+\r
+#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0080)\r
+/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the interrupt raw bit for channel7 event.*/\r
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW (BIT(7))\r
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M (BIT(7))\r
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S 7\r
+/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This is the interrupt raw bit for channel6 event.*/\r
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW (BIT(6))\r
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M (BIT(6))\r
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S 6\r
+/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: This is the interrupt raw bit for channel5 event.*/\r
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW (BIT(5))\r
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M (BIT(5))\r
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S 5\r
+/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This is the interrupt raw bit for channel4 event.*/\r
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW (BIT(4))\r
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M (BIT(4))\r
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S 4\r
+/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This is the interrupt raw bit for channel3 event.*/\r
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3))\r
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3))\r
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3\r
+/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the interrupt raw bit for channel2 event.*/\r
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2))\r
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2))\r
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2\r
+/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: This is the interrupt raw bit for channel1 event.*/\r
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1))\r
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1))\r
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1\r
+/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This is the interrupt raw bit for channel0 event.*/\r
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0))\r
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0))\r
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0\r
+\r
+#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0084)\r
+/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the interrupt status bit for channel7 event.*/\r
+#define PCNT_CNT_THR_EVENT_U7_INT_ST (BIT(7))\r
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_M (BIT(7))\r
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_S 7\r
+/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This is the interrupt status bit for channel6 event.*/\r
+#define PCNT_CNT_THR_EVENT_U6_INT_ST (BIT(6))\r
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_M (BIT(6))\r
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_S 6\r
+/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: This is the interrupt status bit for channel5 event.*/\r
+#define PCNT_CNT_THR_EVENT_U5_INT_ST (BIT(5))\r
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_M (BIT(5))\r
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_S 5\r
+/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This is the interrupt status bit for channel4 event.*/\r
+#define PCNT_CNT_THR_EVENT_U4_INT_ST (BIT(4))\r
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_M (BIT(4))\r
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_S 4\r
+/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This is the interrupt status bit for channel3 event.*/\r
+#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3))\r
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3))\r
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3\r
+/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the interrupt status bit for channel2 event.*/\r
+#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2))\r
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2))\r
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2\r
+/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: This is the interrupt status bit for channel1 event.*/\r
+#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1))\r
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1))\r
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1\r
+/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This is the interrupt status bit for channel0 event.*/\r
+#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0))\r
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0))\r
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0\r
+\r
+#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0088)\r
+/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the interrupt enable bit for channel7 event.*/\r
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA (BIT(7))\r
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M (BIT(7))\r
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S 7\r
+/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This is the interrupt enable bit for channel6 event.*/\r
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA (BIT(6))\r
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M (BIT(6))\r
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S 6\r
+/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: This is the interrupt enable bit for channel5 event.*/\r
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA (BIT(5))\r
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M (BIT(5))\r
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S 5\r
+/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This is the interrupt enable bit for channel4 event.*/\r
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA (BIT(4))\r
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M (BIT(4))\r
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S 4\r
+/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This is the interrupt enable bit for channel3 event.*/\r
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3))\r
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3))\r
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3\r
+/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the interrupt enable bit for channel2 event.*/\r
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2))\r
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2))\r
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2\r
+/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: This is the interrupt enable bit for channel1 event.*/\r
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1))\r
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1))\r
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1\r
+/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This is the interrupt enable bit for channel0 event.*/\r
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0))\r
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0))\r
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0\r
+\r
+#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x008c)\r
+/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear channel7 event interrupt.*/\r
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR (BIT(7))\r
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M (BIT(7))\r
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S 7\r
+/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear channel6 event interrupt.*/\r
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR (BIT(6))\r
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M (BIT(6))\r
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S 6\r
+/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear channel5 event interrupt.*/\r
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR (BIT(5))\r
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M (BIT(5))\r
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S 5\r
+/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear channel4 event interrupt.*/\r
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR (BIT(4))\r
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M (BIT(4))\r
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S 4\r
+/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear channel3 event interrupt.*/\r
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3))\r
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3))\r
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3\r
+/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear channel2 event interrupt.*/\r
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2))\r
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2))\r
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2\r
+/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear channel1 event interrupt.*/\r
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1))\r
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1))\r
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1\r
+/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear channel0 event interrupt.*/\r
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0))\r
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0))\r
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1\r
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0\r
+\r
+#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0090)\r
+/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define PCNT_CORE_STATUS_U0 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U0_M ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S))\r
+#define PCNT_CORE_STATUS_U0_V 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U0_S 0\r
+\r
+#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0094)\r
+/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define PCNT_CORE_STATUS_U1 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U1_M ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S))\r
+#define PCNT_CORE_STATUS_U1_V 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U1_S 0\r
+\r
+#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0098)\r
+/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define PCNT_CORE_STATUS_U2 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U2_M ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S))\r
+#define PCNT_CORE_STATUS_U2_V 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U2_S 0\r
+\r
+#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x009c)\r
+/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define PCNT_CORE_STATUS_U3 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U3_M ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S))\r
+#define PCNT_CORE_STATUS_U3_V 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U3_S 0\r
+\r
+#define PCNT_U4_STATUS_REG (DR_REG_PCNT_BASE + 0x00a0)\r
+/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define PCNT_CORE_STATUS_U4 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U4_M ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S))\r
+#define PCNT_CORE_STATUS_U4_V 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U4_S 0\r
+\r
+#define PCNT_U5_STATUS_REG (DR_REG_PCNT_BASE + 0x00a4)\r
+/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define PCNT_CORE_STATUS_U5 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U5_M ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S))\r
+#define PCNT_CORE_STATUS_U5_V 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U5_S 0\r
+\r
+#define PCNT_U6_STATUS_REG (DR_REG_PCNT_BASE + 0x00a8)\r
+/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define PCNT_CORE_STATUS_U6 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U6_M ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S))\r
+#define PCNT_CORE_STATUS_U6_V 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U6_S 0\r
+\r
+#define PCNT_U7_STATUS_REG (DR_REG_PCNT_BASE + 0x00ac)\r
+/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define PCNT_CORE_STATUS_U7 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U7_M ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S))\r
+#define PCNT_CORE_STATUS_U7_V 0xFFFFFFFF\r
+#define PCNT_CORE_STATUS_U7_S 0\r
+\r
+#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x00b0)\r
+/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: */\r
+#define PCNT_CLK_EN (BIT(16))\r
+#define PCNT_CLK_EN_M (BIT(16))\r
+#define PCNT_CLK_EN_V 0x1\r
+#define PCNT_CLK_EN_S 16\r
+/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: Set this bit to pause unit7's counter.*/\r
+#define PCNT_CNT_PAUSE_U7 (BIT(15))\r
+#define PCNT_CNT_PAUSE_U7_M (BIT(15))\r
+#define PCNT_CNT_PAUSE_U7_V 0x1\r
+#define PCNT_CNT_PAUSE_U7_S 15\r
+/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */\r
+/*description: Set this bit to clear unit7's counter.*/\r
+#define PCNT_PLUS_CNT_RST_U7 (BIT(14))\r
+#define PCNT_PLUS_CNT_RST_U7_M (BIT(14))\r
+#define PCNT_PLUS_CNT_RST_U7_V 0x1\r
+#define PCNT_PLUS_CNT_RST_U7_S 14\r
+/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: Set this bit to pause unit6's counter.*/\r
+#define PCNT_CNT_PAUSE_U6 (BIT(13))\r
+#define PCNT_CNT_PAUSE_U6_M (BIT(13))\r
+#define PCNT_CNT_PAUSE_U6_V 0x1\r
+#define PCNT_CNT_PAUSE_U6_S 13\r
+/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */\r
+/*description: Set this bit to clear unit6's counter.*/\r
+#define PCNT_PLUS_CNT_RST_U6 (BIT(12))\r
+#define PCNT_PLUS_CNT_RST_U6_M (BIT(12))\r
+#define PCNT_PLUS_CNT_RST_U6_V 0x1\r
+#define PCNT_PLUS_CNT_RST_U6_S 12\r
+/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: Set this bit to pause unit5's counter.*/\r
+#define PCNT_CNT_PAUSE_U5 (BIT(11))\r
+#define PCNT_CNT_PAUSE_U5_M (BIT(11))\r
+#define PCNT_CNT_PAUSE_U5_V 0x1\r
+#define PCNT_CNT_PAUSE_U5_S 11\r
+/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: Set this bit to clear unit5's counter.*/\r
+#define PCNT_PLUS_CNT_RST_U5 (BIT(10))\r
+#define PCNT_PLUS_CNT_RST_U5_M (BIT(10))\r
+#define PCNT_PLUS_CNT_RST_U5_V 0x1\r
+#define PCNT_PLUS_CNT_RST_U5_S 10\r
+/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: Set this bit to pause unit4's counter.*/\r
+#define PCNT_CNT_PAUSE_U4 (BIT(9))\r
+#define PCNT_CNT_PAUSE_U4_M (BIT(9))\r
+#define PCNT_CNT_PAUSE_U4_V 0x1\r
+#define PCNT_CNT_PAUSE_U4_S 9\r
+/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */\r
+/*description: Set this bit to clear unit4's counter.*/\r
+#define PCNT_PLUS_CNT_RST_U4 (BIT(8))\r
+#define PCNT_PLUS_CNT_RST_U4_M (BIT(8))\r
+#define PCNT_PLUS_CNT_RST_U4_V 0x1\r
+#define PCNT_PLUS_CNT_RST_U4_S 8\r
+/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: Set this bit to pause unit3's counter.*/\r
+#define PCNT_CNT_PAUSE_U3 (BIT(7))\r
+#define PCNT_CNT_PAUSE_U3_M (BIT(7))\r
+#define PCNT_CNT_PAUSE_U3_V 0x1\r
+#define PCNT_CNT_PAUSE_U3_S 7\r
+/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */\r
+/*description: Set this bit to clear unit3's counter.*/\r
+#define PCNT_PLUS_CNT_RST_U3 (BIT(6))\r
+#define PCNT_PLUS_CNT_RST_U3_M (BIT(6))\r
+#define PCNT_PLUS_CNT_RST_U3_V 0x1\r
+#define PCNT_PLUS_CNT_RST_U3_S 6\r
+/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to pause unit2's counter.*/\r
+#define PCNT_CNT_PAUSE_U2 (BIT(5))\r
+#define PCNT_CNT_PAUSE_U2_M (BIT(5))\r
+#define PCNT_CNT_PAUSE_U2_V 0x1\r
+#define PCNT_CNT_PAUSE_U2_S 5\r
+/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */\r
+/*description: Set this bit to clear unit2's counter.*/\r
+#define PCNT_PLUS_CNT_RST_U2 (BIT(4))\r
+#define PCNT_PLUS_CNT_RST_U2_M (BIT(4))\r
+#define PCNT_PLUS_CNT_RST_U2_V 0x1\r
+#define PCNT_PLUS_CNT_RST_U2_S 4\r
+/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to pause unit1's counter.*/\r
+#define PCNT_CNT_PAUSE_U1 (BIT(3))\r
+#define PCNT_CNT_PAUSE_U1_M (BIT(3))\r
+#define PCNT_CNT_PAUSE_U1_V 0x1\r
+#define PCNT_CNT_PAUSE_U1_S 3\r
+/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */\r
+/*description: Set this bit to clear unit1's counter.*/\r
+#define PCNT_PLUS_CNT_RST_U1 (BIT(2))\r
+#define PCNT_PLUS_CNT_RST_U1_M (BIT(2))\r
+#define PCNT_PLUS_CNT_RST_U1_V 0x1\r
+#define PCNT_PLUS_CNT_RST_U1_S 2\r
+/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to pause unit0's counter.*/\r
+#define PCNT_CNT_PAUSE_U0 (BIT(1))\r
+#define PCNT_CNT_PAUSE_U0_M (BIT(1))\r
+#define PCNT_CNT_PAUSE_U0_V 0x1\r
+#define PCNT_CNT_PAUSE_U0_S 1\r
+/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */\r
+/*description: Set this bit to clear unit0's counter.*/\r
+#define PCNT_PLUS_CNT_RST_U0 (BIT(0))\r
+#define PCNT_PLUS_CNT_RST_U0_M (BIT(0))\r
+#define PCNT_PLUS_CNT_RST_U0_V 0x1\r
+#define PCNT_PLUS_CNT_RST_U0_S 0\r
+\r
+#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc)\r
+/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */\r
+/*description: */\r
+#define PCNT_DATE 0xFFFFFFFF\r
+#define PCNT_DATE_M ((PCNT_DATE_V)<<(PCNT_DATE_S))\r
+#define PCNT_DATE_V 0xFFFFFFFF\r
+#define PCNT_DATE_S 0\r
+\r
+\r
+\r
+\r
+#endif /*_SOC_PCNT_REG_H_ */\r
+\r
+\r
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef _SOC_RMT_REG_H_\r
+#define _SOC_RMT_REG_H_\r
+\r
+#include "soc.h"\r
+#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000)\r
+\r
+#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004)\r
+\r
+#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008)\r
+\r
+#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c)\r
+\r
+#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010)\r
+\r
+#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014)\r
+\r
+#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018)\r
+\r
+#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c)\r
+\r
+#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020)\r
+/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */\r
+/*description: This bit is used to control clock.when software config RMT\r
+ internal registers it controls the register clock.*/\r
+#define RMT_CLK_EN (BIT(31))\r
+#define RMT_CLK_EN_M (BIT(31))\r
+#define RMT_CLK_EN_V 0x1\r
+#define RMT_CLK_EN_S 31\r
+/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/\r
+#define RMT_MEM_PD (BIT(30))\r
+#define RMT_MEM_PD_M (BIT(30))\r
+#define RMT_MEM_PD_V 0x1\r
+#define RMT_MEM_PD_S 30\r
+/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
+/*description: This bit is used to configure the way carrier wave is modulated\r
+ for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level.*/\r
+#define RMT_CARRIER_OUT_LV_CH0 (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH0_M (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH0_V 0x1\r
+#define RMT_CARRIER_OUT_LV_CH0_S 29\r
+/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: This is the carrier modulation enable control bit for channel0.*/\r
+#define RMT_CARRIER_EN_CH0 (BIT(28))\r
+#define RMT_CARRIER_EN_CH0_M (BIT(28))\r
+#define RMT_CARRIER_EN_CH0_V 0x1\r
+#define RMT_CARRIER_EN_CH0_S 28\r
+/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel0.*/\r
+#define RMT_MEM_SIZE_CH0 0x0000000F\r
+#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S))\r
+#define RMT_MEM_SIZE_CH0_V 0xF\r
+#define RMT_MEM_SIZE_CH0_S 24\r
+/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
+/*description: In receive mode when no edge is detected on the input signal\r
+ for longer than reg_idle_thres_ch0 then the receive process is done.*/\r
+#define RMT_IDLE_THRES_CH0 0x0000FFFF\r
+#define RMT_IDLE_THRES_CH0_M ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S))\r
+#define RMT_IDLE_THRES_CH0_V 0xFFFF\r
+#define RMT_IDLE_THRES_CH0_S 8\r
+/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
+/*description: This register is used to configure the frequency divider's factor in channel0.*/\r
+#define RMT_DIV_CNT_CH0 0x000000FF\r
+#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S))\r
+#define RMT_DIV_CNT_CH0_V 0xFF\r
+#define RMT_DIV_CNT_CH0_S 0\r
+\r
+#define RMT_CH0CONF1_REG (DR_REG_RMT_BASE + 0x0024)\r
+/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for channel0 in IDLE state.*/\r
+#define RMT_IDLE_OUT_EN_CH0 (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH0_M (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH0_V 0x1\r
+#define RMT_IDLE_OUT_EN_CH0_S 19\r
+/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This bit configures the output signal's level for channel0 in IDLE state.*/\r
+#define RMT_IDLE_OUT_LV_CH0 (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH0_M (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH0_V 0x1\r
+#define RMT_IDLE_OUT_LV_CH0_S 18\r
+/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
+#define RMT_REF_ALWAYS_ON_CH0 (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH0_M (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH0_V 0x1\r
+#define RMT_REF_ALWAYS_ON_CH0_S 17\r
+/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This bit is used to reset divider in channel0.*/\r
+#define RMT_REF_CNT_RST_CH0 (BIT(16))\r
+#define RMT_REF_CNT_RST_CH0_M (BIT(16))\r
+#define RMT_REF_CNT_RST_CH0_V 0x1\r
+#define RMT_REF_CNT_RST_CH0_S 16\r
+/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
+/*description: in receive mode channel0 ignore input pulse when the pulse width\r
+ is smaller then this value.*/\r
+#define RMT_RX_FILTER_THRES_CH0 0x000000FF\r
+#define RMT_RX_FILTER_THRES_CH0_M ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S))\r
+#define RMT_RX_FILTER_THRES_CH0_V 0xFF\r
+#define RMT_RX_FILTER_THRES_CH0_S 8\r
+/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the receive filter enable bit for channel0.*/\r
+#define RMT_RX_FILTER_EN_CH0 (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH0_M (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH0_V 0x1\r
+#define RMT_RX_FILTER_EN_CH0_S 7\r
+/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to continue sending from the first data to the\r
+ last data in channel0 again and again.*/\r
+#define RMT_TX_CONTI_MODE_CH0 (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH0_M (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH0_V 0x1\r
+#define RMT_TX_CONTI_MODE_CH0_S 6\r
+/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: This is the mark of channel0's ram usage right.1'b1：receiver\r
+ uses the ram 0：transmitter uses the ram*/\r
+#define RMT_MEM_OWNER_CH0 (BIT(5))\r
+#define RMT_MEM_OWNER_CH0_M (BIT(5))\r
+#define RMT_MEM_OWNER_CH0_V 0x1\r
+#define RMT_MEM_OWNER_CH0_S 5\r
+/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/\r
+#define RMT_APB_MEM_RST_CH0 (BIT(4))\r
+#define RMT_APB_MEM_RST_CH0_M (BIT(4))\r
+#define RMT_APB_MEM_RST_CH0_V 0x1\r
+#define RMT_APB_MEM_RST_CH0_S 4\r
+/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/\r
+#define RMT_MEM_RD_RST_CH0 (BIT(3))\r
+#define RMT_MEM_RD_RST_CH0_M (BIT(3))\r
+#define RMT_MEM_RD_RST_CH0_V 0x1\r
+#define RMT_MEM_RD_RST_CH0_S 3\r
+/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset write ram address for channel0 by receiver access.*/\r
+#define RMT_MEM_WR_RST_CH0 (BIT(2))\r
+#define RMT_MEM_WR_RST_CH0_M (BIT(2))\r
+#define RMT_MEM_WR_RST_CH0_V 0x1\r
+#define RMT_MEM_WR_RST_CH0_S 2\r
+/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
+/*description: Set this bit to enbale receving data for channel0.*/\r
+#define RMT_RX_EN_CH0 (BIT(1))\r
+#define RMT_RX_EN_CH0_M (BIT(1))\r
+#define RMT_RX_EN_CH0_V 0x1\r
+#define RMT_RX_EN_CH0_S 1\r
+/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to start sending data for channel0.*/\r
+#define RMT_TX_START_CH0 (BIT(0))\r
+#define RMT_TX_START_CH0_M (BIT(0))\r
+#define RMT_TX_START_CH0_V 0x1\r
+#define RMT_TX_START_CH0_S 0\r
+\r
+#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0028)\r
+/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
+/*description: This bit is used to configure the way carrier wave is modulated\r
+ for channel1.1'b1:transmit on low output level 1'b0:transmit on high output level.*/\r
+#define RMT_CARRIER_OUT_LV_CH1 (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH1_M (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH1_V 0x1\r
+#define RMT_CARRIER_OUT_LV_CH1_S 29\r
+/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: This is the carrier modulation enable control bit for channel1.*/\r
+#define RMT_CARRIER_EN_CH1 (BIT(28))\r
+#define RMT_CARRIER_EN_CH1_M (BIT(28))\r
+#define RMT_CARRIER_EN_CH1_V 0x1\r
+#define RMT_CARRIER_EN_CH1_S 28\r
+/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel1.*/\r
+#define RMT_MEM_SIZE_CH1 0x0000000F\r
+#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S))\r
+#define RMT_MEM_SIZE_CH1_V 0xF\r
+#define RMT_MEM_SIZE_CH1_S 24\r
+/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel1.*/\r
+#define RMT_IDLE_THRES_CH1 0x0000FFFF\r
+#define RMT_IDLE_THRES_CH1_M ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S))\r
+#define RMT_IDLE_THRES_CH1_V 0xFFFF\r
+#define RMT_IDLE_THRES_CH1_S 8\r
+/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
+/*description: This register is used to configure the frequency divider's factor in channel1.*/\r
+#define RMT_DIV_CNT_CH1 0x000000FF\r
+#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S))\r
+#define RMT_DIV_CNT_CH1_V 0xFF\r
+#define RMT_DIV_CNT_CH1_S 0\r
+\r
+#define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x002c)\r
+/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for channel1 in IDLE state.*/\r
+#define RMT_IDLE_OUT_EN_CH1 (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH1_M (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH1_V 0x1\r
+#define RMT_IDLE_OUT_EN_CH1_S 19\r
+/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This bit configures the output signal's level for channel1 in IDLE state.*/\r
+#define RMT_IDLE_OUT_LV_CH1 (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH1_M (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH1_V 0x1\r
+#define RMT_IDLE_OUT_LV_CH1_S 18\r
+/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
+#define RMT_REF_ALWAYS_ON_CH1 (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH1_M (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH1_V 0x1\r
+#define RMT_REF_ALWAYS_ON_CH1_S 17\r
+/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This bit is used to reset divider in channel1.*/\r
+#define RMT_REF_CNT_RST_CH1 (BIT(16))\r
+#define RMT_REF_CNT_RST_CH1_M (BIT(16))\r
+#define RMT_REF_CNT_RST_CH1_V 0x1\r
+#define RMT_REF_CNT_RST_CH1_S 16\r
+/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
+/*description: in receive mode channel1 ignore input pulse when the pulse width\r
+ is smaller then this value.*/\r
+#define RMT_RX_FILTER_THRES_CH1 0x000000FF\r
+#define RMT_RX_FILTER_THRES_CH1_M ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S))\r
+#define RMT_RX_FILTER_THRES_CH1_V 0xFF\r
+#define RMT_RX_FILTER_THRES_CH1_S 8\r
+/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the receive filter enable bit for channel1.*/\r
+#define RMT_RX_FILTER_EN_CH1 (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH1_M (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH1_V 0x1\r
+#define RMT_RX_FILTER_EN_CH1_S 7\r
+/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to continue sending from the first data to the\r
+ last data in channel1 again and again.*/\r
+#define RMT_TX_CONTI_MODE_CH1 (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH1_M (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH1_V 0x1\r
+#define RMT_TX_CONTI_MODE_CH1_S 6\r
+/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: This is the mark of channel1's ram usage right.1'b1：receiver\r
+ uses the ram 0：transmitter uses the ram*/\r
+#define RMT_MEM_OWNER_CH1 (BIT(5))\r
+#define RMT_MEM_OWNER_CH1_M (BIT(5))\r
+#define RMT_MEM_OWNER_CH1_V 0x1\r
+#define RMT_MEM_OWNER_CH1_S 5\r
+/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/\r
+#define RMT_APB_MEM_RST_CH1 (BIT(4))\r
+#define RMT_APB_MEM_RST_CH1_M (BIT(4))\r
+#define RMT_APB_MEM_RST_CH1_V 0x1\r
+#define RMT_APB_MEM_RST_CH1_S 4\r
+/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/\r
+#define RMT_MEM_RD_RST_CH1 (BIT(3))\r
+#define RMT_MEM_RD_RST_CH1_M (BIT(3))\r
+#define RMT_MEM_RD_RST_CH1_V 0x1\r
+#define RMT_MEM_RD_RST_CH1_S 3\r
+/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset write ram address for channel1 by receiver access.*/\r
+#define RMT_MEM_WR_RST_CH1 (BIT(2))\r
+#define RMT_MEM_WR_RST_CH1_M (BIT(2))\r
+#define RMT_MEM_WR_RST_CH1_V 0x1\r
+#define RMT_MEM_WR_RST_CH1_S 2\r
+/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
+/*description: Set this bit to enbale receving data for channel1.*/\r
+#define RMT_RX_EN_CH1 (BIT(1))\r
+#define RMT_RX_EN_CH1_M (BIT(1))\r
+#define RMT_RX_EN_CH1_V 0x1\r
+#define RMT_RX_EN_CH1_S 1\r
+/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to start sending data for channel1.*/\r
+#define RMT_TX_START_CH1 (BIT(0))\r
+#define RMT_TX_START_CH1_M (BIT(0))\r
+#define RMT_TX_START_CH1_V 0x1\r
+#define RMT_TX_START_CH1_S 0\r
+\r
+#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0030)\r
+/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
+/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add\r
+ on low level 1'b0:add on high level.*/\r
+#define RMT_CARRIER_OUT_LV_CH2 (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH2_M (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH2_V 0x1\r
+#define RMT_CARRIER_OUT_LV_CH2_S 29\r
+/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: This is the carrier modulation enable control bit for channel2.*/\r
+#define RMT_CARRIER_EN_CH2 (BIT(28))\r
+#define RMT_CARRIER_EN_CH2_M (BIT(28))\r
+#define RMT_CARRIER_EN_CH2_V 0x1\r
+#define RMT_CARRIER_EN_CH2_S 28\r
+/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel2.*/\r
+#define RMT_MEM_SIZE_CH2 0x0000000F\r
+#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S))\r
+#define RMT_MEM_SIZE_CH2_V 0xF\r
+#define RMT_MEM_SIZE_CH2_S 24\r
+/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2\r
+ then the receive process is done.*/\r
+#define RMT_IDLE_THRES_CH2 0x0000FFFF\r
+#define RMT_IDLE_THRES_CH2_M ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S))\r
+#define RMT_IDLE_THRES_CH2_V 0xFFFF\r
+#define RMT_IDLE_THRES_CH2_S 8\r
+/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
+/*description: This register is used to configure the frequency divider's factor in channel2.*/\r
+#define RMT_DIV_CNT_CH2 0x000000FF\r
+#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S))\r
+#define RMT_DIV_CNT_CH2_V 0xFF\r
+#define RMT_DIV_CNT_CH2_S 0\r
+\r
+#define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x0034)\r
+/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for channel2 in IDLE state.*/\r
+#define RMT_IDLE_OUT_EN_CH2 (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH2_M (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH2_V 0x1\r
+#define RMT_IDLE_OUT_EN_CH2_S 19\r
+/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This bit configures the output signal's level for channel2 in IDLE state.*/\r
+#define RMT_IDLE_OUT_LV_CH2 (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH2_M (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH2_V 0x1\r
+#define RMT_IDLE_OUT_LV_CH2_S 18\r
+/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
+#define RMT_REF_ALWAYS_ON_CH2 (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH2_M (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH2_V 0x1\r
+#define RMT_REF_ALWAYS_ON_CH2_S 17\r
+/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This bit is used to reset divider in channel2.*/\r
+#define RMT_REF_CNT_RST_CH2 (BIT(16))\r
+#define RMT_REF_CNT_RST_CH2_M (BIT(16))\r
+#define RMT_REF_CNT_RST_CH2_V 0x1\r
+#define RMT_REF_CNT_RST_CH2_S 16\r
+/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
+/*description: in receive mode channel2 ignore input pulse when the pulse width\r
+ is smaller then this value.*/\r
+#define RMT_RX_FILTER_THRES_CH2 0x000000FF\r
+#define RMT_RX_FILTER_THRES_CH2_M ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S))\r
+#define RMT_RX_FILTER_THRES_CH2_V 0xFF\r
+#define RMT_RX_FILTER_THRES_CH2_S 8\r
+/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the receive filter enable bit for channel2.*/\r
+#define RMT_RX_FILTER_EN_CH2 (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH2_M (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH2_V 0x1\r
+#define RMT_RX_FILTER_EN_CH2_S 7\r
+/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to continue sending from the first data to the\r
+ last data in channel2.*/\r
+#define RMT_TX_CONTI_MODE_CH2 (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH2_M (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH2_V 0x1\r
+#define RMT_TX_CONTI_MODE_CH2_S 6\r
+/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: This is the mark of channel2's ram usage right.1'b1：receiver\r
+ uses the ram 0：transmitter uses the ram*/\r
+#define RMT_MEM_OWNER_CH2 (BIT(5))\r
+#define RMT_MEM_OWNER_CH2_M (BIT(5))\r
+#define RMT_MEM_OWNER_CH2_V 0x1\r
+#define RMT_MEM_OWNER_CH2_S 5\r
+/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/\r
+#define RMT_APB_MEM_RST_CH2 (BIT(4))\r
+#define RMT_APB_MEM_RST_CH2_M (BIT(4))\r
+#define RMT_APB_MEM_RST_CH2_V 0x1\r
+#define RMT_APB_MEM_RST_CH2_S 4\r
+/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/\r
+#define RMT_MEM_RD_RST_CH2 (BIT(3))\r
+#define RMT_MEM_RD_RST_CH2_M (BIT(3))\r
+#define RMT_MEM_RD_RST_CH2_V 0x1\r
+#define RMT_MEM_RD_RST_CH2_S 3\r
+/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset write ram address for channel2 by receiver access.*/\r
+#define RMT_MEM_WR_RST_CH2 (BIT(2))\r
+#define RMT_MEM_WR_RST_CH2_M (BIT(2))\r
+#define RMT_MEM_WR_RST_CH2_V 0x1\r
+#define RMT_MEM_WR_RST_CH2_S 2\r
+/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
+/*description: Set this bit to enbale receving data for channel2.*/\r
+#define RMT_RX_EN_CH2 (BIT(1))\r
+#define RMT_RX_EN_CH2_M (BIT(1))\r
+#define RMT_RX_EN_CH2_V 0x1\r
+#define RMT_RX_EN_CH2_S 1\r
+/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to start sending data for channel2.*/\r
+#define RMT_TX_START_CH2 (BIT(0))\r
+#define RMT_TX_START_CH2_M (BIT(0))\r
+#define RMT_TX_START_CH2_V 0x1\r
+#define RMT_TX_START_CH2_S 0\r
+\r
+#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x0038)\r
+/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
+/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add\r
+ on low level 1'b0:add on high level.*/\r
+#define RMT_CARRIER_OUT_LV_CH3 (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH3_M (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH3_V 0x1\r
+#define RMT_CARRIER_OUT_LV_CH3_S 29\r
+/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: This is the carrier modulation enable control bit for channel3.*/\r
+#define RMT_CARRIER_EN_CH3 (BIT(28))\r
+#define RMT_CARRIER_EN_CH3_M (BIT(28))\r
+#define RMT_CARRIER_EN_CH3_V 0x1\r
+#define RMT_CARRIER_EN_CH3_S 28\r
+/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel3.*/\r
+#define RMT_MEM_SIZE_CH3 0x0000000F\r
+#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S))\r
+#define RMT_MEM_SIZE_CH3_V 0xF\r
+#define RMT_MEM_SIZE_CH3_S 24\r
+/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3\r
+ then the receive process is done.*/\r
+#define RMT_IDLE_THRES_CH3 0x0000FFFF\r
+#define RMT_IDLE_THRES_CH3_M ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S))\r
+#define RMT_IDLE_THRES_CH3_V 0xFFFF\r
+#define RMT_IDLE_THRES_CH3_S 8\r
+/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
+/*description: This register is used to configure the frequency divider's factor in channel3.*/\r
+#define RMT_DIV_CNT_CH3 0x000000FF\r
+#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S))\r
+#define RMT_DIV_CNT_CH3_V 0xFF\r
+#define RMT_DIV_CNT_CH3_S 0\r
+\r
+#define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x003c)\r
+/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for channel3 in IDLE state.*/\r
+#define RMT_IDLE_OUT_EN_CH3 (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH3_M (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH3_V 0x1\r
+#define RMT_IDLE_OUT_EN_CH3_S 19\r
+/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This bit configures the output signal's level for channel3 in IDLE state.*/\r
+#define RMT_IDLE_OUT_LV_CH3 (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH3_M (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH3_V 0x1\r
+#define RMT_IDLE_OUT_LV_CH3_S 18\r
+/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
+#define RMT_REF_ALWAYS_ON_CH3 (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH3_M (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH3_V 0x1\r
+#define RMT_REF_ALWAYS_ON_CH3_S 17\r
+/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This bit is used to reset divider in channel3.*/\r
+#define RMT_REF_CNT_RST_CH3 (BIT(16))\r
+#define RMT_REF_CNT_RST_CH3_M (BIT(16))\r
+#define RMT_REF_CNT_RST_CH3_V 0x1\r
+#define RMT_REF_CNT_RST_CH3_S 16\r
+/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
+/*description: in receive mode channel3 ignore input pulse when the pulse width\r
+ is smaller then this value.*/\r
+#define RMT_RX_FILTER_THRES_CH3 0x000000FF\r
+#define RMT_RX_FILTER_THRES_CH3_M ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S))\r
+#define RMT_RX_FILTER_THRES_CH3_V 0xFF\r
+#define RMT_RX_FILTER_THRES_CH3_S 8\r
+/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the receive filter enable bit for channel3.*/\r
+#define RMT_RX_FILTER_EN_CH3 (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH3_M (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH3_V 0x1\r
+#define RMT_RX_FILTER_EN_CH3_S 7\r
+/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to continue sending from the first data to the\r
+ last data in channel3.*/\r
+#define RMT_TX_CONTI_MODE_CH3 (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH3_M (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH3_V 0x1\r
+#define RMT_TX_CONTI_MODE_CH3_S 6\r
+/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: This is the mark of channel3's ram usage right.1'b1：receiver\r
+ uses the ram 0：transmitter uses the ram*/\r
+#define RMT_MEM_OWNER_CH3 (BIT(5))\r
+#define RMT_MEM_OWNER_CH3_M (BIT(5))\r
+#define RMT_MEM_OWNER_CH3_V 0x1\r
+#define RMT_MEM_OWNER_CH3_S 5\r
+/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/\r
+#define RMT_APB_MEM_RST_CH3 (BIT(4))\r
+#define RMT_APB_MEM_RST_CH3_M (BIT(4))\r
+#define RMT_APB_MEM_RST_CH3_V 0x1\r
+#define RMT_APB_MEM_RST_CH3_S 4\r
+/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/\r
+#define RMT_MEM_RD_RST_CH3 (BIT(3))\r
+#define RMT_MEM_RD_RST_CH3_M (BIT(3))\r
+#define RMT_MEM_RD_RST_CH3_V 0x1\r
+#define RMT_MEM_RD_RST_CH3_S 3\r
+/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset write ram address for channel3 by receiver access.*/\r
+#define RMT_MEM_WR_RST_CH3 (BIT(2))\r
+#define RMT_MEM_WR_RST_CH3_M (BIT(2))\r
+#define RMT_MEM_WR_RST_CH3_V 0x1\r
+#define RMT_MEM_WR_RST_CH3_S 2\r
+/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
+/*description: Set this bit to enbale receving data for channel3.*/\r
+#define RMT_RX_EN_CH3 (BIT(1))\r
+#define RMT_RX_EN_CH3_M (BIT(1))\r
+#define RMT_RX_EN_CH3_V 0x1\r
+#define RMT_RX_EN_CH3_S 1\r
+/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to start sending data for channel3.*/\r
+#define RMT_TX_START_CH3 (BIT(0))\r
+#define RMT_TX_START_CH3_M (BIT(0))\r
+#define RMT_TX_START_CH3_V 0x1\r
+#define RMT_TX_START_CH3_S 0\r
+\r
+#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0040)\r
+/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
+/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add\r
+ on low level 1'b0:add on high level.*/\r
+#define RMT_CARRIER_OUT_LV_CH4 (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH4_V 0x1\r
+#define RMT_CARRIER_OUT_LV_CH4_S 29\r
+/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: This is the carrier modulation enable control bit for channel4.*/\r
+#define RMT_CARRIER_EN_CH4 (BIT(28))\r
+#define RMT_CARRIER_EN_CH4_M (BIT(28))\r
+#define RMT_CARRIER_EN_CH4_V 0x1\r
+#define RMT_CARRIER_EN_CH4_S 28\r
+/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel4.*/\r
+#define RMT_MEM_SIZE_CH4 0x0000000F\r
+#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S))\r
+#define RMT_MEM_SIZE_CH4_V 0xF\r
+#define RMT_MEM_SIZE_CH4_S 24\r
+/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4\r
+ then the receive process is done.*/\r
+#define RMT_IDLE_THRES_CH4 0x0000FFFF\r
+#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S))\r
+#define RMT_IDLE_THRES_CH4_V 0xFFFF\r
+#define RMT_IDLE_THRES_CH4_S 8\r
+/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
+/*description: This register is used to configure the frequency divider's factor in channel4.*/\r
+#define RMT_DIV_CNT_CH4 0x000000FF\r
+#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S))\r
+#define RMT_DIV_CNT_CH4_V 0xFF\r
+#define RMT_DIV_CNT_CH4_S 0\r
+\r
+#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0044)\r
+/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for channel4 in IDLE state.*/\r
+#define RMT_IDLE_OUT_EN_CH4 (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH4_M (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH4_V 0x1\r
+#define RMT_IDLE_OUT_EN_CH4_S 19\r
+/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This bit configures the output signal's level for channel4 in IDLE state.*/\r
+#define RMT_IDLE_OUT_LV_CH4 (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH4_M (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH4_V 0x1\r
+#define RMT_IDLE_OUT_LV_CH4_S 18\r
+/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
+#define RMT_REF_ALWAYS_ON_CH4 (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH4_M (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH4_V 0x1\r
+#define RMT_REF_ALWAYS_ON_CH4_S 17\r
+/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This bit is used to reset divider in channel4.*/\r
+#define RMT_REF_CNT_RST_CH4 (BIT(16))\r
+#define RMT_REF_CNT_RST_CH4_M (BIT(16))\r
+#define RMT_REF_CNT_RST_CH4_V 0x1\r
+#define RMT_REF_CNT_RST_CH4_S 16\r
+/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
+/*description: in receive mode channel4 ignore input pulse when the pulse width\r
+ is smaller then this value.*/\r
+#define RMT_RX_FILTER_THRES_CH4 0x000000FF\r
+#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S))\r
+#define RMT_RX_FILTER_THRES_CH4_V 0xFF\r
+#define RMT_RX_FILTER_THRES_CH4_S 8\r
+/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the receive filter enable bit for channel4.*/\r
+#define RMT_RX_FILTER_EN_CH4 (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH4_M (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH4_V 0x1\r
+#define RMT_RX_FILTER_EN_CH4_S 7\r
+/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to continue sending from the first data to the\r
+ last data in channel4.*/\r
+#define RMT_TX_CONTI_MODE_CH4 (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH4_M (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH4_V 0x1\r
+#define RMT_TX_CONTI_MODE_CH4_S 6\r
+/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: This is the mark of channel4's ram usage right.1'b1：receiver\r
+ uses the ram 0：transmitter uses the ram*/\r
+#define RMT_MEM_OWNER_CH4 (BIT(5))\r
+#define RMT_MEM_OWNER_CH4_M (BIT(5))\r
+#define RMT_MEM_OWNER_CH4_V 0x1\r
+#define RMT_MEM_OWNER_CH4_S 5\r
+/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/\r
+#define RMT_APB_MEM_RST_CH4 (BIT(4))\r
+#define RMT_APB_MEM_RST_CH4_M (BIT(4))\r
+#define RMT_APB_MEM_RST_CH4_V 0x1\r
+#define RMT_APB_MEM_RST_CH4_S 4\r
+/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/\r
+#define RMT_MEM_RD_RST_CH4 (BIT(3))\r
+#define RMT_MEM_RD_RST_CH4_M (BIT(3))\r
+#define RMT_MEM_RD_RST_CH4_V 0x1\r
+#define RMT_MEM_RD_RST_CH4_S 3\r
+/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset write ram address for channel4 by receiver access.*/\r
+#define RMT_MEM_WR_RST_CH4 (BIT(2))\r
+#define RMT_MEM_WR_RST_CH4_M (BIT(2))\r
+#define RMT_MEM_WR_RST_CH4_V 0x1\r
+#define RMT_MEM_WR_RST_CH4_S 2\r
+/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
+/*description: Set this bit to enbale receving data for channel4.*/\r
+#define RMT_RX_EN_CH4 (BIT(1))\r
+#define RMT_RX_EN_CH4_M (BIT(1))\r
+#define RMT_RX_EN_CH4_V 0x1\r
+#define RMT_RX_EN_CH4_S 1\r
+/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to start sending data for channel4.*/\r
+#define RMT_TX_START_CH4 (BIT(0))\r
+#define RMT_TX_START_CH4_M (BIT(0))\r
+#define RMT_TX_START_CH4_V 0x1\r
+#define RMT_TX_START_CH4_S 0\r
+\r
+#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0048)\r
+/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
+/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add\r
+ on low level 1'b0:add on high level.*/\r
+#define RMT_CARRIER_OUT_LV_CH5 (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH5_V 0x1\r
+#define RMT_CARRIER_OUT_LV_CH5_S 29\r
+/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: This is the carrier modulation enable control bit for channel5.*/\r
+#define RMT_CARRIER_EN_CH5 (BIT(28))\r
+#define RMT_CARRIER_EN_CH5_M (BIT(28))\r
+#define RMT_CARRIER_EN_CH5_V 0x1\r
+#define RMT_CARRIER_EN_CH5_S 28\r
+/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel5.*/\r
+#define RMT_MEM_SIZE_CH5 0x0000000F\r
+#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S))\r
+#define RMT_MEM_SIZE_CH5_V 0xF\r
+#define RMT_MEM_SIZE_CH5_S 24\r
+/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5\r
+ then the receive process is done.*/\r
+#define RMT_IDLE_THRES_CH5 0x0000FFFF\r
+#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S))\r
+#define RMT_IDLE_THRES_CH5_V 0xFFFF\r
+#define RMT_IDLE_THRES_CH5_S 8\r
+/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
+/*description: This register is used to configure the frequency divider's factor in channel5.*/\r
+#define RMT_DIV_CNT_CH5 0x000000FF\r
+#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S))\r
+#define RMT_DIV_CNT_CH5_V 0xFF\r
+#define RMT_DIV_CNT_CH5_S 0\r
+\r
+#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x004c)\r
+/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for channel5 in IDLE state.*/\r
+#define RMT_IDLE_OUT_EN_CH5 (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH5_M (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH5_V 0x1\r
+#define RMT_IDLE_OUT_EN_CH5_S 19\r
+/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This bit configures the output signal's level for channel5 in IDLE state.*/\r
+#define RMT_IDLE_OUT_LV_CH5 (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH5_M (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH5_V 0x1\r
+#define RMT_IDLE_OUT_LV_CH5_S 18\r
+/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
+#define RMT_REF_ALWAYS_ON_CH5 (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH5_M (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH5_V 0x1\r
+#define RMT_REF_ALWAYS_ON_CH5_S 17\r
+/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This bit is used to reset divider in channel5.*/\r
+#define RMT_REF_CNT_RST_CH5 (BIT(16))\r
+#define RMT_REF_CNT_RST_CH5_M (BIT(16))\r
+#define RMT_REF_CNT_RST_CH5_V 0x1\r
+#define RMT_REF_CNT_RST_CH5_S 16\r
+/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
+/*description: in receive mode channel5 ignore input pulse when the pulse width\r
+ is smaller then this value.*/\r
+#define RMT_RX_FILTER_THRES_CH5 0x000000FF\r
+#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S))\r
+#define RMT_RX_FILTER_THRES_CH5_V 0xFF\r
+#define RMT_RX_FILTER_THRES_CH5_S 8\r
+/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the receive filter enable bit for channel5.*/\r
+#define RMT_RX_FILTER_EN_CH5 (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH5_M (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH5_V 0x1\r
+#define RMT_RX_FILTER_EN_CH5_S 7\r
+/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to continue sending from the first data to the\r
+ last data in channel5.*/\r
+#define RMT_TX_CONTI_MODE_CH5 (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH5_M (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH5_V 0x1\r
+#define RMT_TX_CONTI_MODE_CH5_S 6\r
+/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: This is the mark of channel5's ram usage right.1'b1：receiver\r
+ uses the ram 0：transmitter uses the ram*/\r
+#define RMT_MEM_OWNER_CH5 (BIT(5))\r
+#define RMT_MEM_OWNER_CH5_M (BIT(5))\r
+#define RMT_MEM_OWNER_CH5_V 0x1\r
+#define RMT_MEM_OWNER_CH5_S 5\r
+/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/\r
+#define RMT_APB_MEM_RST_CH5 (BIT(4))\r
+#define RMT_APB_MEM_RST_CH5_M (BIT(4))\r
+#define RMT_APB_MEM_RST_CH5_V 0x1\r
+#define RMT_APB_MEM_RST_CH5_S 4\r
+/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/\r
+#define RMT_MEM_RD_RST_CH5 (BIT(3))\r
+#define RMT_MEM_RD_RST_CH5_M (BIT(3))\r
+#define RMT_MEM_RD_RST_CH5_V 0x1\r
+#define RMT_MEM_RD_RST_CH5_S 3\r
+/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset write ram address for channel5 by receiver access.*/\r
+#define RMT_MEM_WR_RST_CH5 (BIT(2))\r
+#define RMT_MEM_WR_RST_CH5_M (BIT(2))\r
+#define RMT_MEM_WR_RST_CH5_V 0x1\r
+#define RMT_MEM_WR_RST_CH5_S 2\r
+/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
+/*description: Set this bit to enbale receving data for channel5.*/\r
+#define RMT_RX_EN_CH5 (BIT(1))\r
+#define RMT_RX_EN_CH5_M (BIT(1))\r
+#define RMT_RX_EN_CH5_V 0x1\r
+#define RMT_RX_EN_CH5_S 1\r
+/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to start sending data for channel5.*/\r
+#define RMT_TX_START_CH5 (BIT(0))\r
+#define RMT_TX_START_CH5_M (BIT(0))\r
+#define RMT_TX_START_CH5_V 0x1\r
+#define RMT_TX_START_CH5_S 0\r
+\r
+#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0050)\r
+/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
+/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add\r
+ on low level 1'b0:add on high level.*/\r
+#define RMT_CARRIER_OUT_LV_CH6 (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH6_V 0x1\r
+#define RMT_CARRIER_OUT_LV_CH6_S 29\r
+/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: This is the carrier modulation enable control bit for channel6.*/\r
+#define RMT_CARRIER_EN_CH6 (BIT(28))\r
+#define RMT_CARRIER_EN_CH6_M (BIT(28))\r
+#define RMT_CARRIER_EN_CH6_V 0x1\r
+#define RMT_CARRIER_EN_CH6_S 28\r
+/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel6.*/\r
+#define RMT_MEM_SIZE_CH6 0x0000000F\r
+#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S))\r
+#define RMT_MEM_SIZE_CH6_V 0xF\r
+#define RMT_MEM_SIZE_CH6_S 24\r
+/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6\r
+ then the receive process is done.*/\r
+#define RMT_IDLE_THRES_CH6 0x0000FFFF\r
+#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S))\r
+#define RMT_IDLE_THRES_CH6_V 0xFFFF\r
+#define RMT_IDLE_THRES_CH6_S 8\r
+/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
+/*description: This register is used to configure the frequency divider's factor in channel6.*/\r
+#define RMT_DIV_CNT_CH6 0x000000FF\r
+#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S))\r
+#define RMT_DIV_CNT_CH6_V 0xFF\r
+#define RMT_DIV_CNT_CH6_S 0\r
+\r
+#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0054)\r
+/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for channel6 in IDLE state.*/\r
+#define RMT_IDLE_OUT_EN_CH6 (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH6_M (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH6_V 0x1\r
+#define RMT_IDLE_OUT_EN_CH6_S 19\r
+/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This bit configures the output signal's level for channel6 in IDLE state.*/\r
+#define RMT_IDLE_OUT_LV_CH6 (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH6_M (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH6_V 0x1\r
+#define RMT_IDLE_OUT_LV_CH6_S 18\r
+/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
+#define RMT_REF_ALWAYS_ON_CH6 (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH6_M (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH6_V 0x1\r
+#define RMT_REF_ALWAYS_ON_CH6_S 17\r
+/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This bit is used to reset divider in channel6.*/\r
+#define RMT_REF_CNT_RST_CH6 (BIT(16))\r
+#define RMT_REF_CNT_RST_CH6_M (BIT(16))\r
+#define RMT_REF_CNT_RST_CH6_V 0x1\r
+#define RMT_REF_CNT_RST_CH6_S 16\r
+/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
+/*description: in receive mode channel6 ignore input pulse when the pulse width\r
+ is smaller then this value.*/\r
+#define RMT_RX_FILTER_THRES_CH6 0x000000FF\r
+#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S))\r
+#define RMT_RX_FILTER_THRES_CH6_V 0xFF\r
+#define RMT_RX_FILTER_THRES_CH6_S 8\r
+/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the receive filter enable bit for channel6.*/\r
+#define RMT_RX_FILTER_EN_CH6 (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH6_M (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH6_V 0x1\r
+#define RMT_RX_FILTER_EN_CH6_S 7\r
+/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to continue sending from the first data to the\r
+ last data in channel6.*/\r
+#define RMT_TX_CONTI_MODE_CH6 (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH6_M (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH6_V 0x1\r
+#define RMT_TX_CONTI_MODE_CH6_S 6\r
+/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: This is the mark of channel6's ram usage right.1'b1：receiver\r
+ uses the ram 0：transmitter uses the ram*/\r
+#define RMT_MEM_OWNER_CH6 (BIT(5))\r
+#define RMT_MEM_OWNER_CH6_M (BIT(5))\r
+#define RMT_MEM_OWNER_CH6_V 0x1\r
+#define RMT_MEM_OWNER_CH6_S 5\r
+/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/\r
+#define RMT_APB_MEM_RST_CH6 (BIT(4))\r
+#define RMT_APB_MEM_RST_CH6_M (BIT(4))\r
+#define RMT_APB_MEM_RST_CH6_V 0x1\r
+#define RMT_APB_MEM_RST_CH6_S 4\r
+/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/\r
+#define RMT_MEM_RD_RST_CH6 (BIT(3))\r
+#define RMT_MEM_RD_RST_CH6_M (BIT(3))\r
+#define RMT_MEM_RD_RST_CH6_V 0x1\r
+#define RMT_MEM_RD_RST_CH6_S 3\r
+/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset write ram address for channel6 by receiver access.*/\r
+#define RMT_MEM_WR_RST_CH6 (BIT(2))\r
+#define RMT_MEM_WR_RST_CH6_M (BIT(2))\r
+#define RMT_MEM_WR_RST_CH6_V 0x1\r
+#define RMT_MEM_WR_RST_CH6_S 2\r
+/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
+/*description: Set this bit to enbale receving data for channel6.*/\r
+#define RMT_RX_EN_CH6 (BIT(1))\r
+#define RMT_RX_EN_CH6_M (BIT(1))\r
+#define RMT_RX_EN_CH6_V 0x1\r
+#define RMT_RX_EN_CH6_S 1\r
+/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to start sending data for channel6.*/\r
+#define RMT_TX_START_CH6 (BIT(0))\r
+#define RMT_TX_START_CH6_M (BIT(0))\r
+#define RMT_TX_START_CH6_V 0x1\r
+#define RMT_TX_START_CH6_S 0\r
+\r
+#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0058)\r
+/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */\r
+/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add\r
+ on low level 1'b0:add on high level.*/\r
+#define RMT_CARRIER_OUT_LV_CH7 (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29))\r
+#define RMT_CARRIER_OUT_LV_CH7_V 0x1\r
+#define RMT_CARRIER_OUT_LV_CH7_S 29\r
+/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: This is the carrier modulation enable control bit for channel7.*/\r
+#define RMT_CARRIER_EN_CH7 (BIT(28))\r
+#define RMT_CARRIER_EN_CH7_M (BIT(28))\r
+#define RMT_CARRIER_EN_CH7_V 0x1\r
+#define RMT_CARRIER_EN_CH7_S 28\r
+/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the the amount of memory blocks\r
+ allocated to channel7.*/\r
+#define RMT_MEM_SIZE_CH7 0x0000000F\r
+#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S))\r
+#define RMT_MEM_SIZE_CH7_V 0xF\r
+#define RMT_MEM_SIZE_CH7_S 24\r
+/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */\r
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7\r
+ then the receive process is done.*/\r
+#define RMT_IDLE_THRES_CH7 0x0000FFFF\r
+#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S))\r
+#define RMT_IDLE_THRES_CH7_V 0xFFFF\r
+#define RMT_IDLE_THRES_CH7_S 8\r
+/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */\r
+/*description: This register is used to configure the frequency divider's factor in channel7.*/\r
+#define RMT_DIV_CNT_CH7 0x000000FF\r
+#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S))\r
+#define RMT_DIV_CNT_CH7_V 0xFF\r
+#define RMT_DIV_CNT_CH7_S 0\r
+\r
+#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x005c)\r
+/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: This is the output enable control bit for channel6 in IDLE state.*/\r
+#define RMT_IDLE_OUT_EN_CH7 (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH7_M (BIT(19))\r
+#define RMT_IDLE_OUT_EN_CH7_V 0x1\r
+#define RMT_IDLE_OUT_EN_CH7_S 19\r
+/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This bit configures the output signal's level for channel7 in IDLE state.*/\r
+#define RMT_IDLE_OUT_LV_CH7 (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH7_M (BIT(18))\r
+#define RMT_IDLE_OUT_LV_CH7_V 0x1\r
+#define RMT_IDLE_OUT_LV_CH7_S 18\r
+/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/\r
+#define RMT_REF_ALWAYS_ON_CH7 (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH7_M (BIT(17))\r
+#define RMT_REF_ALWAYS_ON_CH7_V 0x1\r
+#define RMT_REF_ALWAYS_ON_CH7_S 17\r
+/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This bit is used to reset divider in channel7.*/\r
+#define RMT_REF_CNT_RST_CH7 (BIT(16))\r
+#define RMT_REF_CNT_RST_CH7_M (BIT(16))\r
+#define RMT_REF_CNT_RST_CH7_V 0x1\r
+#define RMT_REF_CNT_RST_CH7_S 16\r
+/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */\r
+/*description: in receive mode channel7 ignore input pulse when the pulse width\r
+ is smaller then this value.*/\r
+#define RMT_RX_FILTER_THRES_CH7 0x000000FF\r
+#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S))\r
+#define RMT_RX_FILTER_THRES_CH7_V 0xFF\r
+#define RMT_RX_FILTER_THRES_CH7_S 8\r
+/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the receive filter enable bit for channel7.*/\r
+#define RMT_RX_FILTER_EN_CH7 (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH7_M (BIT(7))\r
+#define RMT_RX_FILTER_EN_CH7_V 0x1\r
+#define RMT_RX_FILTER_EN_CH7_S 7\r
+/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to continue sending from the first data to the\r
+ last data in channel7.*/\r
+#define RMT_TX_CONTI_MODE_CH7 (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH7_M (BIT(6))\r
+#define RMT_TX_CONTI_MODE_CH7_V 0x1\r
+#define RMT_TX_CONTI_MODE_CH7_S 6\r
+/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: This is the mark of channel7's ram usage right.1'b1：receiver\r
+ uses the ram 0：transmitter uses the ram*/\r
+#define RMT_MEM_OWNER_CH7 (BIT(5))\r
+#define RMT_MEM_OWNER_CH7_M (BIT(5))\r
+#define RMT_MEM_OWNER_CH7_V 0x1\r
+#define RMT_MEM_OWNER_CH7_S 5\r
+/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/\r
+#define RMT_APB_MEM_RST_CH7 (BIT(4))\r
+#define RMT_APB_MEM_RST_CH7_M (BIT(4))\r
+#define RMT_APB_MEM_RST_CH7_V 0x1\r
+#define RMT_APB_MEM_RST_CH7_S 4\r
+/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/\r
+#define RMT_MEM_RD_RST_CH7 (BIT(3))\r
+#define RMT_MEM_RD_RST_CH7_M (BIT(3))\r
+#define RMT_MEM_RD_RST_CH7_V 0x1\r
+#define RMT_MEM_RD_RST_CH7_S 3\r
+/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset write ram address for channel7 by receiver access.*/\r
+#define RMT_MEM_WR_RST_CH7 (BIT(2))\r
+#define RMT_MEM_WR_RST_CH7_M (BIT(2))\r
+#define RMT_MEM_WR_RST_CH7_V 0x1\r
+#define RMT_MEM_WR_RST_CH7_S 2\r
+/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */\r
+/*description: Set this bit to enbale receving data for channel7.*/\r
+#define RMT_RX_EN_CH7 (BIT(1))\r
+#define RMT_RX_EN_CH7_M (BIT(1))\r
+#define RMT_RX_EN_CH7_V 0x1\r
+#define RMT_RX_EN_CH7_S 1\r
+/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to start sending data for channel7.*/\r
+#define RMT_TX_START_CH7 (BIT(0))\r
+#define RMT_TX_START_CH7_M (BIT(0))\r
+#define RMT_TX_START_CH7_V 0x1\r
+#define RMT_TX_START_CH7_S 0\r
+\r
+#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0060)\r
+/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The status for channel0*/\r
+#define RMT_STATUS_CH0 0xFFFFFFFF\r
+#define RMT_STATUS_CH0_M ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S))\r
+#define RMT_STATUS_CH0_V 0xFFFFFFFF\r
+#define RMT_STATUS_CH0_S 0\r
+\r
+#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0064)\r
+/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The status for channel1*/\r
+#define RMT_STATUS_CH1 0xFFFFFFFF\r
+#define RMT_STATUS_CH1_M ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S))\r
+#define RMT_STATUS_CH1_V 0xFFFFFFFF\r
+#define RMT_STATUS_CH1_S 0\r
+\r
+#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0068)\r
+/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The status for channel2*/\r
+#define RMT_STATUS_CH2 0xFFFFFFFF\r
+#define RMT_STATUS_CH2_M ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S))\r
+#define RMT_STATUS_CH2_V 0xFFFFFFFF\r
+#define RMT_STATUS_CH2_S 0\r
+\r
+#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x006c)\r
+/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The status for channel3*/\r
+#define RMT_STATUS_CH3 0xFFFFFFFF\r
+#define RMT_STATUS_CH3_M ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S))\r
+#define RMT_STATUS_CH3_V 0xFFFFFFFF\r
+#define RMT_STATUS_CH3_S 0\r
+\r
+#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0070)\r
+/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The status for channel4*/\r
+#define RMT_STATUS_CH4 0xFFFFFFFF\r
+#define RMT_STATUS_CH4_M ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S))\r
+#define RMT_STATUS_CH4_V 0xFFFFFFFF\r
+#define RMT_STATUS_CH4_S 0\r
+\r
+#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0074)\r
+/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The status for channel5*/\r
+#define RMT_STATUS_CH5 0xFFFFFFFF\r
+#define RMT_STATUS_CH5_M ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S))\r
+#define RMT_STATUS_CH5_V 0xFFFFFFFF\r
+#define RMT_STATUS_CH5_S 0\r
+\r
+#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0078)\r
+/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The status for channel6*/\r
+#define RMT_STATUS_CH6 0xFFFFFFFF\r
+#define RMT_STATUS_CH6_M ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S))\r
+#define RMT_STATUS_CH6_V 0xFFFFFFFF\r
+#define RMT_STATUS_CH6_S 0\r
+\r
+#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x007c)\r
+/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The status for channel7*/\r
+#define RMT_STATUS_CH7 0xFFFFFFFF\r
+#define RMT_STATUS_CH7_M ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S))\r
+#define RMT_STATUS_CH7_V 0xFFFFFFFF\r
+#define RMT_STATUS_CH7_S 0\r
+\r
+#define RMT_CH0ADDR_REG (DR_REG_RMT_BASE + 0x0080)\r
+/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The ram relative address in channel0 by apb fifo access*/\r
+#define RMT_APB_MEM_ADDR_CH0 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH0_M ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S))\r
+#define RMT_APB_MEM_ADDR_CH0_V 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH0_S 0\r
+\r
+#define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x0084)\r
+/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The ram relative address in channel1 by apb fifo access*/\r
+#define RMT_APB_MEM_ADDR_CH1 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH1_M ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S))\r
+#define RMT_APB_MEM_ADDR_CH1_V 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH1_S 0\r
+\r
+#define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x0088)\r
+/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The ram relative address in channel2 by apb fifo access*/\r
+#define RMT_APB_MEM_ADDR_CH2 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH2_M ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S))\r
+#define RMT_APB_MEM_ADDR_CH2_V 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH2_S 0\r
+\r
+#define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x008c)\r
+/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The ram relative address in channel3 by apb fifo access*/\r
+#define RMT_APB_MEM_ADDR_CH3 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH3_M ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S))\r
+#define RMT_APB_MEM_ADDR_CH3_V 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH3_S 0\r
+\r
+#define RMT_CH4ADDR_REG (DR_REG_RMT_BASE + 0x0090)\r
+/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The ram relative address in channel4 by apb fifo access*/\r
+#define RMT_APB_MEM_ADDR_CH4 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH4_M ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S))\r
+#define RMT_APB_MEM_ADDR_CH4_V 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH4_S 0\r
+\r
+#define RMT_CH5ADDR_REG (DR_REG_RMT_BASE + 0x0094)\r
+/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The ram relative address in channel5 by apb fifo access*/\r
+#define RMT_APB_MEM_ADDR_CH5 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH5_M ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S))\r
+#define RMT_APB_MEM_ADDR_CH5_V 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH5_S 0\r
+\r
+#define RMT_CH6ADDR_REG (DR_REG_RMT_BASE + 0x0098)\r
+/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The ram relative address in channel6 by apb fifo access*/\r
+#define RMT_APB_MEM_ADDR_CH6 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH6_M ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S))\r
+#define RMT_APB_MEM_ADDR_CH6_V 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH6_S 0\r
+\r
+#define RMT_CH7ADDR_REG (DR_REG_RMT_BASE + 0x009c)\r
+/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: The ram relative address in channel7 by apb fifo access*/\r
+#define RMT_APB_MEM_ADDR_CH7 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH7_M ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S))\r
+#define RMT_APB_MEM_ADDR_CH7_V 0xFFFFFFFF\r
+#define RMT_APB_MEM_ADDR_CH7_S 0\r
+\r
+#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x00a0)\r
+/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 7 turns to high level when\r
+ transmitter in channle7 have send datas more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old datas with new datas.*/\r
+#define RMT_CH7_TX_THR_EVENT_INT_RAW (BIT(31))\r
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_M (BIT(31))\r
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_V 0x1\r
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_S 31\r
+/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 6 turns to high level when\r
+ transmitter in channle6 have send datas more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old datas with new datas.*/\r
+#define RMT_CH6_TX_THR_EVENT_INT_RAW (BIT(30))\r
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_M (BIT(30))\r
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_V 0x1\r
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_S 30\r
+/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 5 turns to high level when\r
+ transmitter in channle5 have send datas more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old datas with new datas.*/\r
+#define RMT_CH5_TX_THR_EVENT_INT_RAW (BIT(29))\r
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_M (BIT(29))\r
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_V 0x1\r
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_S 29\r
+/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 4 turns to high level when\r
+ transmitter in channle4 have send datas more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old datas with new datas.*/\r
+#define RMT_CH4_TX_THR_EVENT_INT_RAW (BIT(28))\r
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_M (BIT(28))\r
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_V 0x1\r
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_S 28\r
+/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 3 turns to high level when\r
+ transmitter in channle3 have send datas more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old datas with new datas.*/\r
+#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(27))\r
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(27))\r
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1\r
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 27\r
+/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 2 turns to high level when\r
+ transmitter in channle2 have send datas more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old datas with new datas.*/\r
+#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(26))\r
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(26))\r
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1\r
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 26\r
+/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 1 turns to high level when\r
+ transmitter in channle1 have send datas more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old datas with new datas.*/\r
+#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(25))\r
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(25))\r
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1\r
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 25\r
+/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 0 turns to high level when\r
+ transmitter in channle0 have send datas more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old datas with new datas.*/\r
+#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(24))\r
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(24))\r
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1\r
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 24\r
+/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 7 turns to high level when\r
+ channle 7 detects some errors.*/\r
+#define RMT_CH7_ERR_INT_RAW (BIT(23))\r
+#define RMT_CH7_ERR_INT_RAW_M (BIT(23))\r
+#define RMT_CH7_ERR_INT_RAW_V 0x1\r
+#define RMT_CH7_ERR_INT_RAW_S 23\r
+/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 7 turns to high level when\r
+ the receive process is done.*/\r
+#define RMT_CH7_RX_END_INT_RAW (BIT(22))\r
+#define RMT_CH7_RX_END_INT_RAW_M (BIT(22))\r
+#define RMT_CH7_RX_END_INT_RAW_V 0x1\r
+#define RMT_CH7_RX_END_INT_RAW_S 22\r
+/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 7 turns to high level when\r
+ the transmit process is done.*/\r
+#define RMT_CH7_TX_END_INT_RAW (BIT(21))\r
+#define RMT_CH7_TX_END_INT_RAW_M (BIT(21))\r
+#define RMT_CH7_TX_END_INT_RAW_V 0x1\r
+#define RMT_CH7_TX_END_INT_RAW_S 21\r
+/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 6 turns to high level when\r
+ channle 6 detects some errors.*/\r
+#define RMT_CH6_ERR_INT_RAW (BIT(20))\r
+#define RMT_CH6_ERR_INT_RAW_M (BIT(20))\r
+#define RMT_CH6_ERR_INT_RAW_V 0x1\r
+#define RMT_CH6_ERR_INT_RAW_S 20\r
+/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 6 turns to high level when\r
+ the receive process is done.*/\r
+#define RMT_CH6_RX_END_INT_RAW (BIT(19))\r
+#define RMT_CH6_RX_END_INT_RAW_M (BIT(19))\r
+#define RMT_CH6_RX_END_INT_RAW_V 0x1\r
+#define RMT_CH6_RX_END_INT_RAW_S 19\r
+/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 6 turns to high level when\r
+ the transmit process is done.*/\r
+#define RMT_CH6_TX_END_INT_RAW (BIT(18))\r
+#define RMT_CH6_TX_END_INT_RAW_M (BIT(18))\r
+#define RMT_CH6_TX_END_INT_RAW_V 0x1\r
+#define RMT_CH6_TX_END_INT_RAW_S 18\r
+/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 5 turns to high level when\r
+ channle 5 detects some errors.*/\r
+#define RMT_CH5_ERR_INT_RAW (BIT(17))\r
+#define RMT_CH5_ERR_INT_RAW_M (BIT(17))\r
+#define RMT_CH5_ERR_INT_RAW_V 0x1\r
+#define RMT_CH5_ERR_INT_RAW_S 17\r
+/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 5 turns to high level when\r
+ the receive process is done.*/\r
+#define RMT_CH5_RX_END_INT_RAW (BIT(16))\r
+#define RMT_CH5_RX_END_INT_RAW_M (BIT(16))\r
+#define RMT_CH5_RX_END_INT_RAW_V 0x1\r
+#define RMT_CH5_RX_END_INT_RAW_S 16\r
+/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 5 turns to high level when\r
+ the transmit process is done.*/\r
+#define RMT_CH5_TX_END_INT_RAW (BIT(15))\r
+#define RMT_CH5_TX_END_INT_RAW_M (BIT(15))\r
+#define RMT_CH5_TX_END_INT_RAW_V 0x1\r
+#define RMT_CH5_TX_END_INT_RAW_S 15\r
+/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 4 turns to high level when\r
+ channle 4 detects some errors.*/\r
+#define RMT_CH4_ERR_INT_RAW (BIT(14))\r
+#define RMT_CH4_ERR_INT_RAW_M (BIT(14))\r
+#define RMT_CH4_ERR_INT_RAW_V 0x1\r
+#define RMT_CH4_ERR_INT_RAW_S 14\r
+/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 4 turns to high level when\r
+ the receive process is done.*/\r
+#define RMT_CH4_RX_END_INT_RAW (BIT(13))\r
+#define RMT_CH4_RX_END_INT_RAW_M (BIT(13))\r
+#define RMT_CH4_RX_END_INT_RAW_V 0x1\r
+#define RMT_CH4_RX_END_INT_RAW_S 13\r
+/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 4 turns to high level when\r
+ the transmit process is done.*/\r
+#define RMT_CH4_TX_END_INT_RAW (BIT(12))\r
+#define RMT_CH4_TX_END_INT_RAW_M (BIT(12))\r
+#define RMT_CH4_TX_END_INT_RAW_V 0x1\r
+#define RMT_CH4_TX_END_INT_RAW_S 12\r
+/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 3 turns to high level when\r
+ channle 3 detects some errors.*/\r
+#define RMT_CH3_ERR_INT_RAW (BIT(11))\r
+#define RMT_CH3_ERR_INT_RAW_M (BIT(11))\r
+#define RMT_CH3_ERR_INT_RAW_V 0x1\r
+#define RMT_CH3_ERR_INT_RAW_S 11\r
+/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 3 turns to high level when\r
+ the receive process is done.*/\r
+#define RMT_CH3_RX_END_INT_RAW (BIT(10))\r
+#define RMT_CH3_RX_END_INT_RAW_M (BIT(10))\r
+#define RMT_CH3_RX_END_INT_RAW_V 0x1\r
+#define RMT_CH3_RX_END_INT_RAW_S 10\r
+/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 3 turns to high level when\r
+ the transmit process is done.*/\r
+#define RMT_CH3_TX_END_INT_RAW (BIT(9))\r
+#define RMT_CH3_TX_END_INT_RAW_M (BIT(9))\r
+#define RMT_CH3_TX_END_INT_RAW_V 0x1\r
+#define RMT_CH3_TX_END_INT_RAW_S 9\r
+/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 2 turns to high level when\r
+ channle 2 detects some errors.*/\r
+#define RMT_CH2_ERR_INT_RAW (BIT(8))\r
+#define RMT_CH2_ERR_INT_RAW_M (BIT(8))\r
+#define RMT_CH2_ERR_INT_RAW_V 0x1\r
+#define RMT_CH2_ERR_INT_RAW_S 8\r
+/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 2 turns to high level when\r
+ the receive process is done.*/\r
+#define RMT_CH2_RX_END_INT_RAW (BIT(7))\r
+#define RMT_CH2_RX_END_INT_RAW_M (BIT(7))\r
+#define RMT_CH2_RX_END_INT_RAW_V 0x1\r
+#define RMT_CH2_RX_END_INT_RAW_S 7\r
+/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 2 turns to high level when\r
+ the transmit process is done.*/\r
+#define RMT_CH2_TX_END_INT_RAW (BIT(6))\r
+#define RMT_CH2_TX_END_INT_RAW_M (BIT(6))\r
+#define RMT_CH2_TX_END_INT_RAW_V 0x1\r
+#define RMT_CH2_TX_END_INT_RAW_S 6\r
+/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 1 turns to high level when\r
+ channle 1 detects some errors.*/\r
+#define RMT_CH1_ERR_INT_RAW (BIT(5))\r
+#define RMT_CH1_ERR_INT_RAW_M (BIT(5))\r
+#define RMT_CH1_ERR_INT_RAW_V 0x1\r
+#define RMT_CH1_ERR_INT_RAW_S 5\r
+/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 1 turns to high level when\r
+ the receive process is done.*/\r
+#define RMT_CH1_RX_END_INT_RAW (BIT(4))\r
+#define RMT_CH1_RX_END_INT_RAW_M (BIT(4))\r
+#define RMT_CH1_RX_END_INT_RAW_V 0x1\r
+#define RMT_CH1_RX_END_INT_RAW_S 4\r
+/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 1 turns to high level when\r
+ the transmit process is done.*/\r
+#define RMT_CH1_TX_END_INT_RAW (BIT(3))\r
+#define RMT_CH1_TX_END_INT_RAW_M (BIT(3))\r
+#define RMT_CH1_TX_END_INT_RAW_V 0x1\r
+#define RMT_CH1_TX_END_INT_RAW_S 3\r
+/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 0 turns to high level when\r
+ channle 0 detects some errors.*/\r
+#define RMT_CH0_ERR_INT_RAW (BIT(2))\r
+#define RMT_CH0_ERR_INT_RAW_M (BIT(2))\r
+#define RMT_CH0_ERR_INT_RAW_V 0x1\r
+#define RMT_CH0_ERR_INT_RAW_S 2\r
+/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 0 turns to high level when\r
+ the receive process is done.*/\r
+#define RMT_CH0_RX_END_INT_RAW (BIT(1))\r
+#define RMT_CH0_RX_END_INT_RAW_M (BIT(1))\r
+#define RMT_CH0_RX_END_INT_RAW_V 0x1\r
+#define RMT_CH0_RX_END_INT_RAW_S 1\r
+/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for channel 0 turns to high level when\r
+ the transmit process is done.*/\r
+#define RMT_CH0_TX_END_INT_RAW (BIT(0))\r
+#define RMT_CH0_TX_END_INT_RAW_M (BIT(0))\r
+#define RMT_CH0_TX_END_INT_RAW_V 0x1\r
+#define RMT_CH0_TX_END_INT_RAW_S 0\r
+\r
+#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x00a4)\r
+/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw\r
+ when mt_ch7_tx_thr_event_int_ena is set to 1.*/\r
+#define RMT_CH7_TX_THR_EVENT_INT_ST (BIT(31))\r
+#define RMT_CH7_TX_THR_EVENT_INT_ST_M (BIT(31))\r
+#define RMT_CH7_TX_THR_EVENT_INT_ST_V 0x1\r
+#define RMT_CH7_TX_THR_EVENT_INT_ST_S 31\r
+/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw\r
+ when mt_ch6_tx_thr_event_int_ena is set to 1.*/\r
+#define RMT_CH6_TX_THR_EVENT_INT_ST (BIT(30))\r
+#define RMT_CH6_TX_THR_EVENT_INT_ST_M (BIT(30))\r
+#define RMT_CH6_TX_THR_EVENT_INT_ST_V 0x1\r
+#define RMT_CH6_TX_THR_EVENT_INT_ST_S 30\r
+/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw\r
+ when mt_ch5_tx_thr_event_int_ena is set to 1.*/\r
+#define RMT_CH5_TX_THR_EVENT_INT_ST (BIT(29))\r
+#define RMT_CH5_TX_THR_EVENT_INT_ST_M (BIT(29))\r
+#define RMT_CH5_TX_THR_EVENT_INT_ST_V 0x1\r
+#define RMT_CH5_TX_THR_EVENT_INT_ST_S 29\r
+/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw\r
+ when mt_ch4_tx_thr_event_int_ena is set to 1.*/\r
+#define RMT_CH4_TX_THR_EVENT_INT_ST (BIT(28))\r
+#define RMT_CH4_TX_THR_EVENT_INT_ST_M (BIT(28))\r
+#define RMT_CH4_TX_THR_EVENT_INT_ST_V 0x1\r
+#define RMT_CH4_TX_THR_EVENT_INT_ST_S 28\r
+/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw\r
+ when mt_ch3_tx_thr_event_int_ena is set to 1.*/\r
+#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(27))\r
+#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(27))\r
+#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1\r
+#define RMT_CH3_TX_THR_EVENT_INT_ST_S 27\r
+/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw\r
+ when mt_ch2_tx_thr_event_int_ena is set to 1.*/\r
+#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(26))\r
+#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(26))\r
+#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1\r
+#define RMT_CH2_TX_THR_EVENT_INT_ST_S 26\r
+/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw\r
+ when mt_ch1_tx_thr_event_int_ena is set to 1.*/\r
+#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(25))\r
+#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(25))\r
+#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1\r
+#define RMT_CH1_TX_THR_EVENT_INT_ST_S 25\r
+/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw\r
+ when mt_ch0_tx_thr_event_int_ena is set to 1.*/\r
+#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(24))\r
+#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(24))\r
+#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1\r
+#define RMT_CH0_TX_THR_EVENT_INT_ST_S 24\r
+/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 7's rmt_ch7_err_int_raw\r
+ when rmt_ch7_err_int_ena is set to 1.*/\r
+#define RMT_CH7_ERR_INT_ST (BIT(23))\r
+#define RMT_CH7_ERR_INT_ST_M (BIT(23))\r
+#define RMT_CH7_ERR_INT_ST_V 0x1\r
+#define RMT_CH7_ERR_INT_ST_S 23\r
+/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw\r
+ when rmt_ch7_rx_end_int_ena is set to 1.*/\r
+#define RMT_CH7_RX_END_INT_ST (BIT(22))\r
+#define RMT_CH7_RX_END_INT_ST_M (BIT(22))\r
+#define RMT_CH7_RX_END_INT_ST_V 0x1\r
+#define RMT_CH7_RX_END_INT_ST_S 22\r
+/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw\r
+ when mt_ch7_tx_end_int_ena is set to 1.*/\r
+#define RMT_CH7_TX_END_INT_ST (BIT(21))\r
+#define RMT_CH7_TX_END_INT_ST_M (BIT(21))\r
+#define RMT_CH7_TX_END_INT_ST_V 0x1\r
+#define RMT_CH7_TX_END_INT_ST_S 21\r
+/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 6's rmt_ch6_err_int_raw\r
+ when rmt_ch6_err_int_ena is set to 1.*/\r
+#define RMT_CH6_ERR_INT_ST (BIT(20))\r
+#define RMT_CH6_ERR_INT_ST_M (BIT(20))\r
+#define RMT_CH6_ERR_INT_ST_V 0x1\r
+#define RMT_CH6_ERR_INT_ST_S 20\r
+/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw\r
+ when rmt_ch6_rx_end_int_ena is set to 1.*/\r
+#define RMT_CH6_RX_END_INT_ST (BIT(19))\r
+#define RMT_CH6_RX_END_INT_ST_M (BIT(19))\r
+#define RMT_CH6_RX_END_INT_ST_V 0x1\r
+#define RMT_CH6_RX_END_INT_ST_S 19\r
+/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw\r
+ when mt_ch6_tx_end_int_ena is set to 1.*/\r
+#define RMT_CH6_TX_END_INT_ST (BIT(18))\r
+#define RMT_CH6_TX_END_INT_ST_M (BIT(18))\r
+#define RMT_CH6_TX_END_INT_ST_V 0x1\r
+#define RMT_CH6_TX_END_INT_ST_S 18\r
+/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 5's rmt_ch5_err_int_raw\r
+ when rmt_ch5_err_int_ena is set to 1.*/\r
+#define RMT_CH5_ERR_INT_ST (BIT(17))\r
+#define RMT_CH5_ERR_INT_ST_M (BIT(17))\r
+#define RMT_CH5_ERR_INT_ST_V 0x1\r
+#define RMT_CH5_ERR_INT_ST_S 17\r
+/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw\r
+ when rmt_ch5_rx_end_int_ena is set to 1.*/\r
+#define RMT_CH5_RX_END_INT_ST (BIT(16))\r
+#define RMT_CH5_RX_END_INT_ST_M (BIT(16))\r
+#define RMT_CH5_RX_END_INT_ST_V 0x1\r
+#define RMT_CH5_RX_END_INT_ST_S 16\r
+/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw\r
+ when mt_ch5_tx_end_int_ena is set to 1.*/\r
+#define RMT_CH5_TX_END_INT_ST (BIT(15))\r
+#define RMT_CH5_TX_END_INT_ST_M (BIT(15))\r
+#define RMT_CH5_TX_END_INT_ST_V 0x1\r
+#define RMT_CH5_TX_END_INT_ST_S 15\r
+/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 4's rmt_ch4_err_int_raw\r
+ when rmt_ch4_err_int_ena is set to 1.*/\r
+#define RMT_CH4_ERR_INT_ST (BIT(14))\r
+#define RMT_CH4_ERR_INT_ST_M (BIT(14))\r
+#define RMT_CH4_ERR_INT_ST_V 0x1\r
+#define RMT_CH4_ERR_INT_ST_S 14\r
+/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw\r
+ when rmt_ch4_rx_end_int_ena is set to 1.*/\r
+#define RMT_CH4_RX_END_INT_ST (BIT(13))\r
+#define RMT_CH4_RX_END_INT_ST_M (BIT(13))\r
+#define RMT_CH4_RX_END_INT_ST_V 0x1\r
+#define RMT_CH4_RX_END_INT_ST_S 13\r
+/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw\r
+ when mt_ch4_tx_end_int_ena is set to 1.*/\r
+#define RMT_CH4_TX_END_INT_ST (BIT(12))\r
+#define RMT_CH4_TX_END_INT_ST_M (BIT(12))\r
+#define RMT_CH4_TX_END_INT_ST_V 0x1\r
+#define RMT_CH4_TX_END_INT_ST_S 12\r
+/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 3's rmt_ch3_err_int_raw\r
+ when rmt_ch3_err_int_ena is set to 1.*/\r
+#define RMT_CH3_ERR_INT_ST (BIT(11))\r
+#define RMT_CH3_ERR_INT_ST_M (BIT(11))\r
+#define RMT_CH3_ERR_INT_ST_V 0x1\r
+#define RMT_CH3_ERR_INT_ST_S 11\r
+/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw\r
+ when rmt_ch3_rx_end_int_ena is set to 1.*/\r
+#define RMT_CH3_RX_END_INT_ST (BIT(10))\r
+#define RMT_CH3_RX_END_INT_ST_M (BIT(10))\r
+#define RMT_CH3_RX_END_INT_ST_V 0x1\r
+#define RMT_CH3_RX_END_INT_ST_S 10\r
+/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw\r
+ when mt_ch3_tx_end_int_ena is set to 1.*/\r
+#define RMT_CH3_TX_END_INT_ST (BIT(9))\r
+#define RMT_CH3_TX_END_INT_ST_M (BIT(9))\r
+#define RMT_CH3_TX_END_INT_ST_V 0x1\r
+#define RMT_CH3_TX_END_INT_ST_S 9\r
+/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 2's rmt_ch2_err_int_raw\r
+ when rmt_ch2_err_int_ena is set to 1.*/\r
+#define RMT_CH2_ERR_INT_ST (BIT(8))\r
+#define RMT_CH2_ERR_INT_ST_M (BIT(8))\r
+#define RMT_CH2_ERR_INT_ST_V 0x1\r
+#define RMT_CH2_ERR_INT_ST_S 8\r
+/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw\r
+ when rmt_ch2_rx_end_int_ena is set to 1.*/\r
+#define RMT_CH2_RX_END_INT_ST (BIT(7))\r
+#define RMT_CH2_RX_END_INT_ST_M (BIT(7))\r
+#define RMT_CH2_RX_END_INT_ST_V 0x1\r
+#define RMT_CH2_RX_END_INT_ST_S 7\r
+/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw\r
+ when mt_ch2_tx_end_int_ena is set to 1.*/\r
+#define RMT_CH2_TX_END_INT_ST (BIT(6))\r
+#define RMT_CH2_TX_END_INT_ST_M (BIT(6))\r
+#define RMT_CH2_TX_END_INT_ST_V 0x1\r
+#define RMT_CH2_TX_END_INT_ST_S 6\r
+/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 1's rmt_ch1_err_int_raw\r
+ when rmt_ch1_err_int_ena is set to 1.*/\r
+#define RMT_CH1_ERR_INT_ST (BIT(5))\r
+#define RMT_CH1_ERR_INT_ST_M (BIT(5))\r
+#define RMT_CH1_ERR_INT_ST_V 0x1\r
+#define RMT_CH1_ERR_INT_ST_S 5\r
+/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw\r
+ when rmt_ch1_rx_end_int_ena is set to 1.*/\r
+#define RMT_CH1_RX_END_INT_ST (BIT(4))\r
+#define RMT_CH1_RX_END_INT_ST_M (BIT(4))\r
+#define RMT_CH1_RX_END_INT_ST_V 0x1\r
+#define RMT_CH1_RX_END_INT_ST_S 4\r
+/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw\r
+ when mt_ch1_tx_end_int_ena is set to 1.*/\r
+#define RMT_CH1_TX_END_INT_ST (BIT(3))\r
+#define RMT_CH1_TX_END_INT_ST_M (BIT(3))\r
+#define RMT_CH1_TX_END_INT_ST_V 0x1\r
+#define RMT_CH1_TX_END_INT_ST_S 3\r
+/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 0's rmt_ch0_err_int_raw\r
+ when rmt_ch0_err_int_ena is set to 0.*/\r
+#define RMT_CH0_ERR_INT_ST (BIT(2))\r
+#define RMT_CH0_ERR_INT_ST_M (BIT(2))\r
+#define RMT_CH0_ERR_INT_ST_V 0x1\r
+#define RMT_CH0_ERR_INT_ST_S 2\r
+/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw\r
+ when rmt_ch0_rx_end_int_ena is set to 0.*/\r
+#define RMT_CH0_RX_END_INT_ST (BIT(1))\r
+#define RMT_CH0_RX_END_INT_ST_M (BIT(1))\r
+#define RMT_CH0_RX_END_INT_ST_V 0x1\r
+#define RMT_CH0_RX_END_INT_ST_S 1\r
+/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw\r
+ when mt_ch0_tx_end_int_ena is set to 0.*/\r
+#define RMT_CH0_TX_END_INT_ST (BIT(0))\r
+#define RMT_CH0_TX_END_INT_ST_M (BIT(0))\r
+#define RMT_CH0_TX_END_INT_ST_V 0x1\r
+#define RMT_CH0_TX_END_INT_ST_S 0\r
+\r
+#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x00a8)\r
+/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/\r
+#define RMT_CH7_TX_THR_EVENT_INT_ENA (BIT(31))\r
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_M (BIT(31))\r
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_V 0x1\r
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_S 31\r
+/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/\r
+#define RMT_CH6_TX_THR_EVENT_INT_ENA (BIT(30))\r
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_M (BIT(30))\r
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_V 0x1\r
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_S 30\r
+/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/\r
+#define RMT_CH5_TX_THR_EVENT_INT_ENA (BIT(29))\r
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_M (BIT(29))\r
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_V 0x1\r
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_S 29\r
+/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/\r
+#define RMT_CH4_TX_THR_EVENT_INT_ENA (BIT(28))\r
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_M (BIT(28))\r
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_V 0x1\r
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_S 28\r
+/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/\r
+#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(27))\r
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(27))\r
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1\r
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 27\r
+/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/\r
+#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(26))\r
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(26))\r
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1\r
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 26\r
+/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/\r
+#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(25))\r
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(25))\r
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1\r
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 25\r
+/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/\r
+#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(24))\r
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(24))\r
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1\r
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 24\r
+/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch7_err_int_st.*/\r
+#define RMT_CH7_ERR_INT_ENA (BIT(23))\r
+#define RMT_CH7_ERR_INT_ENA_M (BIT(23))\r
+#define RMT_CH7_ERR_INT_ENA_V 0x1\r
+#define RMT_CH7_ERR_INT_ENA_S 23\r
+/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/\r
+#define RMT_CH7_RX_END_INT_ENA (BIT(22))\r
+#define RMT_CH7_RX_END_INT_ENA_M (BIT(22))\r
+#define RMT_CH7_RX_END_INT_ENA_V 0x1\r
+#define RMT_CH7_RX_END_INT_ENA_S 22\r
+/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/\r
+#define RMT_CH7_TX_END_INT_ENA (BIT(21))\r
+#define RMT_CH7_TX_END_INT_ENA_M (BIT(21))\r
+#define RMT_CH7_TX_END_INT_ENA_V 0x1\r
+#define RMT_CH7_TX_END_INT_ENA_S 21\r
+/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch6_err_int_st.*/\r
+#define RMT_CH6_ERR_INT_ENA (BIT(20))\r
+#define RMT_CH6_ERR_INT_ENA_M (BIT(20))\r
+#define RMT_CH6_ERR_INT_ENA_V 0x1\r
+#define RMT_CH6_ERR_INT_ENA_S 20\r
+/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/\r
+#define RMT_CH6_RX_END_INT_ENA (BIT(19))\r
+#define RMT_CH6_RX_END_INT_ENA_M (BIT(19))\r
+#define RMT_CH6_RX_END_INT_ENA_V 0x1\r
+#define RMT_CH6_RX_END_INT_ENA_S 19\r
+/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/\r
+#define RMT_CH6_TX_END_INT_ENA (BIT(18))\r
+#define RMT_CH6_TX_END_INT_ENA_M (BIT(18))\r
+#define RMT_CH6_TX_END_INT_ENA_V 0x1\r
+#define RMT_CH6_TX_END_INT_ENA_S 18\r
+/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch5_err_int_st.*/\r
+#define RMT_CH5_ERR_INT_ENA (BIT(17))\r
+#define RMT_CH5_ERR_INT_ENA_M (BIT(17))\r
+#define RMT_CH5_ERR_INT_ENA_V 0x1\r
+#define RMT_CH5_ERR_INT_ENA_S 17\r
+/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/\r
+#define RMT_CH5_RX_END_INT_ENA (BIT(16))\r
+#define RMT_CH5_RX_END_INT_ENA_M (BIT(16))\r
+#define RMT_CH5_RX_END_INT_ENA_V 0x1\r
+#define RMT_CH5_RX_END_INT_ENA_S 16\r
+/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/\r
+#define RMT_CH5_TX_END_INT_ENA (BIT(15))\r
+#define RMT_CH5_TX_END_INT_ENA_M (BIT(15))\r
+#define RMT_CH5_TX_END_INT_ENA_V 0x1\r
+#define RMT_CH5_TX_END_INT_ENA_S 15\r
+/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch4_err_int_st.*/\r
+#define RMT_CH4_ERR_INT_ENA (BIT(14))\r
+#define RMT_CH4_ERR_INT_ENA_M (BIT(14))\r
+#define RMT_CH4_ERR_INT_ENA_V 0x1\r
+#define RMT_CH4_ERR_INT_ENA_S 14\r
+/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/\r
+#define RMT_CH4_RX_END_INT_ENA (BIT(13))\r
+#define RMT_CH4_RX_END_INT_ENA_M (BIT(13))\r
+#define RMT_CH4_RX_END_INT_ENA_V 0x1\r
+#define RMT_CH4_RX_END_INT_ENA_S 13\r
+/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/\r
+#define RMT_CH4_TX_END_INT_ENA (BIT(12))\r
+#define RMT_CH4_TX_END_INT_ENA_M (BIT(12))\r
+#define RMT_CH4_TX_END_INT_ENA_V 0x1\r
+#define RMT_CH4_TX_END_INT_ENA_S 12\r
+/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch3_err_int_st.*/\r
+#define RMT_CH3_ERR_INT_ENA (BIT(11))\r
+#define RMT_CH3_ERR_INT_ENA_M (BIT(11))\r
+#define RMT_CH3_ERR_INT_ENA_V 0x1\r
+#define RMT_CH3_ERR_INT_ENA_S 11\r
+/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/\r
+#define RMT_CH3_RX_END_INT_ENA (BIT(10))\r
+#define RMT_CH3_RX_END_INT_ENA_M (BIT(10))\r
+#define RMT_CH3_RX_END_INT_ENA_V 0x1\r
+#define RMT_CH3_RX_END_INT_ENA_S 10\r
+/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/\r
+#define RMT_CH3_TX_END_INT_ENA (BIT(9))\r
+#define RMT_CH3_TX_END_INT_ENA_M (BIT(9))\r
+#define RMT_CH3_TX_END_INT_ENA_V 0x1\r
+#define RMT_CH3_TX_END_INT_ENA_S 9\r
+/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch2_err_int_st.*/\r
+#define RMT_CH2_ERR_INT_ENA (BIT(8))\r
+#define RMT_CH2_ERR_INT_ENA_M (BIT(8))\r
+#define RMT_CH2_ERR_INT_ENA_V 0x1\r
+#define RMT_CH2_ERR_INT_ENA_S 8\r
+/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/\r
+#define RMT_CH2_RX_END_INT_ENA (BIT(7))\r
+#define RMT_CH2_RX_END_INT_ENA_M (BIT(7))\r
+#define RMT_CH2_RX_END_INT_ENA_V 0x1\r
+#define RMT_CH2_RX_END_INT_ENA_S 7\r
+/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/\r
+#define RMT_CH2_TX_END_INT_ENA (BIT(6))\r
+#define RMT_CH2_TX_END_INT_ENA_M (BIT(6))\r
+#define RMT_CH2_TX_END_INT_ENA_V 0x1\r
+#define RMT_CH2_TX_END_INT_ENA_S 6\r
+/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch1_err_int_st.*/\r
+#define RMT_CH1_ERR_INT_ENA (BIT(5))\r
+#define RMT_CH1_ERR_INT_ENA_M (BIT(5))\r
+#define RMT_CH1_ERR_INT_ENA_V 0x1\r
+#define RMT_CH1_ERR_INT_ENA_S 5\r
+/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/\r
+#define RMT_CH1_RX_END_INT_ENA (BIT(4))\r
+#define RMT_CH1_RX_END_INT_ENA_M (BIT(4))\r
+#define RMT_CH1_RX_END_INT_ENA_V 0x1\r
+#define RMT_CH1_RX_END_INT_ENA_S 4\r
+/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/\r
+#define RMT_CH1_TX_END_INT_ENA (BIT(3))\r
+#define RMT_CH1_TX_END_INT_ENA_M (BIT(3))\r
+#define RMT_CH1_TX_END_INT_ENA_V 0x1\r
+#define RMT_CH1_TX_END_INT_ENA_S 3\r
+/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch0_err_int_st.*/\r
+#define RMT_CH0_ERR_INT_ENA (BIT(2))\r
+#define RMT_CH0_ERR_INT_ENA_M (BIT(2))\r
+#define RMT_CH0_ERR_INT_ENA_V 0x1\r
+#define RMT_CH0_ERR_INT_ENA_S 2\r
+/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/\r
+#define RMT_CH0_RX_END_INT_ENA (BIT(1))\r
+#define RMT_CH0_RX_END_INT_ENA_M (BIT(1))\r
+#define RMT_CH0_RX_END_INT_ENA_V 0x1\r
+#define RMT_CH0_RX_END_INT_ENA_S 1\r
+/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/\r
+#define RMT_CH0_TX_END_INT_ENA (BIT(0))\r
+#define RMT_CH0_TX_END_INT_ENA_M (BIT(0))\r
+#define RMT_CH0_TX_END_INT_ENA_V 0x1\r
+#define RMT_CH0_TX_END_INT_ENA_S 0\r
+\r
+#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x00ac)\r
+/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/\r
+#define RMT_CH7_TX_THR_EVENT_INT_CLR (BIT(31))\r
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_M (BIT(31))\r
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_V 0x1\r
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_S 31\r
+/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/\r
+#define RMT_CH6_TX_THR_EVENT_INT_CLR (BIT(30))\r
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_M (BIT(30))\r
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_V 0x1\r
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_S 30\r
+/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/\r
+#define RMT_CH5_TX_THR_EVENT_INT_CLR (BIT(29))\r
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_M (BIT(29))\r
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_V 0x1\r
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_S 29\r
+/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/\r
+#define RMT_CH4_TX_THR_EVENT_INT_CLR (BIT(28))\r
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_M (BIT(28))\r
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_V 0x1\r
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_S 28\r
+/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/\r
+#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(27))\r
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(27))\r
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1\r
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 27\r
+/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/\r
+#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(26))\r
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(26))\r
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1\r
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 26\r
+/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/\r
+#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(25))\r
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(25))\r
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1\r
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 25\r
+/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/\r
+#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(24))\r
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(24))\r
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1\r
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 24\r
+/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch7_err_int_raw.*/\r
+#define RMT_CH7_ERR_INT_CLR (BIT(23))\r
+#define RMT_CH7_ERR_INT_CLR_M (BIT(23))\r
+#define RMT_CH7_ERR_INT_CLR_V 0x1\r
+#define RMT_CH7_ERR_INT_CLR_S 23\r
+/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/\r
+#define RMT_CH7_RX_END_INT_CLR (BIT(22))\r
+#define RMT_CH7_RX_END_INT_CLR_M (BIT(22))\r
+#define RMT_CH7_RX_END_INT_CLR_V 0x1\r
+#define RMT_CH7_RX_END_INT_CLR_S 22\r
+/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/\r
+#define RMT_CH7_TX_END_INT_CLR (BIT(21))\r
+#define RMT_CH7_TX_END_INT_CLR_M (BIT(21))\r
+#define RMT_CH7_TX_END_INT_CLR_V 0x1\r
+#define RMT_CH7_TX_END_INT_CLR_S 21\r
+/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch6_err_int_raw.*/\r
+#define RMT_CH6_ERR_INT_CLR (BIT(20))\r
+#define RMT_CH6_ERR_INT_CLR_M (BIT(20))\r
+#define RMT_CH6_ERR_INT_CLR_V 0x1\r
+#define RMT_CH6_ERR_INT_CLR_S 20\r
+/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/\r
+#define RMT_CH6_RX_END_INT_CLR (BIT(19))\r
+#define RMT_CH6_RX_END_INT_CLR_M (BIT(19))\r
+#define RMT_CH6_RX_END_INT_CLR_V 0x1\r
+#define RMT_CH6_RX_END_INT_CLR_S 19\r
+/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/\r
+#define RMT_CH6_TX_END_INT_CLR (BIT(18))\r
+#define RMT_CH6_TX_END_INT_CLR_M (BIT(18))\r
+#define RMT_CH6_TX_END_INT_CLR_V 0x1\r
+#define RMT_CH6_TX_END_INT_CLR_S 18\r
+/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch5_err_int_raw.*/\r
+#define RMT_CH5_ERR_INT_CLR (BIT(17))\r
+#define RMT_CH5_ERR_INT_CLR_M (BIT(17))\r
+#define RMT_CH5_ERR_INT_CLR_V 0x1\r
+#define RMT_CH5_ERR_INT_CLR_S 17\r
+/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/\r
+#define RMT_CH5_RX_END_INT_CLR (BIT(16))\r
+#define RMT_CH5_RX_END_INT_CLR_M (BIT(16))\r
+#define RMT_CH5_RX_END_INT_CLR_V 0x1\r
+#define RMT_CH5_RX_END_INT_CLR_S 16\r
+/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/\r
+#define RMT_CH5_TX_END_INT_CLR (BIT(15))\r
+#define RMT_CH5_TX_END_INT_CLR_M (BIT(15))\r
+#define RMT_CH5_TX_END_INT_CLR_V 0x1\r
+#define RMT_CH5_TX_END_INT_CLR_S 15\r
+/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch4_err_int_raw.*/\r
+#define RMT_CH4_ERR_INT_CLR (BIT(14))\r
+#define RMT_CH4_ERR_INT_CLR_M (BIT(14))\r
+#define RMT_CH4_ERR_INT_CLR_V 0x1\r
+#define RMT_CH4_ERR_INT_CLR_S 14\r
+/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/\r
+#define RMT_CH4_RX_END_INT_CLR (BIT(13))\r
+#define RMT_CH4_RX_END_INT_CLR_M (BIT(13))\r
+#define RMT_CH4_RX_END_INT_CLR_V 0x1\r
+#define RMT_CH4_RX_END_INT_CLR_S 13\r
+/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/\r
+#define RMT_CH4_TX_END_INT_CLR (BIT(12))\r
+#define RMT_CH4_TX_END_INT_CLR_M (BIT(12))\r
+#define RMT_CH4_TX_END_INT_CLR_V 0x1\r
+#define RMT_CH4_TX_END_INT_CLR_S 12\r
+/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch3_err_int_raw.*/\r
+#define RMT_CH3_ERR_INT_CLR (BIT(11))\r
+#define RMT_CH3_ERR_INT_CLR_M (BIT(11))\r
+#define RMT_CH3_ERR_INT_CLR_V 0x1\r
+#define RMT_CH3_ERR_INT_CLR_S 11\r
+/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/\r
+#define RMT_CH3_RX_END_INT_CLR (BIT(10))\r
+#define RMT_CH3_RX_END_INT_CLR_M (BIT(10))\r
+#define RMT_CH3_RX_END_INT_CLR_V 0x1\r
+#define RMT_CH3_RX_END_INT_CLR_S 10\r
+/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/\r
+#define RMT_CH3_TX_END_INT_CLR (BIT(9))\r
+#define RMT_CH3_TX_END_INT_CLR_M (BIT(9))\r
+#define RMT_CH3_TX_END_INT_CLR_V 0x1\r
+#define RMT_CH3_TX_END_INT_CLR_S 9\r
+/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch2_err_int_raw.*/\r
+#define RMT_CH2_ERR_INT_CLR (BIT(8))\r
+#define RMT_CH2_ERR_INT_CLR_M (BIT(8))\r
+#define RMT_CH2_ERR_INT_CLR_V 0x1\r
+#define RMT_CH2_ERR_INT_CLR_S 8\r
+/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/\r
+#define RMT_CH2_RX_END_INT_CLR (BIT(7))\r
+#define RMT_CH2_RX_END_INT_CLR_M (BIT(7))\r
+#define RMT_CH2_RX_END_INT_CLR_V 0x1\r
+#define RMT_CH2_RX_END_INT_CLR_S 7\r
+/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/\r
+#define RMT_CH2_TX_END_INT_CLR (BIT(6))\r
+#define RMT_CH2_TX_END_INT_CLR_M (BIT(6))\r
+#define RMT_CH2_TX_END_INT_CLR_V 0x1\r
+#define RMT_CH2_TX_END_INT_CLR_S 6\r
+/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch1_err_int_raw.*/\r
+#define RMT_CH1_ERR_INT_CLR (BIT(5))\r
+#define RMT_CH1_ERR_INT_CLR_M (BIT(5))\r
+#define RMT_CH1_ERR_INT_CLR_V 0x1\r
+#define RMT_CH1_ERR_INT_CLR_S 5\r
+/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/\r
+#define RMT_CH1_RX_END_INT_CLR (BIT(4))\r
+#define RMT_CH1_RX_END_INT_CLR_M (BIT(4))\r
+#define RMT_CH1_RX_END_INT_CLR_V 0x1\r
+#define RMT_CH1_RX_END_INT_CLR_S 4\r
+/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/\r
+#define RMT_CH1_TX_END_INT_CLR (BIT(3))\r
+#define RMT_CH1_TX_END_INT_CLR_M (BIT(3))\r
+#define RMT_CH1_TX_END_INT_CLR_V 0x1\r
+#define RMT_CH1_TX_END_INT_CLR_S 3\r
+/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch0_err_int_raw.*/\r
+#define RMT_CH0_ERR_INT_CLR (BIT(2))\r
+#define RMT_CH0_ERR_INT_CLR_M (BIT(2))\r
+#define RMT_CH0_ERR_INT_CLR_V 0x1\r
+#define RMT_CH0_ERR_INT_CLR_S 2\r
+/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/\r
+#define RMT_CH0_RX_END_INT_CLR (BIT(1))\r
+#define RMT_CH0_RX_END_INT_CLR_M (BIT(1))\r
+#define RMT_CH0_RX_END_INT_CLR_V 0x1\r
+#define RMT_CH0_RX_END_INT_CLR_S 1\r
+/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/\r
+#define RMT_CH0_TX_END_INT_CLR (BIT(0))\r
+#define RMT_CH0_TX_END_INT_CLR_M (BIT(0))\r
+#define RMT_CH0_TX_END_INT_CLR_V 0x1\r
+#define RMT_CH0_TX_END_INT_CLR_S 0\r
+\r
+#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b0)\r
+/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's high level value for channel0.*/\r
+#define RMT_CARRIER_HIGH_CH0 0x0000FFFF\r
+#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S))\r
+#define RMT_CARRIER_HIGH_CH0_V 0xFFFF\r
+#define RMT_CARRIER_HIGH_CH0_S 16\r
+/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's low level value for channel0.*/\r
+#define RMT_CARRIER_LOW_CH0 0x0000FFFF\r
+#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S))\r
+#define RMT_CARRIER_LOW_CH0_V 0xFFFF\r
+#define RMT_CARRIER_LOW_CH0_S 0\r
+\r
+#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b4)\r
+/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's high level value for channel1.*/\r
+#define RMT_CARRIER_HIGH_CH1 0x0000FFFF\r
+#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S))\r
+#define RMT_CARRIER_HIGH_CH1_V 0xFFFF\r
+#define RMT_CARRIER_HIGH_CH1_S 16\r
+/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's low level value for channel1.*/\r
+#define RMT_CARRIER_LOW_CH1 0x0000FFFF\r
+#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S))\r
+#define RMT_CARRIER_LOW_CH1_V 0xFFFF\r
+#define RMT_CARRIER_LOW_CH1_S 0\r
+\r
+#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00b8)\r
+/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's high level value for channel2.*/\r
+#define RMT_CARRIER_HIGH_CH2 0x0000FFFF\r
+#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S))\r
+#define RMT_CARRIER_HIGH_CH2_V 0xFFFF\r
+#define RMT_CARRIER_HIGH_CH2_S 16\r
+/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's low level value for channel2.*/\r
+#define RMT_CARRIER_LOW_CH2 0x0000FFFF\r
+#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S))\r
+#define RMT_CARRIER_LOW_CH2_V 0xFFFF\r
+#define RMT_CARRIER_LOW_CH2_S 0\r
+\r
+#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00bc)\r
+/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's high level value for channel3.*/\r
+#define RMT_CARRIER_HIGH_CH3 0x0000FFFF\r
+#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S))\r
+#define RMT_CARRIER_HIGH_CH3_V 0xFFFF\r
+#define RMT_CARRIER_HIGH_CH3_S 16\r
+/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's low level value for channel3.*/\r
+#define RMT_CARRIER_LOW_CH3 0x0000FFFF\r
+#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S))\r
+#define RMT_CARRIER_LOW_CH3_V 0xFFFF\r
+#define RMT_CARRIER_LOW_CH3_S 0\r
+\r
+#define RMT_CH4CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c0)\r
+/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's high level value for channel4.*/\r
+#define RMT_CARRIER_HIGH_CH4 0x0000FFFF\r
+#define RMT_CARRIER_HIGH_CH4_M ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S))\r
+#define RMT_CARRIER_HIGH_CH4_V 0xFFFF\r
+#define RMT_CARRIER_HIGH_CH4_S 16\r
+/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's low level value for channel4.*/\r
+#define RMT_CARRIER_LOW_CH4 0x0000FFFF\r
+#define RMT_CARRIER_LOW_CH4_M ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S))\r
+#define RMT_CARRIER_LOW_CH4_V 0xFFFF\r
+#define RMT_CARRIER_LOW_CH4_S 0\r
+\r
+#define RMT_CH5CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c4)\r
+/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's high level value for channel5.*/\r
+#define RMT_CARRIER_HIGH_CH5 0x0000FFFF\r
+#define RMT_CARRIER_HIGH_CH5_M ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S))\r
+#define RMT_CARRIER_HIGH_CH5_V 0xFFFF\r
+#define RMT_CARRIER_HIGH_CH5_S 16\r
+/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's low level value for channel5.*/\r
+#define RMT_CARRIER_LOW_CH5 0x0000FFFF\r
+#define RMT_CARRIER_LOW_CH5_M ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S))\r
+#define RMT_CARRIER_LOW_CH5_V 0xFFFF\r
+#define RMT_CARRIER_LOW_CH5_S 0\r
+\r
+#define RMT_CH6CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00c8)\r
+/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's high level value for channel6.*/\r
+#define RMT_CARRIER_HIGH_CH6 0x0000FFFF\r
+#define RMT_CARRIER_HIGH_CH6_M ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S))\r
+#define RMT_CARRIER_HIGH_CH6_V 0xFFFF\r
+#define RMT_CARRIER_HIGH_CH6_S 16\r
+/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's low level value for channel6.*/\r
+#define RMT_CARRIER_LOW_CH6 0x0000FFFF\r
+#define RMT_CARRIER_LOW_CH6_M ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S))\r
+#define RMT_CARRIER_LOW_CH6_V 0xFFFF\r
+#define RMT_CARRIER_LOW_CH6_S 0\r
+\r
+#define RMT_CH7CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x00cc)\r
+/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's high level value for channel7.*/\r
+#define RMT_CARRIER_HIGH_CH7 0x0000FFFF\r
+#define RMT_CARRIER_HIGH_CH7_M ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S))\r
+#define RMT_CARRIER_HIGH_CH7_V 0xFFFF\r
+#define RMT_CARRIER_HIGH_CH7_S 16\r
+/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */\r
+/*description: This register is used to configure carrier wave's low level value for channel7.*/\r
+#define RMT_CARRIER_LOW_CH7 0x0000FFFF\r
+#define RMT_CARRIER_LOW_CH7_M ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S))\r
+#define RMT_CARRIER_LOW_CH7_V 0xFFFF\r
+#define RMT_CARRIER_LOW_CH7_S 0\r
+\r
+#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d0)\r
+/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
+/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0\r
+ produce the relative interrupt.*/\r
+#define RMT_TX_LIM_CH0 0x000001FF\r
+#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S))\r
+#define RMT_TX_LIM_CH0_V 0x1FF\r
+#define RMT_TX_LIM_CH0_S 0\r
+\r
+#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d4)\r
+/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
+/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1\r
+ produce the relative interrupt.*/\r
+#define RMT_TX_LIM_CH1 0x000001FF\r
+#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S))\r
+#define RMT_TX_LIM_CH1_V 0x1FF\r
+#define RMT_TX_LIM_CH1_S 0\r
+\r
+#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00d8)\r
+/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
+/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2\r
+ produce the relative interrupt.*/\r
+#define RMT_TX_LIM_CH2 0x000001FF\r
+#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S))\r
+#define RMT_TX_LIM_CH2_V 0x1FF\r
+#define RMT_TX_LIM_CH2_S 0\r
+\r
+#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00dc)\r
+/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
+/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3\r
+ produce the relative interrupt.*/\r
+#define RMT_TX_LIM_CH3 0x000001FF\r
+#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S))\r
+#define RMT_TX_LIM_CH3_V 0x1FF\r
+#define RMT_TX_LIM_CH3_S 0\r
+\r
+#define RMT_CH4_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e0)\r
+/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
+/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4\r
+ produce the relative interrupt.*/\r
+#define RMT_TX_LIM_CH4 0x000001FF\r
+#define RMT_TX_LIM_CH4_M ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S))\r
+#define RMT_TX_LIM_CH4_V 0x1FF\r
+#define RMT_TX_LIM_CH4_S 0\r
+\r
+#define RMT_CH5_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e4)\r
+/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
+/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5\r
+ produce the relative interrupt.*/\r
+#define RMT_TX_LIM_CH5 0x000001FF\r
+#define RMT_TX_LIM_CH5_M ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S))\r
+#define RMT_TX_LIM_CH5_V 0x1FF\r
+#define RMT_TX_LIM_CH5_S 0\r
+\r
+#define RMT_CH6_TX_LIM_REG (DR_REG_RMT_BASE + 0x00e8)\r
+/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
+/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6\r
+ produce the relative interrupt.*/\r
+#define RMT_TX_LIM_CH6 0x000001FF\r
+#define RMT_TX_LIM_CH6_M ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S))\r
+#define RMT_TX_LIM_CH6_V 0x1FF\r
+#define RMT_TX_LIM_CH6_S 0\r
+\r
+#define RMT_CH7_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ec)\r
+/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */\r
+/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7\r
+ produce the relative interrupt.*/\r
+#define RMT_TX_LIM_CH7 0x000001FF\r
+#define RMT_TX_LIM_CH7_M ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S))\r
+#define RMT_TX_LIM_CH7_V 0x1FF\r
+#define RMT_TX_LIM_CH7_S 0\r
+\r
+#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00f0)\r
+/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: when datas need to be send is more than channel's mem can store\r
+ then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/\r
+#define RMT_MEM_TX_WRAP_EN (BIT(1))\r
+#define RMT_MEM_TX_WRAP_EN_M (BIT(1))\r
+#define RMT_MEM_TX_WRAP_EN_V 0x1\r
+#define RMT_MEM_TX_WRAP_EN_S 1\r
+/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */\r
+/*description: Set this bit to disable apb fifo access*/\r
+#define RMT_APB_FIFO_MASK (BIT(0))\r
+#define RMT_APB_FIFO_MASK_M (BIT(0))\r
+#define RMT_APB_FIFO_MASK_V 0x1\r
+#define RMT_APB_FIFO_MASK_S 0\r
+\r
+#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00fc)\r
+/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */\r
+/*description: This is the version register.*/\r
+#define RMT_DATE 0xFFFFFFFF\r
+#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S))\r
+#define RMT_DATE_V 0xFFFFFFFF\r
+#define RMT_DATE_S 0\r
+\r
+\r
+\r
+\r
+#endif /*_SOC_RMT_REG_H_ */\r
+\r
+\r
#ifndef _SOC_RTC_CNTL_REG_H_
#define _SOC_RTC_CNTL_REG_H_
+
#include "soc.h"
+#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
+/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: SW system reset*/
+#define RTC_CNTL_SW_SYS_RST (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_M (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_V 0x1
+#define RTC_CNTL_SW_SYS_RST_S 31
+/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force no reset in deep sleep*/
+#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30
+/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: digital wrap force reset in deep sleep*/
+#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29
+/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28
+/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1
+#define RTC_CNTL_PLL_FORCE_NOISO_S 27
+/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1
+#define RTC_CNTL_XTL_FORCE_NOISO_S 26
+/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1
+#define RTC_CNTL_ANALOG_FORCE_ISO_S 25
+/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_PLL_FORCE_ISO (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_V 0x1
+#define RTC_CNTL_PLL_FORCE_ISO_S 24
+/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_XTL_FORCE_ISO (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_V 0x1
+#define RTC_CNTL_XTL_FORCE_ISO_S 23
+/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */
+/*description: BIAS_CORE force power up*/
+#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22))
+#define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22))
+#define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1
+#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22
+/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: BIAS_CORE force power down*/
+#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21))
+#define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21))
+#define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1
+#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21
+/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: BIAS_CORE follow CK8M*/
+#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20))
+#define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20))
+#define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1
+#define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20
+/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */
+/*description: BIAS_I2C force power up*/
+#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19))
+#define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19))
+#define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1
+#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19
+/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: BIAS_I2C force power down*/
+#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18))
+#define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18))
+#define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1
+#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18
+/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: BIAS_I2C follow CK8M*/
+#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17))
+#define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17))
+#define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1
+#define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17
+/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: BIAS_SLEEP force no sleep*/
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16))
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16))
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16
+/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: BIAS_SLEEP force sleep*/
+#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15))
+#define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15))
+#define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1
+#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15
+/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: BIAS_SLEEP follow CK8M*/
+#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14))
+#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14))
+#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1
+#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14
+/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
+/*description: crystall force power up*/
+#define RTC_CNTL_XTL_FORCE_PU (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_V 0x1
+#define RTC_CNTL_XTL_FORCE_PU_S 13
+/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: crystall force power down*/
+#define RTC_CNTL_XTL_FORCE_PD (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_V 0x1
+#define RTC_CNTL_XTL_FORCE_PD_S 12
+/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: BB_PLL force power up*/
+#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1
+#define RTC_CNTL_BBPLL_FORCE_PU_S 11
+/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: BB_PLL force power down*/
+#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1
+#define RTC_CNTL_BBPLL_FORCE_PD_S 10
+/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: BB_PLL_I2C force power up*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9
+/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: BB_PLL _I2C force power down*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8
+/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: BB_I2C force power up*/
+#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1
+#define RTC_CNTL_BB_I2C_FORCE_PU_S 7
+/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: BB_I2C force power down*/
+#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1
+#define RTC_CNTL_BB_I2C_FORCE_PD_S 6
+/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: PRO CPU SW reset*/
+#define RTC_CNTL_SW_PROCPU_RST (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_V 0x1
+#define RTC_CNTL_SW_PROCPU_RST_S 5
+/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: APP CPU SW reset*/
+#define RTC_CNTL_SW_APPCPU_RST (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_V 0x1
+#define RTC_CNTL_SW_APPCPU_RST_S 4
+/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} ==
+ 0x86 will stall PRO CPU*/
+#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2
+/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} ==
+ 0x86 will stall APP CPU*/
+#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003
+#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3
+#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0
+
+#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4)
+/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC sleep timer low 32 bits*/
+#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
+#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_S 0
+
+#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8)
+/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: timer alarm enable bit*/
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16
+/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC sleep timer high 16 bits*/
+#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF
+#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
+#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF
+#define RTC_CNTL_SLP_VAL_HI_S 0
+
+#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc)
+/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Set 1: to update register with RTC timer*/
+#define RTC_CNTL_TIME_UPDATE (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_M (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_V 0x1
+#define RTC_CNTL_TIME_UPDATE_S 31
+/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: To indicate the register is updated*/
+#define RTC_CNTL_TIME_VALID (BIT(30))
+#define RTC_CNTL_TIME_VALID_M (BIT(30))
+#define RTC_CNTL_TIME_VALID_V 0x1
+#define RTC_CNTL_TIME_VALID_S 30
+
+#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10)
+/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits*/
+#define RTC_CNTL_TIME_LO 0xFFFFFFFF
+#define RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S))
+#define RTC_CNTL_TIME_LO_V 0xFFFFFFFF
+#define RTC_CNTL_TIME_LO_S 0
+
+#define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14)
+/* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits*/
+#define RTC_CNTL_TIME_HI 0x0000FFFF
+#define RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S))
+#define RTC_CNTL_TIME_HI_V 0xFFFF
+#define RTC_CNTL_TIME_HI_S 0
+
+#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18)
+/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: sleep enable bit*/
+#define RTC_CNTL_SLEEP_EN (BIT(31))
+#define RTC_CNTL_SLEEP_EN_M (BIT(31))
+#define RTC_CNTL_SLEEP_EN_V 0x1
+#define RTC_CNTL_SLEEP_EN_S 31
+/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: sleep reject bit*/
+#define RTC_CNTL_SLP_REJECT (BIT(30))
+#define RTC_CNTL_SLP_REJECT_M (BIT(30))
+#define RTC_CNTL_SLP_REJECT_V 0x1
+#define RTC_CNTL_SLP_REJECT_S 30
+/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: sleep wakeup bit*/
+#define RTC_CNTL_SLP_WAKEUP (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_M (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_V 0x1
+#define RTC_CNTL_SLP_WAKEUP_S 29
+/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: SDIO active indication*/
+#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1
+#define RTC_CNTL_SDIO_ACTIVE_IND_S 28
+/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: ULP-coprocessor timer enable bit*/
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24))
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24))
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24
+/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: touch timer enable bit*/
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23
+/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22
+/* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
+/*description: ULP-coprocessor force wake up*/
+#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21))
+#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21))
+#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1
+#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21
+/* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: touch controller force wake up*/
+#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20))
+#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20))
+#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1
+#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20
+
+#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c)
+/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
+/*description: PLL wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF
+#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
+#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF
+#define RTC_CNTL_PLL_BUF_WAIT_S 24
+/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
+/*description: XTAL wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF
+#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
+#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF
+#define RTC_CNTL_XTL_BUF_WAIT_S 14
+/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
+/*description: CK8M wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_CK8M_WAIT 0x000000FF
+#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
+#define RTC_CNTL_CK8M_WAIT_V 0xFF
+#define RTC_CNTL_CK8M_WAIT_S 6
+/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
+/*description: CPU stall wait cycles in fast_clk_rtc*/
+#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F
+#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
+#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F
+#define RTC_CNTL_CPU_STALL_WAIT_S 1
+/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: CPU stall enable bit*/
+#define RTC_CNTL_CPU_STALL_EN (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_M (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_V 0x1
+#define RTC_CNTL_CPU_STALL_EN_S 0
+
+#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20)
+/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
+/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/
+#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24
+/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */
+/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller
+ start to work*/
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S))
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15
+
+#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24)
+/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */
+/*description: */
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S))
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25
+/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */
+/*description: */
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S))
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16
+/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
+#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9
+/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
+#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_S 0
+
+#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28)
+/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25
+/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16
+/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S))
+#define RTC_CNTL_POWERUP_TIMER_V 0x7F
+#define RTC_CNTL_POWERUP_TIMER_S 9
+/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S))
+#define RTC_CNTL_WAIT_TIMER_V 0x1FF
+#define RTC_CNTL_WAIT_TIMER_S 0
+
+#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c)
+/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */
+/*description: */
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S))
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25
+/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */
+/*description: */
+#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S))
+#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF
+#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16
+/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
+/*description: minimal sleep cycles in slow_clk_rtc*/
+#define RTC_CNTL_MIN_SLP_VAL 0x000000FF
+#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
+#define RTC_CNTL_MIN_SLP_VAL_V 0xFF
+#define RTC_CNTL_MIN_SLP_VAL_S 8
+/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */
+/*description: */
+#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF
+#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S))
+#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF
+#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0
+
+#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30)
+/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: 1: PLL_I2C power up otherwise power down*/
+#define RTC_CNTL_PLL_I2C_PU (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_M (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_V 0x1
+#define RTC_CNTL_PLL_I2C_PU_S 31
+/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: CKGEN_I2C power up otherwise power down*/
+#define RTC_CNTL_CKGEN_I2C_PU (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_V 0x1
+#define RTC_CNTL_CKGEN_I2C_PU_S 30
+/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: 1: RFRX_PBUS power up otherwise power down*/
+#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_V 0x1
+#define RTC_CNTL_RFRX_PBUS_PU_S 28
+/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: TXRF_I2C power up otherwise power down*/
+#define RTC_CNTL_TXRF_I2C_PU (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_V 0x1
+#define RTC_CNTL_TXRF_I2C_PU_S 27
+/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: PVTMON power up otherwise power down*/
+#define RTC_CNTL_PVTMON_PU (BIT(26))
+#define RTC_CNTL_PVTMON_PU_M (BIT(26))
+#define RTC_CNTL_PVTMON_PU_V 0x1
+#define RTC_CNTL_PVTMON_PU_S 26
+/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: start BBPLL calibration during sleep*/
+#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25
+/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: PLLA force power up*/
+#define RTC_CNTL_PLLA_FORCE_PU (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_V 0x1
+#define RTC_CNTL_PLLA_FORCE_PU_S 24
+/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: PLLA force power down*/
+#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_V 0x1
+#define RTC_CNTL_PLLA_FORCE_PD_S 23
+
+#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34)
+/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: PRO CPU state vector sel*/
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13))
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13))
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13
+/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: APP CPU state vector sel*/
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12))
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12))
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12
+/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
+/*description: reset cause of APP CPU*/
+#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
+#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6
+/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
+/*description: reset cause of PRO CPU*/
+#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
+#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0
+
+#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38)
+/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: enable filter for gpio wakeup event*/
+#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22
+/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */
+/*description: wakeup enable bitmap*/
+#define RTC_CNTL_WAKEUP_ENA 0x000007FF
+#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
+#define RTC_CNTL_WAKEUP_ENA_V 0x7FF
+#define RTC_CNTL_WAKEUP_ENA_S 11
+/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: wakeup cause*/
+#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF
+#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
+#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF
+#define RTC_CNTL_WAKEUP_CAUSE_S 0
+
+#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c)
+/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 8
+/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable brown out interrupt*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_S 7
+/* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable touch interrupt*/
+#define RTC_CNTL_TOUCH_INT_ENA (BIT(6))
+#define RTC_CNTL_TOUCH_INT_ENA_M (BIT(6))
+#define RTC_CNTL_TOUCH_INT_ENA_V 0x1
+#define RTC_CNTL_TOUCH_INT_ENA_S 6
+/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable ULP-coprocessor interrupt*/
+#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1
+#define RTC_CNTL_ULP_CP_INT_ENA_S 5
+/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable RTC time valid interrupt*/
+#define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1
+#define RTC_CNTL_TIME_VALID_INT_ENA_S 4
+/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt*/
+#define RTC_CNTL_WDT_INT_ENA (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_M (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_V 0x1
+#define RTC_CNTL_WDT_INT_ENA_S 3
+/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable SDIO idle interrupt*/
+#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2
+/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0
+
+#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40)
+/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt raw*/
+#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 8
+/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: brown out interrupt raw*/
+#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1
+#define RTC_CNTL_BROWN_OUT_INT_RAW_S 7
+/* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: touch interrupt raw*/
+#define RTC_CNTL_TOUCH_INT_RAW (BIT(6))
+#define RTC_CNTL_TOUCH_INT_RAW_M (BIT(6))
+#define RTC_CNTL_TOUCH_INT_RAW_V 0x1
+#define RTC_CNTL_TOUCH_INT_RAW_S 6
+/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ULP-coprocessor interrupt raw*/
+#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1
+#define RTC_CNTL_ULP_CP_INT_RAW_S 5
+/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: RTC time valid interrupt raw*/
+#define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1
+#define RTC_CNTL_TIME_VALID_INT_RAW_S 4
+/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt raw*/
+#define RTC_CNTL_WDT_INT_RAW (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_M (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_V 0x1
+#define RTC_CNTL_WDT_INT_RAW_S 3
+/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SDIO idle interrupt raw*/
+#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2
+/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt raw*/
+#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1
+/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt raw*/
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0
+
+#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44)
+/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt state*/
+#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ST_S 8
+/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: brown out interrupt state*/
+#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(7))
+#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7))
+#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1
+#define RTC_CNTL_BROWN_OUT_INT_ST_S 7
+/* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: touch interrupt state*/
+#define RTC_CNTL_TOUCH_INT_ST (BIT(6))
+#define RTC_CNTL_TOUCH_INT_ST_M (BIT(6))
+#define RTC_CNTL_TOUCH_INT_ST_V 0x1
+#define RTC_CNTL_TOUCH_INT_ST_S 6
+/* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ULP-coprocessor interrupt state*/
+#define RTC_CNTL_SAR_INT_ST (BIT(5))
+#define RTC_CNTL_SAR_INT_ST_M (BIT(5))
+#define RTC_CNTL_SAR_INT_ST_V 0x1
+#define RTC_CNTL_SAR_INT_ST_S 5
+/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: RTC time valid interrupt state*/
+#define RTC_CNTL_TIME_VALID_INT_ST (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_ST_V 0x1
+#define RTC_CNTL_TIME_VALID_INT_ST_S 4
+/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt state*/
+#define RTC_CNTL_WDT_INT_ST (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_M (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_V 0x1
+#define RTC_CNTL_WDT_INT_ST_S 3
+/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SDIO idle interrupt state*/
+#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1
+#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2
+/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt state*/
+#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1
+#define RTC_CNTL_SLP_REJECT_INT_ST_S 1
+/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt state*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0
+
+#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48)
+/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Clear RTC main timer interrupt state*/
+#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 8
+/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Clear brown out interrupt state*/
+#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1
+#define RTC_CNTL_BROWN_OUT_INT_CLR_S 7
+/* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Clear touch interrupt state*/
+#define RTC_CNTL_TOUCH_INT_CLR (BIT(6))
+#define RTC_CNTL_TOUCH_INT_CLR_M (BIT(6))
+#define RTC_CNTL_TOUCH_INT_CLR_V 0x1
+#define RTC_CNTL_TOUCH_INT_CLR_S 6
+/* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Clear ULP-coprocessor interrupt state*/
+#define RTC_CNTL_SAR_INT_CLR (BIT(5))
+#define RTC_CNTL_SAR_INT_CLR_M (BIT(5))
+#define RTC_CNTL_SAR_INT_CLR_V 0x1
+#define RTC_CNTL_SAR_INT_CLR_S 5
+/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Clear RTC time valid interrupt state*/
+#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1
+#define RTC_CNTL_TIME_VALID_INT_CLR_S 4
+/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state*/
+#define RTC_CNTL_WDT_INT_CLR (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_M (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_V 0x1
+#define RTC_CNTL_WDT_INT_CLR_S 3
+/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Clear SDIO idle interrupt state*/
+#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2
+/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Clear sleep reject interrupt state*/
+#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1
+/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Clear sleep wakeup interrupt state*/
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0
+
+#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c)
+/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: 32-bit general purpose retention register*/
+#define RTC_CNTL_SCRATCH0 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
+#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_S 0
+
+#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50)
+/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: 32-bit general purpose retention register*/
+#define RTC_CNTL_SCRATCH1 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
+#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_S 0
+
+#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54)
+/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: 32-bit general purpose retention register*/
+#define RTC_CNTL_SCRATCH2 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
+#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_S 0
+
+#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58)
+/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: 32-bit general purpose retention register*/
+#define RTC_CNTL_SCRATCH3 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
+#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_S 0
+
+#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c)
+/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable control XTAL by external pads*/
+#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1
+#define RTC_CNTL_XTL_EXT_CTR_EN_S 31
+/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: power down XTAL at high level 1: power down XTAL at low level*/
+#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1
+#define RTC_CNTL_XTL_EXT_CTR_LV_S 30
+
+#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60)
+/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 0: external wakeup at low level 1: external wakeup at high level*/
+#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31))
+#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31))
+#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1
+#define RTC_CNTL_EXT_WAKEUP1_LV_S 31
+/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: external wakeup at low level 1: external wakeup at high level*/
+#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30))
+#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30))
+#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1
+#define RTC_CNTL_EXT_WAKEUP0_LV_S 30
+
+#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64)
+/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: sleep reject cause*/
+#define RTC_CNTL_REJECT_CAUSE 0x0000000F
+#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
+#define RTC_CNTL_REJECT_CAUSE_V 0xF
+#define RTC_CNTL_REJECT_CAUSE_S 28
+/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: enable reject for deep sleep*/
+#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27
+/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: enable reject for light sleep*/
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26
+/* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: enable SDIO reject*/
+#define RTC_CNTL_SDIO_REJECT_EN (BIT(25))
+#define RTC_CNTL_SDIO_REJECT_EN_M (BIT(25))
+#define RTC_CNTL_SDIO_REJECT_EN_V 0x1
+#define RTC_CNTL_SDIO_REJECT_EN_S 25
+/* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: enable GPIO reject*/
+#define RTC_CNTL_GPIO_REJECT_EN (BIT(24))
+#define RTC_CNTL_GPIO_REJECT_EN_M (BIT(24))
+#define RTC_CNTL_GPIO_REJECT_EN_V 0x1
+#define RTC_CNTL_GPIO_REJECT_EN_S 24
+
+#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68)
+/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
+/*description: CPU period sel*/
+#define RTC_CNTL_CPUPERIOD_SEL 0x00000003
+#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
+#define RTC_CNTL_CPUPERIOD_SEL_V 0x3
+#define RTC_CNTL_CPUPERIOD_SEL_S 30
+/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: CPU sel option*/
+#define RTC_CNTL_CPUSEL_CONF (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_M (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_V 0x1
+#define RTC_CNTL_CPUSEL_CONF_S 29
+
+#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c)
+/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */
+/*description: */
+#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF
+#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S))
+#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF
+#define RTC_CNTL_SDIO_ACT_DNUM_S 22
+
+#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70)
+/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/
+#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
+#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30
+/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/
+#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
+/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
+/*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/
+#define RTC_CNTL_SOC_CLK_SEL 0x00000003
+#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S))
+#define RTC_CNTL_SOC_CLK_SEL_V 0x3
+#define RTC_CNTL_SOC_CLK_SEL_S 27
+/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: CK8M force power up*/
+#define RTC_CNTL_CK8M_FORCE_PU (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_V 0x1
+#define RTC_CNTL_CK8M_FORCE_PU_S 26
+/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: CK8M force power down*/
+#define RTC_CNTL_CK8M_FORCE_PD (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_V 0x1
+#define RTC_CNTL_CK8M_FORCE_PD_S 25
+/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */
+/*description: CK8M_DFREQ*/
+#define RTC_CNTL_CK8M_DFREQ 0x000000FF
+#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
+#define RTC_CNTL_CK8M_DFREQ_V 0xFF
+#define RTC_CNTL_CK8M_DFREQ_S 17
+/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: CK8M force no gating during sleep*/
+#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1
+#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16
+/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: XTAL force no gating during sleep*/
+#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15
+/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */
+/*description: divider = reg_ck8m_div_sel + 1*/
+#define RTC_CNTL_CK8M_DIV_SEL 0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
+#define RTC_CNTL_CK8M_DIV_SEL_V 0x7
+#define RTC_CNTL_CK8M_DIV_SEL_S 12
+/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11))
+#define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11))
+#define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1
+#define RTC_CNTL_CK8M_DFREQ_FORCE_S 11
+/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable CK8M for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_CLK8M_EN (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_V 0x1
+#define RTC_CNTL_DIG_CLK8M_EN_S 10
+/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1
+#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9
+/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1
+#define RTC_CNTL_DIG_XTAL32K_EN_S 8
+/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/
+#define RTC_CNTL_ENB_CK8M_DIV (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_V 0x1
+#define RTC_CNTL_ENB_CK8M_DIV_S 7
+/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: disable CK8M and CK8M_D256_OUT*/
+#define RTC_CNTL_ENB_CK8M (BIT(6))
+#define RTC_CNTL_ENB_CK8M_M (BIT(6))
+#define RTC_CNTL_ENB_CK8M_V 0x1
+#define RTC_CNTL_ENB_CK8M_S 6
+/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
+/*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/
+#define RTC_CNTL_CK8M_DIV 0x00000003
+#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
+#define RTC_CNTL_CK8M_DIV_V 0x3
+#define RTC_CNTL_CK8M_DIV_S 4
+
+#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74)
+/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_XPD_SDIO_REG (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_V 0x1
+#define RTC_CNTL_XPD_SDIO_REG_S 31
+/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
+/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFH_SDIO 0x00000003
+#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
+#define RTC_CNTL_DREFH_SDIO_V 0x3
+#define RTC_CNTL_DREFH_SDIO_S 29
+/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
+/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFM_SDIO 0x00000003
+#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
+#define RTC_CNTL_DREFM_SDIO_V 0x3
+#define RTC_CNTL_DREFM_SDIO_S 27
+/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
+/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFL_SDIO 0x00000003
+#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
+#define RTC_CNTL_DREFL_SDIO_V 0x3
+#define RTC_CNTL_DREFL_SDIO_S 25
+/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: read only register for REG1P8_READY*/
+#define RTC_CNTL_REG1P8_READY (BIT(24))
+#define RTC_CNTL_REG1P8_READY_M (BIT(24))
+#define RTC_CNTL_REG1P8_READY_V 0x1
+#define RTC_CNTL_REG1P8_READY_S 24
+/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_SDIO_TIEH (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_M (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_V 0x1
+#define RTC_CNTL_SDIO_TIEH_S 23
+/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: use SW option to control SDIO_REG 0: use state machine*/
+#define RTC_CNTL_SDIO_FORCE (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_M (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_V 0x1
+#define RTC_CNTL_SDIO_FORCE_S 22
+/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
+/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
+#define RTC_CNTL_SDIO_PD_EN (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_M (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_V 0x1
+#define RTC_CNTL_SDIO_PD_EN_S 21
-#define RTC_OPTIONS0 (DR_REG_RTCCNTL_BASE + 0x0)
-#define RTC_CNTL_SW_SYS_RST (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_S 31
-#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30
-#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29
-#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28
-#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
-#define RTC_CNTL_PLL_FORCE_NOISO_S 27
-#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26))
-#define RTC_CNTL_XTL_FORCE_NOISO_S 26
-#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_S 25
-#define RTC_CNTL_PLL_FORCE_ISO (BIT(24))
-#define RTC_CNTL_PLL_FORCE_ISO_S 24
-#define RTC_CNTL_XTL_FORCE_ISO (BIT(23))
-#define RTC_CNTL_XTL_FORCE_ISO_S 23
-#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22))
-#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22
-#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21))
-#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21
-#define RTC_CNTL_BIAS_CORE_FOLW_12M (BIT(20))
-#define RTC_CNTL_BIAS_CORE_FOLW_12M_S 20
-#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19))
-#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19
-#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18))
-#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18
-#define RTC_CNTL_BIAS_I2C_FOLW_12M (BIT(17))
-#define RTC_CNTL_BIAS_I2C_FOLW_12M_S 17
-#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16))
-#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16
-#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15))
-#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15
-#define RTC_CNTL_BIAS_SLEEP_FOLW_12M (BIT(14))
-#define RTC_CNTL_BIAS_SLEEP_FOLW_12M_S 14
-#define RTC_CNTL_XTL_FORCE_PU (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_S 13
-#define RTC_CNTL_XTL_FORCE_PD (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_S 12
-#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_S 11
-#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_S 10
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8
-#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_S 7
-#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_S 6
-#define RTC_CNTL_SW_PROCPU_RST (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_S 5
-#define RTC_CNTL_SW_APPCPU_RST (BIT(4))
-#define RTC_CNTL_SW_APPCPU_RST_S 4
-#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003
-#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2
-#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003
-#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0
-
-#define RTC_SLP_TIMER0 (DR_REG_RTCCNTL_BASE + 0x4)
-#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_S 0
-
-#define RTC_SLP_TIMER1 (DR_REG_RTCCNTL_BASE + 0x8)
-#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN (BIT(16))
-#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_S 16
-#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF
-#define RTC_CNTL_SLP_VAL_HI_S 0
-
-#define RTC_TIME_UPDATE (DR_REG_RTCCNTL_BASE + 0xc)
-#define RTC_CNTL_RTC_TIME_UPDATE (BIT(31))
-#define RTC_CNTL_RTC_TIME_UPDATE_S 31
-#define RTC_CNTL_RTC_TIME_VALID (BIT(30))
-#define RTC_CNTL_RTC_TIME_VALID_S 30
-
-#define RTC_TIME0 (DR_REG_RTCCNTL_BASE + 0x10)
-#define RTC_CNTL_RTC_TIME_LO 0xFFFFFFFF
-#define RTC_CNTL_RTC_TIME_LO_S 0
-
-#define RTC_TIME1 (DR_REG_RTCCNTL_BASE + 0x14)
-#define RTC_CNTL_RTC_TIME_HI 0x0000FFFF
-#define RTC_CNTL_RTC_TIME_HI_S 0
-
-#define RTC_STATE0 (DR_REG_RTCCNTL_BASE + 0x18)
-#define RTC_CNTL_SLEEP_EN (BIT(31))
-#define RTC_CNTL_SLEEP_EN_S 31
-#define RTC_CNTL_SLP_REJECT (BIT(30))
-#define RTC_CNTL_SLP_REJECT_S 30
-#define RTC_CNTL_SLP_WAKEUP (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_S 29
-#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_S 28
-#define RTC_CNTL_SAR_SLP_TIMER_EN (BIT(24))
-#define RTC_CNTL_SAR_SLP_TIMER_EN_S 24
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23))
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22
-#define RTC_CNTL_SAR_WAKEUP_FORCE_EN (BIT(21))
-#define RTC_CNTL_SAR_WAKEUP_FORCE_EN_S 21
-#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20))
-#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20
-
-#define RTC_TIMER1 (DR_REG_RTCCNTL_BASE + 0x1c)
-#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF
-#define RTC_CNTL_PLL_BUF_WAIT_S 24
-#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF
-#define RTC_CNTL_XTL_BUF_WAIT_S 14
-#define RTC_CNTL_CK12M_WAIT 0x000000FF
-#define RTC_CNTL_CK12M_WAIT_S 6
-#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F
-#define RTC_CNTL_CPU_STALL_WAIT_S 1
-#define RTC_CNTL_CPU_STALL_EN (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_S 0
-
-#define RTC_TIMER2 (DR_REG_RTCCNTL_BASE + 0x20)
-#define RTC_CNTL_MIN_TIME_CK12M_OFF 0x000000FF
-#define RTC_CNTL_MIN_TIME_CK12M_OFF_S 24
-#define RTC_CNTL_SAR_TOUCH_START_WAIT 0x000001FF
-#define RTC_CNTL_SAR_TOUCH_START_WAIT_S 15
-
-#define RTC_TIMER3 (DR_REG_RTCCNTL_BASE + 0x24)
-#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F
-#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25
-#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF
-#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16
-#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F
-#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9
-#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF
-#define RTC_CNTL_WIFI_WAIT_TIMER_S 0
-
-#define RTC_TIMER4 (DR_REG_RTCCNTL_BASE + 0x28)
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16
-#define RTC_CNTL_RTC_POWERUP_TIMER 0x0000007F
-#define RTC_CNTL_RTC_POWERUP_TIMER_S 9
-#define RTC_CNTL_RTC_WAIT_TIMER 0x000001FF
-#define RTC_CNTL_RTC_WAIT_TIMER_S 0
-
-#define RTC_TIMER5 (DR_REG_RTCCNTL_BASE + 0x2c)
-#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F
-#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25
-#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF
-#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16
-#define RTC_CNTL_MIN_SLP_VAL 0x000000FF
-#define RTC_CNTL_MIN_SLP_VAL_S 8
-#define RTC_CNTL_SAR_SUBTIMER_PREDIV 0x000000FF
-#define RTC_CNTL_SAR_SUBTIMER_PREDIV_S 0
-
-#define RTC_ANA_CONF (DR_REG_RTCCNTL_BASE + 0x30)
-#define RTC_CNTL_PLL_I2C_PU (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_S 31
-#define RTC_CNTL_CKGEN_I2C_PU (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_S 30
-#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_S 28
-#define RTC_CNTL_TXRF_I2C_PU (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_S 27
-#define RTC_CNTL_PVTMON_PU (BIT(26))
-#define RTC_CNTL_PVTMON_PU_S 26
-#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25
-#define RTC_CNTL_PLLA_FORCE_PU (BIT(24))
-#define RTC_CNTL_PLLA_FORCE_PU_S 24
-#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))
-#define RTC_CNTL_PLLA_FORCE_PD_S 23
-
-#define RTC_RESET_STATE (DR_REG_RTCCNTL_BASE + 0x34)
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13))
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12))
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12
-#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F
-#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6
-#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0
-
-#define RTC_WAKEUP_STATE (DR_REG_RTCCNTL_BASE + 0x38)
-#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22
-#define RTC_CNTL_RTC_WAKEUP_ENA 0x000007FF
-#define RTC_CNTL_RTC_WAKEUP_ENA_S 11
-#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF
-#define RTC_CNTL_WAKEUP_CAUSE_S 0
-
-#define INT_ENA_RTC (DR_REG_RTCCNTL_BASE + 0x3c)
-#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA (BIT(8))
-#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_S 8
-#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA (BIT(7))
-#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_S 7
-#define RTC_CNTL_RTC_TOUCH_INT_ENA (BIT(6))
-#define RTC_CNTL_RTC_TOUCH_INT_ENA_S 6
-#define RTC_CNTL_RTC_SAR_INT_ENA (BIT(5))
-#define RTC_CNTL_RTC_SAR_INT_ENA_S 5
-#define RTC_CNTL_RTC_TIME_VALID_INT_ENA (BIT(4))
-#define RTC_CNTL_RTC_TIME_VALID_INT_ENA_S 4
-#define RTC_CNTL_RTC_WDT_INT_ENA (BIT(3))
-#define RTC_CNTL_RTC_WDT_INT_ENA_S 3
-#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2
-#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0
-
-#define INT_RAW_RTC (DR_REG_RTCCNTL_BASE + 0x40)
-#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW (BIT(8))
-#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_S 8
-#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW (BIT(7))
-#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_S 7
-#define RTC_CNTL_RTC_TOUCH_INT_RAW (BIT(6))
-#define RTC_CNTL_RTC_TOUCH_INT_RAW_S 6
-#define RTC_CNTL_RTC_SAR_INT_RAW (BIT(5))
-#define RTC_CNTL_RTC_SAR_INT_RAW_S 5
-#define RTC_CNTL_RTC_TIME_VALID_INT_RAW (BIT(4))
-#define RTC_CNTL_RTC_TIME_VALID_INT_RAW_S 4
-#define RTC_CNTL_RTC_WDT_INT_RAW (BIT(3))
-#define RTC_CNTL_RTC_WDT_INT_RAW_S 3
-#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2
-#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0
-
-#define INT_ST_RTC (DR_REG_RTCCNTL_BASE + 0x44)
-#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST (BIT(8))
-#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_S 8
-#define RTC_CNTL_RTC_BROWN_OUT_INT_ST (BIT(7))
-#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_S 7
-#define RTC_CNTL_RTC_TOUCH_INT_ST (BIT(6))
-#define RTC_CNTL_RTC_TOUCH_INT_ST_S 6
-#define RTC_CNTL_RTC_SAR_INT_ST (BIT(5))
-#define RTC_CNTL_RTC_SAR_INT_ST_S 5
-#define RTC_CNTL_RTC_TIME_VALID_INT_ST (BIT(4))
-#define RTC_CNTL_RTC_TIME_VALID_INT_ST_S 4
-#define RTC_CNTL_RTC_WDT_INT_ST (BIT(3))
-#define RTC_CNTL_RTC_WDT_INT_ST_S 3
-#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2
-#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_S 1
-#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0
-
-#define INT_CLR_RTC (DR_REG_RTCCNTL_BASE + 0x48)
-#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR (BIT(8))
-#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_S 8
-#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR (BIT(7))
-#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_S 7
-#define RTC_CNTL_RTC_TOUCH_INT_CLR (BIT(6))
-#define RTC_CNTL_RTC_TOUCH_INT_CLR_S 6
-#define RTC_CNTL_RTC_SAR_INT_CLR (BIT(5))
-#define RTC_CNTL_RTC_SAR_INT_CLR_S 5
-#define RTC_CNTL_RTC_TIME_VALID_INT_CLR (BIT(4))
-#define RTC_CNTL_RTC_TIME_VALID_INT_CLR_S 4
-#define RTC_CNTL_RTC_WDT_INT_CLR (BIT(3))
-#define RTC_CNTL_RTC_WDT_INT_CLR_S 3
-#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2
-#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0
-
-#define RTC_STORE0 (DR_REG_RTCCNTL_BASE + 0x4c)
-#define RTC_CNTL_RTC_SCRATCH0 0xFFFFFFFF
-#define RTC_CNTL_RTC_SCRATCH0_S 0
-
-#define RTC_STORE1 (DR_REG_RTCCNTL_BASE + 0x50)
-#define RTC_CNTL_RTC_SCRATCH1 0xFFFFFFFF
-#define RTC_CNTL_RTC_SCRATCH1_S 0
-
-#define RTC_STORE2 (DR_REG_RTCCNTL_BASE + 0x54)
-#define RTC_CNTL_RTC_SCRATCH2 0xFFFFFFFF
-#define RTC_CNTL_RTC_SCRATCH2_S 0
-
-#define RTC_STORE3 (DR_REG_RTCCNTL_BASE + 0x58)
-#define RTC_CNTL_RTC_SCRATCH3 0xFFFFFFFF
-#define RTC_CNTL_RTC_SCRATCH3_S 0
-
-#define RTC_EXT_XTL_CONF (DR_REG_RTCCNTL_BASE + 0x5c)
-#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_S 31
-#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_S 30
-
-#define RTC_EXT_WAKEUP_CONF (DR_REG_RTCCNTL_BASE + 0x60)
-#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31))
-#define RTC_CNTL_EXT_WAKEUP1_LV_S 31
-#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30))
-#define RTC_CNTL_EXT_WAKEUP0_LV_S 30
-
-#define RTC_SLP_REJECT_CONF (DR_REG_RTCCNTL_BASE + 0x64)
-#define RTC_CNTL_REJECT_CAUSE 0x0000000F
-#define RTC_CNTL_REJECT_CAUSE_S 28
-#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26
-#define RTC_CNTL_SDIO_REJECT_EN (BIT(25))
-#define RTC_CNTL_SDIO_REJECT_EN_S 25
-#define RTC_CNTL_GPIO_REJECT_EN (BIT(24))
-#define RTC_CNTL_GPIO_REJECT_EN_S 24
-
-#define RTC_CPU_PERIOD_CONF (DR_REG_RTCCNTL_BASE + 0x68)
-#define RTC_CNTL_RTC_CPUPERIOD_SEL 0x00000003
-#define RTC_CNTL_RTC_CPUPERIOD_SEL_S 30
-#define RTC_CNTL_RTC_CPUSEL_CONF (BIT(29))
-#define RTC_CNTL_RTC_CPUSEL_CONF_S 29
-
-#define RTC_SDIO_ACT_CONF (DR_REG_RTCCNTL_BASE + 0x6c)
-#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF
-#define RTC_CNTL_SDIO_ACT_DNUM_S 22
-
-#define RTC_CLK_CONF (DR_REG_RTCCNTL_BASE + 0x70)
-#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003
-#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30
-#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
-#define RTC_CNTL_SOC_CLK_SEL 0x00000003
-#define RTC_CNTL_SOC_CLK_SEL_S 27
-#define RTC_CNTL_CK12M_FORCE_PU (BIT(26))
-#define RTC_CNTL_CK12M_FORCE_PU_S 26
-#define RTC_CNTL_CK12M_FORCE_PD (BIT(25))
-#define RTC_CNTL_CK12M_FORCE_PD_S 25
-#define RTC_CNTL_CK12M_DFREQ 0x000000FF
-#define RTC_CNTL_CK12M_DFREQ_S 17
-#define RTC_CNTL_CK12M_FORCE_NOGATING (BIT(16))
-#define RTC_CNTL_CK12M_FORCE_NOGATING_S 16
-#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15
-#define RTC_CNTL_CK12M_DIV_SEL 0x00000007
-#define RTC_CNTL_CK12M_DIV_SEL_S 12
-#define RTC_CNTL_CK12M_DFREQ_FORCE (BIT(11))
-#define RTC_CNTL_CK12M_DFREQ_FORCE_S 11
-#define RTC_CNTL_DIG_CLK12M_EN (BIT(10))
-#define RTC_CNTL_DIG_CLK12M_EN_S 10
-#define RTC_CNTL_DIG_CLK12M_D256_EN (BIT(9))
-#define RTC_CNTL_DIG_CLK12M_D256_EN_S 9
-#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_S 8
-#define RTC_CNTL_ENB_CK12M_DIV (BIT(7))
-#define RTC_CNTL_ENB_CK12M_DIV_S 7
-#define RTC_CNTL_ENB_CK12M (BIT(6))
-#define RTC_CNTL_ENB_CK12M_S 6
-#define RTC_CNTL_CK12M_DIV 0x00000003
-#define RTC_CNTL_CK12M_DIV_S 4
-
-#define RTC_SDIO_CONF (DR_REG_RTCCNTL_BASE + 0x74)
-#define RTC_CNTL_XPD_SDIO_REG (BIT(31))
-#define RTC_CNTL_XPD_SDIO_REG_S 31
-#define RTC_CNTL_DREFH_SDIO 0x00000003
-#define RTC_CNTL_DREFH_SDIO_S 29
-#define RTC_CNTL_DREFM_SDIO 0x00000003
-#define RTC_CNTL_DREFM_SDIO_S 27
-#define RTC_CNTL_DREFL_SDIO 0x00000003
-#define RTC_CNTL_DREFL_SDIO_S 25
-#define RTC_CNTL_REG1P8_READY (BIT(24))
-#define RTC_CNTL_REG1P8_READY_S 24
-#define RTC_CNTL_SDIO_TIEH (BIT(23))
-#define RTC_CNTL_SDIO_TIEH_S 23
-#define RTC_CNTL_SDIO_FORCE (BIT(22))
-#define RTC_CNTL_SDIO_FORCE_S 22
-#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21))
-#define RTC_CNTL_SDIO_REG_PD_EN_S 21
-
-#define RTC_BIAS_CONF (DR_REG_RTCCNTL_BASE + 0x78)
-#define RTC_CNTL_RST_BIAS_I2C (BIT(31))
-#define RTC_CNTL_RST_BIAS_I2C_S 31
-#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30))
-#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30
-#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29))
-#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29
-#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28))
-#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28
-#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27))
-#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27
-#define RTC_CNTL_ENB_SCK_XTAL (BIT(26))
-#define RTC_CNTL_ENB_SCK_XTAL_S 26
-#define RTC_CNTL_DBG_ATTEN 0x00000003
-#define RTC_CNTL_DBG_ATTEN_S 24
-
-#define RTC_REG (DR_REG_RTCCNTL_BASE + 0x7c)
-#define RTC_CNTL_RTC_REG_FORCE_PU (BIT(31))
-#define RTC_CNTL_RTC_REG_FORCE_PU_S 31
-#define RTC_CNTL_RTC_REG_FORCE_PD (BIT(30))
-#define RTC_CNTL_RTC_REG_FORCE_PD_S 30
-#define RTC_CNTL_RTC_DBOOST_FORCE_PU (BIT(29))
-#define RTC_CNTL_RTC_DBOOST_FORCE_PU_S 29
-#define RTC_CNTL_RTC_DBOOST_FORCE_PD (BIT(28))
-#define RTC_CNTL_RTC_DBOOST_FORCE_PD_S 28
-#define RTC_CNTL_RTC_DBIAS_WAK 0x00000007
-#define RTC_CNTL_RTC_DBIAS_WAK_S 25
-#define RTC_CNTL_RTC_DBIAS_SLP 0x00000007
-#define RTC_CNTL_RTC_DBIAS_SLP_S 22
-#define RTC_CNTL_SCK_DCAP 0x000000FF
-#define RTC_CNTL_SCK_DCAP_S 14
-#define RTC_CNTL_DIG_REG_DBIAS_WAK 0x00000007
-#define RTC_CNTL_DIG_REG_DBIAS_WAK_S 11
-#define RTC_CNTL_DIG_REG_DBIAS_SLP 0x00000007
-#define RTC_CNTL_DIG_REG_DBIAS_SLP_S 8
-#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7))
-#define RTC_CNTL_SCK_DCAP_FORCE_S 7
-
-#define RTC_PWC (DR_REG_RTCCNTL_BASE + 0x80)
-#define RTC_CNTL_RTC_PD_EN (BIT(20))
-#define RTC_CNTL_RTC_PD_EN_S 20
-#define RTC_CNTL_RTC_FORCE_PU (BIT(19))
-#define RTC_CNTL_RTC_FORCE_PU_S 19
-#define RTC_CNTL_RTC_FORCE_PD (BIT(18))
-#define RTC_CNTL_RTC_FORCE_PD_S 18
-#define RTC_CNTL_RTC_SLOWMEM_PD_EN (BIT(17))
-#define RTC_CNTL_RTC_SLOWMEM_PD_EN_S 17
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_PU (BIT(16))
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_PU_S 16
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_PD (BIT(15))
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_PD_S 15
-#define RTC_CNTL_RTC_FASTMEM_PD_EN (BIT(14))
-#define RTC_CNTL_RTC_FASTMEM_PD_EN_S 14
-#define RTC_CNTL_RTC_FASTMEM_FORCE_PU (BIT(13))
-#define RTC_CNTL_RTC_FASTMEM_FORCE_PU_S 13
-#define RTC_CNTL_RTC_FASTMEM_FORCE_PD (BIT(12))
-#define RTC_CNTL_RTC_FASTMEM_FORCE_PD_S 12
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU (BIT(11))
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_S 11
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD (BIT(10))
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_S 10
-#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU (BIT(9))
-#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_S 9
-#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU (BIT(8))
-#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_S 8
-#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD (BIT(7))
-#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_S 7
-#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU (BIT(6))
-#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_S 6
-#define RTC_CNTL_RTC_FORCE_NOISO (BIT(5))
-#define RTC_CNTL_RTC_FORCE_NOISO_S 5
-#define RTC_CNTL_RTC_FORCE_ISO (BIT(4))
-#define RTC_CNTL_RTC_FORCE_ISO_S 4
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO (BIT(3))
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_S 3
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO (BIT(2))
-#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_S 2
-#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO (BIT(1))
-#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_S 1
-#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO (BIT(0))
-#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_S 0
-
-#define DIG_PWC (DR_REG_RTCCNTL_BASE + 0x84)
-#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_S 31
-#define RTC_CNTL_WIFI_PD_EN (BIT(30))
-#define RTC_CNTL_WIFI_PD_EN_S 30
-#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29))
-#define RTC_CNTL_INTER_RAM4_PD_EN_S 29
-#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28))
-#define RTC_CNTL_INTER_RAM3_PD_EN_S 28
-#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27))
-#define RTC_CNTL_INTER_RAM2_PD_EN_S 27
-#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26))
-#define RTC_CNTL_INTER_RAM1_PD_EN_S 26
-#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25))
-#define RTC_CNTL_INTER_RAM0_PD_EN_S 25
-#define RTC_CNTL_ROM0_PD_EN (BIT(24))
-#define RTC_CNTL_ROM0_PD_EN_S 24
-#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20
-#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19
-#define RTC_CNTL_WIFI_FORCE_PU (BIT(18))
-#define RTC_CNTL_WIFI_FORCE_PU_S 18
-#define RTC_CNTL_WIFI_FORCE_PD (BIT(17))
-#define RTC_CNTL_WIFI_FORCE_PD_S 17
-#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16))
-#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16
-#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15))
-#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15
-#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14))
-#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14
-#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13))
-#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13
-#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12))
-#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12
-#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11))
-#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11
-#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10))
-#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10
-#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9))
-#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9
-#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8))
-#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8
-#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7))
-#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7
-#define RTC_CNTL_ROM0_FORCE_PU (BIT(6))
-#define RTC_CNTL_ROM0_FORCE_PU_S 6
-#define RTC_CNTL_ROM0_FORCE_PD (BIT(5))
-#define RTC_CNTL_ROM0_FORCE_PD_S 5
-#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4
-#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3
-
-#define DIG_ISO (DR_REG_RTCCNTL_BASE + 0x88)
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31
-#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30
-#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29))
-#define RTC_CNTL_WIFI_FORCE_NOISO_S 29
-#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28))
-#define RTC_CNTL_WIFI_FORCE_ISO_S 28
-#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27))
-#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27
-#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26))
-#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26
-#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25))
-#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25
-#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24))
-#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24
-#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23))
-#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23
-#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22))
-#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22
-#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21))
-#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21
-#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20))
-#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20
-#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19))
-#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19
-#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18))
-#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18
-#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17))
-#define RTC_CNTL_ROM0_FORCE_NOISO_S 17
-#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16))
-#define RTC_CNTL_ROM0_FORCE_ISO_S 16
-#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14
-#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13
-#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10
-#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9
-#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8
-#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7
-
-#define RTC_WDTCONFIG0 (DR_REG_RTCCNTL_BASE + 0x8c)
-#define RTC_CNTL_WDT_EN (BIT(31))
-#define RTC_CNTL_WDT_EN_S 31
-#define RTC_CNTL_WDT_STG0 0x00000007
-#define RTC_CNTL_WDT_STG0_S 28
-#define RTC_CNTL_WDT_STG1 0x00000007
-#define RTC_CNTL_WDT_STG1_S 25
-#define RTC_CNTL_WDT_STG2 0x00000007
-#define RTC_CNTL_WDT_STG2_S 22
-#define RTC_CNTL_WDT_STG3 0x00000007
-#define RTC_CNTL_WDT_STG3_S 19
-#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18))
-#define RTC_CNTL_WDT_EDGE_INT_EN_S 18
-#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17))
-#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10
-#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9
-#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8))
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8
-#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7
-
-#define RTC_WDTCONFIG1 (DR_REG_RTCCNTL_BASE + 0x90)
-#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_S 0
-
-#define RTC_WDTCONFIG2 (DR_REG_RTCCNTL_BASE + 0x94)
-#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_S 0
-
-#define RTC_WDTCONFIG3 (DR_REG_RTCCNTL_BASE + 0x98)
-#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_S 0
-
-#define RTC_WDTCONFIG4 (DR_REG_RTCCNTL_BASE + 0x9c)
-#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_S 0
-
-#define RTC_WDTFEED (DR_REG_RTCCNTL_BASE + 0xa0)
-#define RTC_CNTL_RTC_WDT_FEED (BIT(31))
-#define RTC_CNTL_RTC_WDT_FEED_S 31
-
-#define RTC_WDTWPROTECT (DR_REG_RTCCNTL_BASE + 0xa4)
-#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_S 0
-
-#define RTC_TEST_MUX (DR_REG_RTCCNTL_BASE + 0xa8)
-#define RTC_CNTL_DTEST_RTC 0x00000003
-#define RTC_CNTL_DTEST_RTC_S 30
-#define RTC_CNTL_ENT_RTC (BIT(29))
-#define RTC_CNTL_ENT_RTC_S 29
-
-#define RTC_SW_CPU_STALL (DR_REG_RTCCNTL_BASE + 0xac)
-#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26
-#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F
-#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20
-
-#define RTC_STORE4 (DR_REG_RTCCNTL_BASE + 0xb0)
-#define RTC_CNTL_RTC_SCRATCH4 0xFFFFFFFF
-#define RTC_CNTL_RTC_SCRATCH4_S 0
-
-#define RTC_STORE5 (DR_REG_RTCCNTL_BASE + 0xb4)
-#define RTC_CNTL_RTC_SCRATCH5 0xFFFFFFFF
-#define RTC_CNTL_RTC_SCRATCH5_S 0
-
-#define RTC_STORE6 (DR_REG_RTCCNTL_BASE + 0xb8)
-#define RTC_CNTL_RTC_SCRATCH6 0xFFFFFFFF
-#define RTC_CNTL_RTC_SCRATCH6_S 0
-
-#define RTC_STORE7 (DR_REG_RTCCNTL_BASE + 0xbc)
-#define RTC_CNTL_RTC_SCRATCH7 0xFFFFFFFF
-#define RTC_CNTL_RTC_SCRATCH7_S 0
-
-#define RTC_DIAG0 (DR_REG_RTCCNTL_BASE + 0xc0)
-#define RTC_CNTL_RTC_LOW_POWER_DIAG0 0xFFFFFFFF
-#define RTC_CNTL_RTC_LOW_POWER_DIAG0_S 0
-
-#define RTC_DIAG1 (DR_REG_RTCCNTL_BASE + 0xc4)
-#define RTC_CNTL_RTC_LOW_POWER_DIAG1 0xFFFFFFFF
-#define RTC_CNTL_RTC_LOW_POWER_DIAG1_S 0
-
-#define RTC_HOLD_FORCE (DR_REG_RTCCNTL_BASE + 0xc8)
-#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17))
-#define RTC_CNTL_X32N_HOLD_FORCE_S 17
-#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16))
-#define RTC_CNTL_X32P_HOLD_FORCE_S 16
-#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15))
-#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15
-#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14))
-#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14
-#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13))
-#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13
-#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12))
-#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12
-#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11))
-#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11
-#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10))
-#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10
-#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9))
-#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9
-#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8))
-#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8
-#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7))
-#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7
-#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6))
-#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6
-#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5))
-#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5
-#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4))
-#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4
-#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3))
-#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3
-#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2))
-#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2
-#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1))
-#define RTC_CNTL_ADC2_HOLD_FORCE_S 1
-#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0))
-#define RTC_CNTL_ADC1_HOLD_FORCE_S 0
-
-#define RTC_EXT_WAKEUP1 (DR_REG_RTCCNTL_BASE + 0xcc)
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18))
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18
-#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF
-#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0
-
-#define RTC_EXT_WAKEUP1_STATUS (DR_REG_RTCCNTL_BASE + 0xd0)
-#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0
-
-#define RTC_BROWN_OUT (DR_REG_RTCCNTL_BASE + 0xd4)
-#define RTC_CNTL_RTC_BROWN_OUT_DET (BIT(31))
-#define RTC_CNTL_RTC_BROWN_OUT_DET_S 31
-#define RTC_CNTL_BROWN_OUT_ENA (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_S 30
-#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007
-#define RTC_CNTL_DBROWN_OUT_THRES_S 27
-#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26
-#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14
+#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78)
+/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: RST_BIAS_I2C*/
+#define RTC_CNTL_RST_BIAS_I2C (BIT(31))
+#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31))
+#define RTC_CNTL_RST_BIAS_I2C_V 0x1
+#define RTC_CNTL_RST_BIAS_I2C_S 31
+/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: DEC_HEARTBEAT_WIDTH*/
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30))
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30))
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30
+/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: INC_HEARTBEAT_PERIOD*/
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29))
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29))
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29
+/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: DEC_HEARTBEAT_PERIOD*/
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28))
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28))
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28
+/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: INC_HEARTBEAT_REFRESH*/
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27))
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27))
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27
+/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: ENB_SCK_XTAL*/
+#define RTC_CNTL_ENB_SCK_XTAL (BIT(26))
+#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26))
+#define RTC_CNTL_ENB_SCK_XTAL_V 0x1
+#define RTC_CNTL_ENB_SCK_XTAL_S 26
+/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */
+/*description: DBG_ATTEN*/
+#define RTC_CNTL_DBG_ATTEN 0x00000003
+#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S))
+#define RTC_CNTL_DBG_ATTEN_V 0x3
+#define RTC_CNTL_DBG_ATTEN_S 24
+
+#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c)
+/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: RTC_REG force power up*/
+#define RTC_CNTL_FORCE_PU (BIT(31))
+#define RTC_CNTL_FORCE_PU_M (BIT(31))
+#define RTC_CNTL_FORCE_PU_V 0x1
+#define RTC_CNTL_FORCE_PU_S 31
+/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: RTC_REG force power down (for RTC_REG power down means decrease
+ the voltage to 0.8v or lower )*/
+#define RTC_CNTL_FORCE_PD (BIT(30))
+#define RTC_CNTL_FORCE_PD_M (BIT(30))
+#define RTC_CNTL_FORCE_PD_V 0x1
+#define RTC_CNTL_FORCE_PD_S 30
+/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: RTC_DBOOST force power up*/
+#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1
+#define RTC_CNTL_DBOOST_FORCE_PU_S 29
+/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RTC_DBOOST force power down*/
+#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1
+#define RTC_CNTL_DBOOST_FORCE_PD_S 28
+/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
+/*description: RTC_DBIAS during wakeup*/
+#define RTC_CNTL_DBIAS_WAK 0x00000007
+#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S))
+#define RTC_CNTL_DBIAS_WAK_V 0x7
+#define RTC_CNTL_DBIAS_WAK_S 25
+/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */
+/*description: RTC_DBIAS during sleep*/
+#define RTC_CNTL_DBIAS_SLP 0x00000007
+#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S))
+#define RTC_CNTL_DBIAS_SLP_V 0x7
+#define RTC_CNTL_DBIAS_SLP_S 22
+/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
+/*description: SCK_DCAP*/
+#define RTC_CNTL_SCK_DCAP 0x000000FF
+#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
+#define RTC_CNTL_SCK_DCAP_V 0xFF
+#define RTC_CNTL_SCK_DCAP_S 14
+/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
+/*description: DIG_REG_DBIAS during wakeup*/
+#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007
+#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S))
+#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7
+#define RTC_CNTL_DIG_DBIAS_WAK_S 11
+/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */
+/*description: DIG_REG_DBIAS during sleep*/
+#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007
+#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S))
+#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7
+#define RTC_CNTL_DIG_DBIAS_SLP_S 8
+/* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: N/A*/
+#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7))
+#define RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7))
+#define RTC_CNTL_SCK_DCAP_FORCE_V 0x1
+#define RTC_CNTL_SCK_DCAP_FORCE_S 7
+
+#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80)
+/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: enable power down rtc_peri in sleep*/
+#define RTC_CNTL_PD_EN (BIT(20))
+#define RTC_CNTL_PD_EN_M (BIT(20))
+#define RTC_CNTL_PD_EN_V 0x1
+#define RTC_CNTL_PD_EN_S 20
+/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: rtc_peri force power up*/
+#define RTC_CNTL_PWC_FORCE_PU (BIT(19))
+#define RTC_CNTL_PWC_FORCE_PU_M (BIT(19))
+#define RTC_CNTL_PWC_FORCE_PU_V 0x1
+#define RTC_CNTL_PWC_FORCE_PU_S 19
+/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc_peri force power down*/
+#define RTC_CNTL_PWC_FORCE_PD (BIT(18))
+#define RTC_CNTL_PWC_FORCE_PD_M (BIT(18))
+#define RTC_CNTL_PWC_FORCE_PD_V 0x1
+#define RTC_CNTL_PWC_FORCE_PD_S 18
+/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: enable power down RTC memory in sleep*/
+#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17))
+#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17))
+#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1
+#define RTC_CNTL_SLOWMEM_PD_EN_S 17
+/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: RTC memory force power up*/
+#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16))
+#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16))
+#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1
+#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16
+/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: RTC memory force power down*/
+#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15))
+#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15))
+#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1
+#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15
+/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable power down fast RTC memory in sleep*/
+#define RTC_CNTL_FASTMEM_PD_EN (BIT(14))
+#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14))
+#define RTC_CNTL_FASTMEM_PD_EN_V 0x1
+#define RTC_CNTL_FASTMEM_PD_EN_S 14
+/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: Fast RTC memory force power up*/
+#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13))
+#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13))
+#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1
+#define RTC_CNTL_FASTMEM_FORCE_PU_S 13
+/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Fast RTC memory force power down*/
+#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12))
+#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12))
+#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1
+#define RTC_CNTL_FASTMEM_FORCE_PD_S 12
+/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: RTC memory force no PD*/
+#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11))
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11))
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11
+/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC memory force PD*/
+#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10))
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10))
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10
+/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/
+#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9))
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9))
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9
+/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: Fast RTC memory force no PD*/
+#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8
+/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Fast RTC memory force PD*/
+#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7
+/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following
+ RTC state machine*/
+#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6))
+#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6))
+#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1
+#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6
+/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */
+/*description: rtc_peri force no ISO*/
+#define RTC_CNTL_FORCE_NOISO (BIT(5))
+#define RTC_CNTL_FORCE_NOISO_M (BIT(5))
+#define RTC_CNTL_FORCE_NOISO_V 0x1
+#define RTC_CNTL_FORCE_NOISO_S 5
+/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: rtc_peri force ISO*/
+#define RTC_CNTL_FORCE_ISO (BIT(4))
+#define RTC_CNTL_FORCE_ISO_M (BIT(4))
+#define RTC_CNTL_FORCE_ISO_V 0x1
+#define RTC_CNTL_FORCE_ISO_S 4
+/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC memory force ISO*/
+#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3))
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3))
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3
+/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: RTC memory force no ISO*/
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2))
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2))
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2
+/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Fast RTC memory force ISO*/
+#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1))
+#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1))
+#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1
+#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1
+/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Fast RTC memory force no ISO*/
+#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0))
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0))
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0
+
+#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84)
+/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */
+/*description: enable power down digital core in sleep*/
+#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1
+#define RTC_CNTL_DG_WRAP_PD_EN_S 31
+/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */
+/*description: enable power down wifi in sleep*/
+#define RTC_CNTL_WIFI_PD_EN (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_M (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_V 0x1
+#define RTC_CNTL_WIFI_PD_EN_S 30
+/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */
+/*description: enable power down internal SRAM 4 in sleep*/
+#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29))
+#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29))
+#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1
+#define RTC_CNTL_INTER_RAM4_PD_EN_S 29
+/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */
+/*description: enable power down internal SRAM 3 in sleep*/
+#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28))
+#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28))
+#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1
+#define RTC_CNTL_INTER_RAM3_PD_EN_S 28
+/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */
+/*description: enable power down internal SRAM 2 in sleep*/
+#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27))
+#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27))
+#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1
+#define RTC_CNTL_INTER_RAM2_PD_EN_S 27
+/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */
+/*description: enable power down internal SRAM 1 in sleep*/
+#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26))
+#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26))
+#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1
+#define RTC_CNTL_INTER_RAM1_PD_EN_S 26
+/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */
+/*description: enable power down internal SRAM 0 in sleep*/
+#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25))
+#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25))
+#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1
+#define RTC_CNTL_INTER_RAM0_PD_EN_S 25
+/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */
+/*description: enable power down ROM in sleep*/
+#define RTC_CNTL_ROM0_PD_EN (BIT(24))
+#define RTC_CNTL_ROM0_PD_EN_M (BIT(24))
+#define RTC_CNTL_ROM0_PD_EN_V 0x1
+#define RTC_CNTL_ROM0_PD_EN_S 24
+/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: digital core force power up*/
+#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20
+/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: digital core force power down*/
+#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19
+/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
+/*description: wifi force power up*/
+#define RTC_CNTL_WIFI_FORCE_PU (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_V 0x1
+#define RTC_CNTL_WIFI_FORCE_PU_S 18
+/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: wifi force power down*/
+#define RTC_CNTL_WIFI_FORCE_PD (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_V 0x1
+#define RTC_CNTL_WIFI_FORCE_PD_S 17
+/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: internal SRAM 4 force power up*/
+#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16))
+#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16))
+#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1
+#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16
+/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: internal SRAM 4 force power down*/
+#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15))
+#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15))
+#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1
+#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15
+/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */
+/*description: internal SRAM 3 force power up*/
+#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14))
+#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14))
+#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1
+#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14
+/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: internal SRAM 3 force power down*/
+#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13))
+#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13))
+#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1
+#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13
+/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: internal SRAM 2 force power up*/
+#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12))
+#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12))
+#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1
+#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12
+/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: internal SRAM 2 force power down*/
+#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11))
+#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11))
+#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1
+#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11
+/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */
+/*description: internal SRAM 1 force power up*/
+#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10))
+#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10))
+#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1
+#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10
+/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: internal SRAM 1 force power down*/
+#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9))
+#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9))
+#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1
+#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9
+/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */
+/*description: internal SRAM 0 force power up*/
+#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8))
+#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8))
+#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1
+#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8
+/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: internal SRAM 0 force power down*/
+#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7))
+#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7))
+#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1
+#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7
+/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */
+/*description: ROM force power up*/
+#define RTC_CNTL_ROM0_FORCE_PU (BIT(6))
+#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6))
+#define RTC_CNTL_ROM0_FORCE_PU_V 0x1
+#define RTC_CNTL_ROM0_FORCE_PU_S 6
+/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ROM force power down*/
+#define RTC_CNTL_ROM0_FORCE_PD (BIT(5))
+#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5))
+#define RTC_CNTL_ROM0_FORCE_PD_V 0x1
+#define RTC_CNTL_ROM0_FORCE_PD_S 5
+/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: memories in digital core force no PD in sleep*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4
+/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: memories in digital core force PD in sleep*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3
+
+#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88)
+/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: digital core force no ISO*/
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31
+/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force ISO*/
+#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30
+/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: wifi force no ISO*/
+#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1
+#define RTC_CNTL_WIFI_FORCE_NOISO_S 29
+/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: wifi force ISO*/
+#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1
+#define RTC_CNTL_WIFI_FORCE_ISO_S 28
+/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: internal SRAM 4 force no ISO*/
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27))
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27))
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27
+/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: internal SRAM 4 force ISO*/
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26))
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26))
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26
+/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
+/*description: internal SRAM 3 force no ISO*/
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25))
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25))
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25
+/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: internal SRAM 3 force ISO*/
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24))
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24))
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24
+/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: internal SRAM 2 force no ISO*/
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23))
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23))
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23
+/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: internal SRAM 2 force ISO*/
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22))
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22))
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22
+/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */
+/*description: internal SRAM 1 force no ISO*/
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21))
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21))
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21
+/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: internal SRAM 1 force ISO*/
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20))
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20))
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20
+/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */
+/*description: internal SRAM 0 force no ISO*/
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19))
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19))
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19
+/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: internal SRAM 0 force ISO*/
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18))
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18))
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18
+/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */
+/*description: ROM force no ISO*/
+#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17))
+#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17))
+#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1
+#define RTC_CNTL_ROM0_FORCE_NOISO_S 17
+/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: ROM force ISO*/
+#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16))
+#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16))
+#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1
+#define RTC_CNTL_ROM0_FORCE_ISO_S 16
+/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: digital pad force hold*/
+#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15
+/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
+/*description: digital pad force un-hold*/
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14
+/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: digital pad force ISO*/
+#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13
+/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: digital pad force no ISO*/
+#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12
+/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: digital pad enable auto-hold*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11
+/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: wtite only register to clear digital pad auto-hold*/
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10
+/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: read only register to indicate digital pad auto-hold status*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9
+/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8
+/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7
+
+#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c)
+/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: enable RTC WDT*/
+#define RTC_CNTL_WDT_EN (BIT(31))
+#define RTC_CNTL_WDT_EN_M (BIT(31))
+#define RTC_CNTL_WDT_EN_V 0x1
+#define RTC_CNTL_WDT_EN_S 31
+/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset
+ stage en 4: RTC reset stage en*/
+#define RTC_CNTL_WDT_STG0 0x00000007
+#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
+#define RTC_CNTL_WDT_STG0_V 0x7
+#define RTC_CNTL_WDT_STG0_S 28
+/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset
+ stage en 4: RTC reset stage en*/
+#define RTC_CNTL_WDT_STG1 0x00000007
+#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
+#define RTC_CNTL_WDT_STG1_V 0x7
+#define RTC_CNTL_WDT_STG1_S 25
+/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset
+ stage en 4: RTC reset stage en*/
+#define RTC_CNTL_WDT_STG2 0x00000007
+#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
+#define RTC_CNTL_WDT_STG2_V 0x7
+#define RTC_CNTL_WDT_STG2_S 22
+/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset
+ stage en 4: RTC reset stage en*/
+#define RTC_CNTL_WDT_STG3 0x00000007
+#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
+#define RTC_CNTL_WDT_STG3_V 0x7
+#define RTC_CNTL_WDT_STG3_S 19
+/* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: N/A*/
+#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18))
+#define RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18))
+#define RTC_CNTL_WDT_EDGE_INT_EN_V 0x1
+#define RTC_CNTL_WDT_EDGE_INT_EN_S 18
+/* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: N/A*/
+#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17))
+#define RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17))
+#define RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1
+#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17
+/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */
+/*description: CPU reset counter length*/
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14
+/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */
+/*description: system reset counter length*/
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11
+/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: enable WDT in flash boot*/
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10
+/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: enable WDT reset PRO CPU*/
+#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9
+/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: enable WDT reset APP CPU*/
+#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8
+/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */
+/*description: pause WDT in sleep*/
+#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7
+
+#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90)
+/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */
+/*description: */
+#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
+#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_S 0
+
+#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94)
+/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
+/*description: */
+#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
+#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_S 0
+
+#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98)
+/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: */
+#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
+#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_S 0
+
+#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c)
+/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: */
+#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
+#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_S 0
+
+#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0)
+/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_WDT_FEED (BIT(31))
+#define RTC_CNTL_WDT_FEED_M (BIT(31))
+#define RTC_CNTL_WDT_FEED_V 0x1
+#define RTC_CNTL_WDT_FEED_S 31
+
+#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4)
+/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: */
+#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
+#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_S 0
+
+#define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8)
+/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: DTEST_RTC*/
+#define RTC_CNTL_DTEST_RTC 0x00000003
+#define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S))
+#define RTC_CNTL_DTEST_RTC_V 0x3
+#define RTC_CNTL_DTEST_RTC_S 30
+/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: ENT_RTC*/
+#define RTC_CNTL_ENT_RTC (BIT(29))
+#define RTC_CNTL_ENT_RTC_M (BIT(29))
+#define RTC_CNTL_ENT_RTC_V 0x1
+#define RTC_CNTL_ENT_RTC_S 29
+
+#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac)
+/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
+/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} ==
+ 0x86 will stall PRO CPU*/
+#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26
+/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} ==
+ 0x86 will stall APP CPU*/
+#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20
+
+#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0)
+/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: 32-bit general purpose retention register*/
+#define RTC_CNTL_SCRATCH4 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
+#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_S 0
+
+#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4)
+/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: 32-bit general purpose retention register*/
+#define RTC_CNTL_SCRATCH5 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
+#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_S 0
+
+#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8)
+/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: 32-bit general purpose retention register*/
+#define RTC_CNTL_SCRATCH6 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
+#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_S 0
+
+#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc)
+/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: 32-bit general purpose retention register*/
+#define RTC_CNTL_SCRATCH7 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
+#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_S 0
+
+#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0)
+/* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S))
+#define RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG0_S 0
+
+#define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4)
+/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
+#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_S 0
+
+#define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8)
+/* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17))
+#define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17))
+#define RTC_CNTL_X32N_HOLD_FORCE_V 0x1
+#define RTC_CNTL_X32N_HOLD_FORCE_S 17
+/* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16))
+#define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16))
+#define RTC_CNTL_X32P_HOLD_FORCE_V 0x1
+#define RTC_CNTL_X32P_HOLD_FORCE_S 16
+/* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15))
+#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15))
+#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1
+#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15
+/* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14))
+#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14))
+#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1
+#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14
+/* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13))
+#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13))
+#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1
+#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13
+/* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12))
+#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12))
+#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1
+#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12
+/* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11))
+#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11))
+#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1
+#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11
+/* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10))
+#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10))
+#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1
+#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10
+/* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9))
+#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9))
+#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1
+#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9
+/* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8))
+#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8))
+#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1
+#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8
+/* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7))
+#define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7))
+#define RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1
+#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7
+/* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6))
+#define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6))
+#define RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1
+#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6
+/* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5))
+#define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5))
+#define RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1
+#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5
+/* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4))
+#define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4))
+#define RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1
+#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4
+/* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3))
+#define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3))
+#define RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1
+#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3
+/* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2))
+#define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2))
+#define RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1
+#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2
+/* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1))
+#define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1))
+#define RTC_CNTL_ADC2_HOLD_FORCE_V 0x1
+#define RTC_CNTL_ADC2_HOLD_FORCE_S 1
+/* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0))
+#define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0))
+#define RTC_CNTL_ADC1_HOLD_FORCE_V 0x1
+#define RTC_CNTL_ADC1_HOLD_FORCE_S 0
+
+#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc)
+/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: clear ext wakeup1 status*/
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18
+/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: Bitmap to select RTC pads for ext wakeup1*/
+#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF
+#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S))
+#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF
+#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0
+
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0)
+/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: ext wakeup1 status*/
+#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0
+
+#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4)
+/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: brown out detect*/
+#define RTC_CNTL_BROWN_OUT_DET (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_V 0x1
+#define RTC_CNTL_BROWN_OUT_DET_S 31
+/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable brown out*/
+#define RTC_CNTL_BROWN_OUT_ENA (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_V 0x1
+#define RTC_CNTL_BROWN_OUT_ENA_S 30
+/* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */
+/*description: brown out threshold*/
+#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007
+#define RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S))
+#define RTC_CNTL_DBROWN_OUT_THRES_V 0x7
+#define RTC_CNTL_DBROWN_OUT_THRES_S 27
+/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: enable brown out reset*/
+#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26
+/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
+/*description: brown out reset wait cycles*/
+#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16
+/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable power down RF when brown out happens*/
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15
+/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable close flash when brown out happens*/
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14
#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4)
#define RTC_MEM_CRC_FINISH (BIT(31))
+#define RTC_MEM_CRC_FINISH_M (BIT(31))
+#define RTC_MEM_CRC_FINISH_V 0x1
#define RTC_MEM_CRC_FINISH_S (31)
#define RTC_MEM_CRC_LEN (0x7ff)
+#define RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S))
+#define RTC_MEM_CRC_LEN_V (0x7ff)
#define RTC_MEM_CRC_LEN_S (20)
#define RTC_MEM_CRC_ADDR (0x7ff)
+#define RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S))
+#define RTC_MEM_CRC_ADDR_V (0x7ff)
#define RTC_MEM_CRC_ADDR_S (9)
#define RTC_MEM_CRC_START (BIT(8))
+#define RTC_MEM_CRC_START_M (BIT(8))
+#define RTC_MEM_CRC_START_V 0x1
#define RTC_MEM_CRC_START_S (8)
#define RTC_MEM_PID_CONF (0xff)
+#define RTC_MEM_PID_CONF_M (0xff)
+#define RTC_MEM_PID_CONF_V (0xff)
#define RTC_MEM_PID_CONF_S (0)
#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4)
-
-#define RTC_CNTL_DATE (DR_REG_RTCCNTL_BASE + 0x13c)
-#define RTC_CNTL_RTC_CNTL_DATE 0x0FFFFFFF
-#define RTC_CNTL_RTC_CNTL_DATE_S 0
+#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c)
+/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */
+/*description: */
+#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF
+#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S))
+#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF
+#define RTC_CNTL_CNTL_DATE_S 0
#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280
-#endif /* _SOC_RTC_CNTL_REG_H_ */
+
+
+
+#endif /*_SOC_RTC_CNTL_REG_H_ */
+
+
#ifndef _SOC_RTC_IO_REG_H_
#define _SOC_RTC_IO_REG_H_
+
#include "soc.h"
+#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0)
+/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output value*/
+#define RTC_GPIO_OUT_DATA 0x0003FFFF
+#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S))
+#define RTC_GPIO_OUT_DATA_V 0x3FFFF
+#define RTC_GPIO_OUT_DATA_S 14
+
+#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4)
+/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output value write 1 to set*/
+#define RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF
+#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))
+#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFF
+#define RTC_GPIO_OUT_DATA_W1TS_S 14
+
+#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8)
+/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output value write 1 to clear*/
+#define RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF
+#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S))
+#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFF
+#define RTC_GPIO_OUT_DATA_W1TC_S 14
+
+#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc)
+/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output enable*/
+#define RTC_GPIO_ENABLE 0x0003FFFF
+#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S))
+#define RTC_GPIO_ENABLE_V 0x3FFFF
+#define RTC_GPIO_ENABLE_S 14
+
+#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10)
+/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output enable write 1 to set*/
+#define RTC_GPIO_ENABLE_W1TS 0x0003FFFF
+#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))
+#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFF
+#define RTC_GPIO_ENABLE_W1TS_S 14
+
+#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14)
+/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 output enable write 1 to clear*/
+#define RTC_GPIO_ENABLE_W1TC 0x0003FFFF
+#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S))
+#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFF
+#define RTC_GPIO_ENABLE_W1TC_S 14
+
+#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18)
+/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 interrupt status*/
+#define RTC_GPIO_STATUS_INT 0x0003FFFF
+#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S))
+#define RTC_GPIO_STATUS_INT_V 0x3FFFF
+#define RTC_GPIO_STATUS_INT_S 14
+
+#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c)
+/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 interrupt status write 1 to set*/
+#define RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF
+#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))
+#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFF
+#define RTC_GPIO_STATUS_INT_W1TS_S 14
+
+#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20)
+/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
+/*description: GPIO0~17 interrupt status write 1 to clear*/
+#define RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF
+#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S))
+#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFF
+#define RTC_GPIO_STATUS_INT_W1TC_S 14
+
+#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24)
+/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default: ; */
+/*description: GPIO0~17 input value*/
+#define RTC_GPIO_IN_NEXT 0x0003FFFF
+#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S))
+#define RTC_GPIO_IN_NEXT_V 0x3FFFF
+#define RTC_GPIO_IN_NEXT_S 14
+
+#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28)
+/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN0_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))
+#define RTC_GPIO_PIN0_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN0_INT_TYPE_S 7
+/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN0_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c)
+/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN1_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))
+#define RTC_GPIO_PIN1_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN1_INT_TYPE_S 7
+/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN1_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30)
+/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN2_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))
+#define RTC_GPIO_PIN2_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN2_INT_TYPE_S 7
+/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN2_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34)
+/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN3_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))
+#define RTC_GPIO_PIN3_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN3_INT_TYPE_S 7
+/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN3_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38)
+/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN4_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))
+#define RTC_GPIO_PIN4_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN4_INT_TYPE_S 7
+/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN4_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c)
+/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN5_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))
+#define RTC_GPIO_PIN5_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN5_INT_TYPE_S 7
+/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN5_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40)
+/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN6_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))
+#define RTC_GPIO_PIN6_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN6_INT_TYPE_S 7
+/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN6_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44)
+/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN7_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))
+#define RTC_GPIO_PIN7_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN7_INT_TYPE_S 7
+/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN7_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48)
+/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN8_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))
+#define RTC_GPIO_PIN8_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN8_INT_TYPE_S 7
+/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN8_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c)
+/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN9_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))
+#define RTC_GPIO_PIN9_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN9_INT_TYPE_S 7
+/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN9_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50)
+/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN10_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))
+#define RTC_GPIO_PIN10_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN10_INT_TYPE_S 7
+/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN10_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54)
+/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN11_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))
+#define RTC_GPIO_PIN11_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN11_INT_TYPE_S 7
+/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN11_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58)
+/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN12_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))
+#define RTC_GPIO_PIN12_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN12_INT_TYPE_S 7
+/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN12_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c)
+/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN13_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))
+#define RTC_GPIO_PIN13_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN13_INT_TYPE_S 7
+/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN13_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60)
+/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN14_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))
+#define RTC_GPIO_PIN14_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN14_INT_TYPE_S 7
+/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN14_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64)
+/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN15_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))
+#define RTC_GPIO_PIN15_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN15_INT_TYPE_S 7
+/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN15_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68)
+/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN16_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))
+#define RTC_GPIO_PIN16_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN16_INT_TYPE_S 7
+/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN16_PAD_DRIVER_S 2
-#define RTC_GPIO_OUT (DR_REG_RTCIO_BASE + 0x0)
-#define RTC_IO_RTC_GPIO_OUT_DATA 0x0003FFFF
-#define RTC_IO_RTC_GPIO_OUT_DATA_S 14
-
-#define RTC_GPIO_OUT_W1TS (DR_REG_RTCIO_BASE + 0x4)
-#define RTC_IO_RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF
-#define RTC_IO_RTC_GPIO_OUT_DATA_W1TS_S 14
-
-#define RTC_GPIO_OUT_W1TC (DR_REG_RTCIO_BASE + 0x8)
-#define RTC_IO_RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF
-#define RTC_IO_RTC_GPIO_OUT_DATA_W1TC_S 14
-
-#define RTC_GPIO_ENABLE (DR_REG_RTCIO_BASE + 0xc)
-#define RTC_IO_RTC_GPIO_ENABLE 0x0003FFFF
-#define RTC_IO_RTC_GPIO_ENABLE_S 14
-
-#define RTC_GPIO_ENABLE_W1TS (DR_REG_RTCIO_BASE + 0x10)
-#define RTC_IO_RTC_GPIO_ENABLE_W1TS 0x0003FFFF
-#define RTC_IO_RTC_GPIO_ENABLE_W1TS_S 14
-
-#define RTC_GPIO_ENABLE_W1TC (DR_REG_RTCIO_BASE + 0x14)
-#define RTC_IO_RTC_GPIO_ENABLE_W1TC 0x0003FFFF
-#define RTC_IO_RTC_GPIO_ENABLE_W1TC_S 14
-
-#define RTC_GPIO_STATUS (DR_REG_RTCIO_BASE + 0x18)
-#define RTC_IO_RTC_GPIO_STATUS_INT 0x0003FFFF
-#define RTC_IO_RTC_GPIO_STATUS_INT_S 14
-
-#define RTC_GPIO_STATUS_W1TS (DR_REG_RTCIO_BASE + 0x1c)
-#define RTC_IO_RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF
-#define RTC_IO_RTC_GPIO_STATUS_INT_W1TS_S 14
-
-#define RTC_GPIO_STATUS_W1TC (DR_REG_RTCIO_BASE + 0x20)
-#define RTC_IO_RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF
-#define RTC_IO_RTC_GPIO_STATUS_INT_W1TC_S 14
-
-#define RTC_GPIO_IN (DR_REG_RTCIO_BASE + 0x24)
-#define RTC_IO_RTC_GPIO_IN_NEXT 0x0003FFFF
-#define RTC_IO_RTC_GPIO_IN_NEXT_S 14
-
-#define RTC_GPIO_PIN0 (DR_REG_RTCIO_BASE + 0x28)
-#define RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN0_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN0_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN1 (DR_REG_RTCIO_BASE + 0x2c)
-#define RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN1_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN1_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN2 (DR_REG_RTCIO_BASE + 0x30)
-#define RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN2_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN2_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN3 (DR_REG_RTCIO_BASE + 0x34)
-#define RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN3_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN3_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN4 (DR_REG_RTCIO_BASE + 0x38)
-#define RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN4_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN4_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN5 (DR_REG_RTCIO_BASE + 0x3c)
-#define RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN5_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN5_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN6 (DR_REG_RTCIO_BASE + 0x40)
-#define RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN6_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN6_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN7 (DR_REG_RTCIO_BASE + 0x44)
-#define RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN7_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN7_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN8 (DR_REG_RTCIO_BASE + 0x48)
-#define RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN8_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN8_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN9 (DR_REG_RTCIO_BASE + 0x4c)
-#define RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN9_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN9_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN10 (DR_REG_RTCIO_BASE + 0x50)
-#define RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN10_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN10_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN11 (DR_REG_RTCIO_BASE + 0x54)
-#define RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN11_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN11_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN12 (DR_REG_RTCIO_BASE + 0x58)
-#define RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN12_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN12_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN13 (DR_REG_RTCIO_BASE + 0x5c)
-#define RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN13_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN13_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN14 (DR_REG_RTCIO_BASE + 0x60)
-#define RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN14_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN14_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN15 (DR_REG_RTCIO_BASE + 0x64)
-#define RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN15_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN15_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN16 (DR_REG_RTCIO_BASE + 0x68)
-#define RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN16_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN16_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER_S 2
-
-#define RTC_GPIO_PIN17 (DR_REG_RTCIO_BASE + 0x6c)
-#define RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
-#define RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10
-#define RTC_IO_RTC_GPIO_PIN17_INT_TYPE 0x00000007
-#define RTC_IO_RTC_GPIO_PIN17_INT_TYPE_S 7
-#define RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER (BIT(2))
-#define RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER_S 2
-
-#define RTC_DEBUG_SEL (DR_REG_RTCIO_BASE + 0x70)
-#define RTC_IO_RTC_DEBUG_12M_NO_GATING (BIT(25))
-#define RTC_IO_RTC_DEBUG_12M_NO_GATING_S 25
-#define RTC_IO_RTC_DEBUG_SEL4 0x0000001F
-#define RTC_IO_RTC_DEBUG_SEL4_S 20
-#define RTC_IO_RTC_DEBUG_SEL3 0x0000001F
-#define RTC_IO_RTC_DEBUG_SEL3_S 15
-#define RTC_IO_RTC_DEBUG_SEL2 0x0000001F
-#define RTC_IO_RTC_DEBUG_SEL2_S 10
-#define RTC_IO_RTC_DEBUG_SEL1 0x0000001F
-#define RTC_IO_RTC_DEBUG_SEL1_S 5
-#define RTC_IO_RTC_DEBUG_SEL0 0x0000001F
-#define RTC_IO_RTC_DEBUG_SEL0_S 0
-
-#define DIG_PAD_HOLD (DR_REG_RTCIO_BASE + 0x74)
-#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF
-#define RTC_IO_DIG_PAD_HOLD_S 0
-
-#define HALL_SENS (DR_REG_RTCIO_BASE + 0x78)
-#define RTC_IO_XPD_HALL (BIT(31))
-#define RTC_IO_XPD_HALL_S 31
-#define RTC_IO_HALL_PHASE (BIT(30))
-#define RTC_IO_HALL_PHASE_S 30
-
-#define SENSOR_PADS (DR_REG_RTCIO_BASE + 0x7c)
-#define RTC_IO_SENSE1_HOLD (BIT(31))
-#define RTC_IO_SENSE1_HOLD_S 31
-#define RTC_IO_SENSE2_HOLD (BIT(30))
-#define RTC_IO_SENSE2_HOLD_S 30
-#define RTC_IO_SENSE3_HOLD (BIT(29))
-#define RTC_IO_SENSE3_HOLD_S 29
-#define RTC_IO_SENSE4_HOLD (BIT(28))
-#define RTC_IO_SENSE4_HOLD_S 28
-#define RTC_IO_SENSE1_MUX_SEL (BIT(27))
-#define RTC_IO_SENSE1_MUX_SEL_S 27
-#define RTC_IO_SENSE2_MUX_SEL (BIT(26))
-#define RTC_IO_SENSE2_MUX_SEL_S 26
-#define RTC_IO_SENSE3_MUX_SEL (BIT(25))
-#define RTC_IO_SENSE3_MUX_SEL_S 25
-#define RTC_IO_SENSE4_MUX_SEL (BIT(24))
-#define RTC_IO_SENSE4_MUX_SEL_S 24
-#define RTC_IO_SENSE1_FUN_SEL 0x00000003
-#define RTC_IO_SENSE1_FUN_SEL_S 22
-#define RTC_IO_SENSE1_SLP_SEL (BIT(21))
-#define RTC_IO_SENSE1_SLP_SEL_S 21
-#define RTC_IO_SENSE1_SLP_IE (BIT(20))
-#define RTC_IO_SENSE1_SLP_IE_S 20
-#define RTC_IO_SENSE1_FUN_IE (BIT(19))
-#define RTC_IO_SENSE1_FUN_IE_S 19
-#define RTC_IO_SENSE2_FUN_SEL 0x00000003
-#define RTC_IO_SENSE2_FUN_SEL_S 17
-#define RTC_IO_SENSE2_SLP_SEL (BIT(16))
-#define RTC_IO_SENSE2_SLP_SEL_S 16
-#define RTC_IO_SENSE2_SLP_IE (BIT(15))
-#define RTC_IO_SENSE2_SLP_IE_S 15
-#define RTC_IO_SENSE2_FUN_IE (BIT(14))
-#define RTC_IO_SENSE2_FUN_IE_S 14
-#define RTC_IO_SENSE3_FUN_SEL 0x00000003
-#define RTC_IO_SENSE3_FUN_SEL_S 12
-#define RTC_IO_SENSE3_SLP_SEL (BIT(11))
-#define RTC_IO_SENSE3_SLP_SEL_S 11
-#define RTC_IO_SENSE3_SLP_IE (BIT(10))
-#define RTC_IO_SENSE3_SLP_IE_S 10
-#define RTC_IO_SENSE3_FUN_IE (BIT(9))
-#define RTC_IO_SENSE3_FUN_IE_S 9
-#define RTC_IO_SENSE4_FUN_SEL 0x00000003
-#define RTC_IO_SENSE4_FUN_SEL_S 7
-#define RTC_IO_SENSE4_SLP_SEL (BIT(6))
-#define RTC_IO_SENSE4_SLP_SEL_S 6
-#define RTC_IO_SENSE4_SLP_IE (BIT(5))
-#define RTC_IO_SENSE4_SLP_IE_S 5
-#define RTC_IO_SENSE4_FUN_IE (BIT(4))
-#define RTC_IO_SENSE4_FUN_IE_S 4
-
-#define ADC_PAD (DR_REG_RTCIO_BASE + 0x80)
-#define RTC_IO_ADC1_HOLD (BIT(31))
-#define RTC_IO_ADC1_HOLD_S 31
-#define RTC_IO_ADC2_HOLD (BIT(30))
-#define RTC_IO_ADC2_HOLD_S 30
-#define RTC_IO_ADC1_MUX_SEL (BIT(29))
-#define RTC_IO_ADC1_MUX_SEL_S 29
-#define RTC_IO_ADC2_MUX_SEL (BIT(28))
-#define RTC_IO_ADC2_MUX_SEL_S 28
-#define RTC_IO_ADC1_FUN_SEL 0x00000003
-#define RTC_IO_ADC1_FUN_SEL_S 26
-#define RTC_IO_ADC1_SLP_SEL (BIT(25))
-#define RTC_IO_ADC1_SLP_SEL_S 25
-#define RTC_IO_ADC1_SLP_IE (BIT(24))
-#define RTC_IO_ADC1_SLP_IE_S 24
-#define RTC_IO_ADC1_FUN_IE (BIT(23))
-#define RTC_IO_ADC1_FUN_IE_S 23
-#define RTC_IO_ADC2_FUN_SEL 0x00000003
-#define RTC_IO_ADC2_FUN_SEL_S 21
-#define RTC_IO_ADC2_SLP_SEL (BIT(20))
-#define RTC_IO_ADC2_SLP_SEL_S 20
-#define RTC_IO_ADC2_SLP_IE (BIT(19))
-#define RTC_IO_ADC2_SLP_IE_S 19
-#define RTC_IO_ADC2_FUN_IE (BIT(18))
-#define RTC_IO_ADC2_FUN_IE_S 18
-
-#define PAD_DAC1 (DR_REG_RTCIO_BASE + 0x84)
-#define RTC_IO_PDAC1_DRV 0x00000003
-#define RTC_IO_PDAC1_DRV_S 30
-#define RTC_IO_PDAC1_HOLD (BIT(29))
-#define RTC_IO_PDAC1_HOLD_S 29
-#define RTC_IO_PDAC1_RDE (BIT(28))
-#define RTC_IO_PDAC1_RDE_S 28
-#define RTC_IO_PDAC1_RUE (BIT(27))
-#define RTC_IO_PDAC1_RUE_S 27
-#define RTC_IO_PDAC1_DAC 0x000000FF
-#define RTC_IO_PDAC1_DAC_S 19
-#define RTC_IO_PDAC1_XPD_DAC (BIT(18))
-#define RTC_IO_PDAC1_XPD_DAC_S 18
-#define RTC_IO_PDAC1_MUX_SEL (BIT(17))
-#define RTC_IO_PDAC1_MUX_SEL_S 17
-#define RTC_IO_PDAC1_FUN_SEL 0x00000003
-#define RTC_IO_PDAC1_FUN_SEL_S 15
-#define RTC_IO_PDAC1_SLP_SEL (BIT(14))
-#define RTC_IO_PDAC1_SLP_SEL_S 14
-#define RTC_IO_PDAC1_SLP_IE (BIT(13))
-#define RTC_IO_PDAC1_SLP_IE_S 13
-#define RTC_IO_PDAC1_SLP_OE (BIT(12))
-#define RTC_IO_PDAC1_SLP_OE_S 12
-#define RTC_IO_PDAC1_FUN_IE (BIT(11))
-#define RTC_IO_PDAC1_FUN_IE_S 11
-#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10))
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10
-
-#define PAD_DAC2 (DR_REG_RTCIO_BASE + 0x88)
-#define RTC_IO_PDAC2_DRV 0x00000003
-#define RTC_IO_PDAC2_DRV_S 30
-#define RTC_IO_PDAC2_HOLD (BIT(29))
-#define RTC_IO_PDAC2_HOLD_S 29
-#define RTC_IO_PDAC2_RDE (BIT(28))
-#define RTC_IO_PDAC2_RDE_S 28
-#define RTC_IO_PDAC2_RUE (BIT(27))
-#define RTC_IO_PDAC2_RUE_S 27
-#define RTC_IO_PDAC2_DAC 0x000000FF
-#define RTC_IO_PDAC2_DAC_S 19
-#define RTC_IO_PDAC2_XPD_DAC (BIT(18))
-#define RTC_IO_PDAC2_XPD_DAC_S 18
-#define RTC_IO_PDAC2_MUX_SEL (BIT(17))
-#define RTC_IO_PDAC2_MUX_SEL_S 17
-#define RTC_IO_PDAC2_FUN_SEL 0x00000003
-#define RTC_IO_PDAC2_FUN_SEL_S 15
-#define RTC_IO_PDAC2_SLP_SEL (BIT(14))
-#define RTC_IO_PDAC2_SLP_SEL_S 14
-#define RTC_IO_PDAC2_SLP_IE (BIT(13))
-#define RTC_IO_PDAC2_SLP_IE_S 13
-#define RTC_IO_PDAC2_SLP_OE (BIT(12))
-#define RTC_IO_PDAC2_SLP_OE_S 12
-#define RTC_IO_PDAC2_FUN_IE (BIT(11))
-#define RTC_IO_PDAC2_FUN_IE_S 11
-#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10))
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10
-
-#define XTAL_32K_PAD (DR_REG_RTCIO_BASE + 0x8c)
-#define RTC_IO_X32N_DRV 0x00000003
-#define RTC_IO_X32N_DRV_S 30
-#define RTC_IO_X32N_HOLD (BIT(29))
-#define RTC_IO_X32N_HOLD_S 29
-#define RTC_IO_X32N_RDE (BIT(28))
-#define RTC_IO_X32N_RDE_S 28
-#define RTC_IO_X32N_RUE (BIT(27))
-#define RTC_IO_X32N_RUE_S 27
-#define RTC_IO_X32P_DRV 0x00000003
-#define RTC_IO_X32P_DRV_S 25
-#define RTC_IO_X32P_HOLD (BIT(24))
-#define RTC_IO_X32P_HOLD_S 24
-#define RTC_IO_X32P_RDE (BIT(23))
-#define RTC_IO_X32P_RDE_S 23
-#define RTC_IO_X32P_RUE (BIT(22))
-#define RTC_IO_X32P_RUE_S 22
-#define RTC_IO_DAC_XTAL_32K 0x00000003
-#define RTC_IO_DAC_XTAL_32K_S 20
-#define RTC_IO_XPD_XTAL_32K (BIT(19))
-#define RTC_IO_XPD_XTAL_32K_S 19
-#define RTC_IO_X32N_MUX_SEL (BIT(18))
-#define RTC_IO_X32N_MUX_SEL_S 18
-#define RTC_IO_X32P_MUX_SEL (BIT(17))
-#define RTC_IO_X32P_MUX_SEL_S 17
-#define RTC_IO_X32N_FUN_SEL 0x00000003
-#define RTC_IO_X32N_FUN_SEL_S 15
-#define RTC_IO_X32N_SLP_SEL (BIT(14))
-#define RTC_IO_X32N_SLP_SEL_S 14
-#define RTC_IO_X32N_SLP_IE (BIT(13))
-#define RTC_IO_X32N_SLP_IE_S 13
-#define RTC_IO_X32N_SLP_OE (BIT(12))
-#define RTC_IO_X32N_SLP_OE_S 12
-#define RTC_IO_X32N_FUN_IE (BIT(11))
-#define RTC_IO_X32N_FUN_IE_S 11
-#define RTC_IO_X32P_FUN_SEL 0x00000003
-#define RTC_IO_X32P_FUN_SEL_S 9
-#define RTC_IO_X32P_SLP_SEL (BIT(8))
-#define RTC_IO_X32P_SLP_SEL_S 8
-#define RTC_IO_X32P_SLP_IE (BIT(7))
-#define RTC_IO_X32P_SLP_IE_S 7
-#define RTC_IO_X32P_SLP_OE (BIT(6))
-#define RTC_IO_X32P_SLP_OE_S 6
-#define RTC_IO_X32P_FUN_IE (BIT(5))
-#define RTC_IO_X32P_FUN_IE_S 5
-#define RTC_IO_DRES_XTAL_32K 0x00000003
-#define RTC_IO_DRES_XTAL_32K_S 3
-#define RTC_IO_DBIAS_XTAL_32K 0x00000003
-#define RTC_IO_DBIAS_XTAL_32K_S 1
-
-#define TOUCH_CFG (DR_REG_RTCIO_BASE + 0x90)
-#define RTC_IO_TOUCH_XPD_BIAS (BIT(31))
-#define RTC_IO_TOUCH_XPD_BIAS_S 31
-#define RTC_IO_TOUCH_DREFH 0x00000003
-#define RTC_IO_TOUCH_DREFH_S 29
-#define RTC_IO_TOUCH_DREFL 0x00000003
-#define RTC_IO_TOUCH_DREFL_S 27
-#define RTC_IO_TOUCH_DRANGE 0x00000003
-#define RTC_IO_TOUCH_DRANGE_S 25
-#define RTC_IO_TOUCH_DCUR 0x00000003
-#define RTC_IO_TOUCH_DCUR_S 23
-
-#define TOUCH_PAD0 (DR_REG_RTCIO_BASE + 0x94)
-#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31))
-#define RTC_IO_TOUCH_PAD0_HOLD_S 31
-#define RTC_IO_TOUCH_PAD0_DRV 0x00000003
-#define RTC_IO_TOUCH_PAD0_DRV_S 29
-#define RTC_IO_TOUCH_PAD0_RDE (BIT(28))
-#define RTC_IO_TOUCH_PAD0_RDE_S 28
-#define RTC_IO_TOUCH_PAD0_RUE (BIT(27))
-#define RTC_IO_TOUCH_PAD0_RUE_S 27
-#define RTC_IO_TOUCH_PAD0_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD0_DAC_S 23
-#define RTC_IO_TOUCH_PAD0_START (BIT(22))
-#define RTC_IO_TOUCH_PAD0_START_S 22
-#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD0_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD0_XPD_S 20
-#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19))
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19
-#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17
-#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16))
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16
-#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15))
-#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15
-#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14))
-#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14
-#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13))
-#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13
-#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12))
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12
-
-#define TOUCH_PAD1 (DR_REG_RTCIO_BASE + 0x98)
-#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31))
-#define RTC_IO_TOUCH_PAD1_HOLD_S 31
-#define RTC_IO_TOUCH_PAD1_DRV 0x00000003
-#define RTC_IO_TOUCH_PAD1_DRV_S 29
-#define RTC_IO_TOUCH_PAD1_RDE (BIT(28))
-#define RTC_IO_TOUCH_PAD1_RDE_S 28
-#define RTC_IO_TOUCH_PAD1_RUE (BIT(27))
-#define RTC_IO_TOUCH_PAD1_RUE_S 27
-#define RTC_IO_TOUCH_PAD1_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD1_DAC_S 23
-#define RTC_IO_TOUCH_PAD1_START (BIT(22))
-#define RTC_IO_TOUCH_PAD1_START_S 22
-#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD1_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD1_XPD_S 20
-#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19))
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19
-#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17
-#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16))
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16
-#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15))
-#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15
-#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14))
-#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14
-#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13))
-#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13
-#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12))
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12
-
-#define TOUCH_PAD2 (DR_REG_RTCIO_BASE + 0x9c)
-#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31))
-#define RTC_IO_TOUCH_PAD2_HOLD_S 31
-#define RTC_IO_TOUCH_PAD2_DRV 0x00000003
-#define RTC_IO_TOUCH_PAD2_DRV_S 29
-#define RTC_IO_TOUCH_PAD2_RDE (BIT(28))
-#define RTC_IO_TOUCH_PAD2_RDE_S 28
-#define RTC_IO_TOUCH_PAD2_RUE (BIT(27))
-#define RTC_IO_TOUCH_PAD2_RUE_S 27
-#define RTC_IO_TOUCH_PAD2_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD2_DAC_S 23
-#define RTC_IO_TOUCH_PAD2_START (BIT(22))
-#define RTC_IO_TOUCH_PAD2_START_S 22
-#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD2_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD2_XPD_S 20
-#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19))
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19
-#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17
-#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16))
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16
-#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15))
-#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15
-#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14))
-#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14
-#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13))
-#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13
-#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12))
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12
-
-#define TOUCH_PAD3 (DR_REG_RTCIO_BASE + 0xa0)
-#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31))
-#define RTC_IO_TOUCH_PAD3_HOLD_S 31
-#define RTC_IO_TOUCH_PAD3_DRV 0x00000003
-#define RTC_IO_TOUCH_PAD3_DRV_S 29
-#define RTC_IO_TOUCH_PAD3_RDE (BIT(28))
-#define RTC_IO_TOUCH_PAD3_RDE_S 28
-#define RTC_IO_TOUCH_PAD3_RUE (BIT(27))
-#define RTC_IO_TOUCH_PAD3_RUE_S 27
-#define RTC_IO_TOUCH_PAD3_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD3_DAC_S 23
-#define RTC_IO_TOUCH_PAD3_START (BIT(22))
-#define RTC_IO_TOUCH_PAD3_START_S 22
-#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD3_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD3_XPD_S 20
-#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19))
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19
-#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17
-#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16))
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16
-#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15))
-#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15
-#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14))
-#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14
-#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13))
-#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13
-#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12))
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12
-
-#define TOUCH_PAD4 (DR_REG_RTCIO_BASE + 0xa4)
-#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31))
-#define RTC_IO_TOUCH_PAD4_HOLD_S 31
-#define RTC_IO_TOUCH_PAD4_DRV 0x00000003
-#define RTC_IO_TOUCH_PAD4_DRV_S 29
-#define RTC_IO_TOUCH_PAD4_RDE (BIT(28))
-#define RTC_IO_TOUCH_PAD4_RDE_S 28
-#define RTC_IO_TOUCH_PAD4_RUE (BIT(27))
-#define RTC_IO_TOUCH_PAD4_RUE_S 27
-#define RTC_IO_TOUCH_PAD4_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD4_DAC_S 23
-#define RTC_IO_TOUCH_PAD4_START (BIT(22))
-#define RTC_IO_TOUCH_PAD4_START_S 22
-#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD4_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD4_XPD_S 20
-#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19))
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19
-#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17
-#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16))
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16
-#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15))
-#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15
-#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14))
-#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14
-#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13))
-#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13
-#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12))
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12
-
-#define TOUCH_PAD5 (DR_REG_RTCIO_BASE + 0xa8)
-#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31))
-#define RTC_IO_TOUCH_PAD5_HOLD_S 31
-#define RTC_IO_TOUCH_PAD5_DRV 0x00000003
-#define RTC_IO_TOUCH_PAD5_DRV_S 29
-#define RTC_IO_TOUCH_PAD5_RDE (BIT(28))
-#define RTC_IO_TOUCH_PAD5_RDE_S 28
-#define RTC_IO_TOUCH_PAD5_RUE (BIT(27))
-#define RTC_IO_TOUCH_PAD5_RUE_S 27
-#define RTC_IO_TOUCH_PAD5_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD5_DAC_S 23
-#define RTC_IO_TOUCH_PAD5_START (BIT(22))
-#define RTC_IO_TOUCH_PAD5_START_S 22
-#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD5_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD5_XPD_S 20
-#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19))
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19
-#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17
-#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16))
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16
-#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15))
-#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15
-#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14))
-#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14
-#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13))
-#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13
-#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12))
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12
-
-#define TOUCH_PAD6 (DR_REG_RTCIO_BASE + 0xac)
-#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31))
-#define RTC_IO_TOUCH_PAD6_HOLD_S 31
-#define RTC_IO_TOUCH_PAD6_DRV 0x00000003
-#define RTC_IO_TOUCH_PAD6_DRV_S 29
-#define RTC_IO_TOUCH_PAD6_RDE (BIT(28))
-#define RTC_IO_TOUCH_PAD6_RDE_S 28
-#define RTC_IO_TOUCH_PAD6_RUE (BIT(27))
-#define RTC_IO_TOUCH_PAD6_RUE_S 27
-#define RTC_IO_TOUCH_PAD6_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD6_DAC_S 23
-#define RTC_IO_TOUCH_PAD6_START (BIT(22))
-#define RTC_IO_TOUCH_PAD6_START_S 22
-#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD6_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD6_XPD_S 20
-#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19))
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19
-#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17
-#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16))
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16
-#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15))
-#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15
-#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14))
-#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14
-#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13))
-#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13
-#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12))
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12
-
-#define TOUCH_PAD7 (DR_REG_RTCIO_BASE + 0xb0)
-#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31))
-#define RTC_IO_TOUCH_PAD7_HOLD_S 31
-#define RTC_IO_TOUCH_PAD7_DRV 0x00000003
-#define RTC_IO_TOUCH_PAD7_DRV_S 29
-#define RTC_IO_TOUCH_PAD7_RDE (BIT(28))
-#define RTC_IO_TOUCH_PAD7_RDE_S 28
-#define RTC_IO_TOUCH_PAD7_RUE (BIT(27))
-#define RTC_IO_TOUCH_PAD7_RUE_S 27
-#define RTC_IO_TOUCH_PAD7_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD7_DAC_S 23
-#define RTC_IO_TOUCH_PAD7_START (BIT(22))
-#define RTC_IO_TOUCH_PAD7_START_S 22
-#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD7_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD7_XPD_S 20
-#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19))
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19
-#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17
-#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16))
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16
-#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15))
-#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15
-#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14))
-#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14
-#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13))
-#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13
-#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12))
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12
-
-#define TOUCH_PAD8 (DR_REG_RTCIO_BASE + 0xb4)
-#define RTC_IO_TOUCH_PAD8_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD8_DAC_S 23
-#define RTC_IO_TOUCH_PAD8_START (BIT(22))
-#define RTC_IO_TOUCH_PAD8_START_S 22
-#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD8_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD8_XPD_S 20
-#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19))
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19
-
-#define TOUCH_PAD9 (DR_REG_RTCIO_BASE + 0xb8)
-#define RTC_IO_TOUCH_PAD9_DAC 0x00000007
-#define RTC_IO_TOUCH_PAD9_DAC_S 23
-#define RTC_IO_TOUCH_PAD9_START (BIT(22))
-#define RTC_IO_TOUCH_PAD9_START_S 22
-#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21))
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21
-#define RTC_IO_TOUCH_PAD9_XPD (BIT(20))
-#define RTC_IO_TOUCH_PAD9_XPD_S 20
-#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19))
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19
-
-#define EXT_WAKEUP0 (DR_REG_RTCIO_BASE + 0xbc)
-#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F
-#define RTC_IO_EXT_WAKEUP0_SEL_S 27
-
-#define XTL_EXT_CTR (DR_REG_RTCIO_BASE + 0xc0)
-#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F
-#define RTC_IO_XTL_EXT_CTR_SEL_S 27
-
-#define SAR_I2C_IO (DR_REG_RTCIO_BASE + 0xc4)
-#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003
-#define RTC_IO_SAR_I2C_SDA_SEL_S 30
-#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003
-#define RTC_IO_SAR_I2C_SCL_SEL_S 28
-#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F
-#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23
-
-#define RTC_IO_DATE (DR_REG_RTCIO_BASE + 0xc8)
-#define RTC_IO_RTC_IO_DATE 0x0FFFFFFF
-#define RTC_IO_RTC_IO_DATE_S 0
+#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c)
+/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: GPIO wake up enable only available in light sleep*/
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10))
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10
+/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge
+ trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
+#define RTC_GPIO_PIN17_INT_TYPE 0x00000007
+#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))
+#define RTC_GPIO_PIN17_INT_TYPE_V 0x7
+#define RTC_GPIO_PIN17_INT_TYPE_S 7
+/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output if set to 1: open drain*/
+#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2))
+#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2))
+#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1
+#define RTC_GPIO_PIN17_PAD_DRIVER_S 2
+
+#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x70)
+/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25))
+#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25))
+#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1
+#define RTC_IO_DEBUG_12M_NO_GATING_S 25
+/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL4 0x0000001F
+#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S))
+#define RTC_IO_DEBUG_SEL4_V 0x1F
+#define RTC_IO_DEBUG_SEL4_S 20
+/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL3 0x0000001F
+#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S))
+#define RTC_IO_DEBUG_SEL3_V 0x1F
+#define RTC_IO_DEBUG_SEL3_S 15
+/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL2 0x0000001F
+#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S))
+#define RTC_IO_DEBUG_SEL2_V 0x1F
+#define RTC_IO_DEBUG_SEL2_S 10
+/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL1 0x0000001F
+#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))
+#define RTC_IO_DEBUG_SEL1_V 0x1F
+#define RTC_IO_DEBUG_SEL1_S 5
+/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL0 0x0000001F
+#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))
+#define RTC_IO_DEBUG_SEL0_V 0x1F
+#define RTC_IO_DEBUG_SEL0_S 0
+
+#define RTC_IO_DIG_PAD_HOLD_REG (DR_REG_RTCIO_BASE + 0x74)
+/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */
+/*description: select the digital pad hold value.*/
+#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF
+#define RTC_IO_DIG_PAD_HOLD_M ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S))
+#define RTC_IO_DIG_PAD_HOLD_V 0xFFFFFFFF
+#define RTC_IO_DIG_PAD_HOLD_S 0
+
+#define RTC_IO_HALL_SENS_REG (DR_REG_RTCIO_BASE + 0x78)
+/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: Power on hall sensor and connect to VP and VN*/
+#define RTC_IO_XPD_HALL (BIT(31))
+#define RTC_IO_XPD_HALL_M (BIT(31))
+#define RTC_IO_XPD_HALL_V 0x1
+#define RTC_IO_XPD_HALL_S 31
+/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: Reverse phase of hall sensor*/
+#define RTC_IO_HALL_PHASE (BIT(30))
+#define RTC_IO_HALL_PHASE_M (BIT(30))
+#define RTC_IO_HALL_PHASE_V 0x1
+#define RTC_IO_HALL_PHASE_S 30
+
+#define RTC_IO_SENSOR_PADS_REG (DR_REG_RTCIO_BASE + 0x7c)
+/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_SENSE1_HOLD (BIT(31))
+#define RTC_IO_SENSE1_HOLD_M (BIT(31))
+#define RTC_IO_SENSE1_HOLD_V 0x1
+#define RTC_IO_SENSE1_HOLD_S 31
+/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_SENSE2_HOLD (BIT(30))
+#define RTC_IO_SENSE2_HOLD_M (BIT(30))
+#define RTC_IO_SENSE2_HOLD_V 0x1
+#define RTC_IO_SENSE2_HOLD_S 30
+/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_SENSE3_HOLD (BIT(29))
+#define RTC_IO_SENSE3_HOLD_M (BIT(29))
+#define RTC_IO_SENSE3_HOLD_V 0x1
+#define RTC_IO_SENSE3_HOLD_S 29
+/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_SENSE4_HOLD (BIT(28))
+#define RTC_IO_SENSE4_HOLD_M (BIT(28))
+#define RTC_IO_SENSE4_HOLD_V 0x1
+#define RTC_IO_SENSE4_HOLD_S 28
+/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_SENSE1_MUX_SEL (BIT(27))
+#define RTC_IO_SENSE1_MUX_SEL_M (BIT(27))
+#define RTC_IO_SENSE1_MUX_SEL_V 0x1
+#define RTC_IO_SENSE1_MUX_SEL_S 27
+/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_SENSE2_MUX_SEL (BIT(26))
+#define RTC_IO_SENSE2_MUX_SEL_M (BIT(26))
+#define RTC_IO_SENSE2_MUX_SEL_V 0x1
+#define RTC_IO_SENSE2_MUX_SEL_S 26
+/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_SENSE3_MUX_SEL (BIT(25))
+#define RTC_IO_SENSE3_MUX_SEL_M (BIT(25))
+#define RTC_IO_SENSE3_MUX_SEL_V 0x1
+#define RTC_IO_SENSE3_MUX_SEL_S 25
+/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_SENSE4_MUX_SEL (BIT(24))
+#define RTC_IO_SENSE4_MUX_SEL_M (BIT(24))
+#define RTC_IO_SENSE4_MUX_SEL_V 0x1
+#define RTC_IO_SENSE4_MUX_SEL_S 24
+/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_SENSE1_FUN_SEL 0x00000003
+#define RTC_IO_SENSE1_FUN_SEL_M ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S))
+#define RTC_IO_SENSE1_FUN_SEL_V 0x3
+#define RTC_IO_SENSE1_FUN_SEL_S 22
+/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_SENSE1_SLP_SEL (BIT(21))
+#define RTC_IO_SENSE1_SLP_SEL_M (BIT(21))
+#define RTC_IO_SENSE1_SLP_SEL_V 0x1
+#define RTC_IO_SENSE1_SLP_SEL_S 21
+/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_SENSE1_SLP_IE (BIT(20))
+#define RTC_IO_SENSE1_SLP_IE_M (BIT(20))
+#define RTC_IO_SENSE1_SLP_IE_V 0x1
+#define RTC_IO_SENSE1_SLP_IE_S 20
+/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_SENSE1_FUN_IE (BIT(19))
+#define RTC_IO_SENSE1_FUN_IE_M (BIT(19))
+#define RTC_IO_SENSE1_FUN_IE_V 0x1
+#define RTC_IO_SENSE1_FUN_IE_S 19
+/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_SENSE2_FUN_SEL 0x00000003
+#define RTC_IO_SENSE2_FUN_SEL_M ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S))
+#define RTC_IO_SENSE2_FUN_SEL_V 0x3
+#define RTC_IO_SENSE2_FUN_SEL_S 17
+/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_SENSE2_SLP_SEL (BIT(16))
+#define RTC_IO_SENSE2_SLP_SEL_M (BIT(16))
+#define RTC_IO_SENSE2_SLP_SEL_V 0x1
+#define RTC_IO_SENSE2_SLP_SEL_S 16
+/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_SENSE2_SLP_IE (BIT(15))
+#define RTC_IO_SENSE2_SLP_IE_M (BIT(15))
+#define RTC_IO_SENSE2_SLP_IE_V 0x1
+#define RTC_IO_SENSE2_SLP_IE_S 15
+/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_SENSE2_FUN_IE (BIT(14))
+#define RTC_IO_SENSE2_FUN_IE_M (BIT(14))
+#define RTC_IO_SENSE2_FUN_IE_V 0x1
+#define RTC_IO_SENSE2_FUN_IE_S 14
+/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_SENSE3_FUN_SEL 0x00000003
+#define RTC_IO_SENSE3_FUN_SEL_M ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S))
+#define RTC_IO_SENSE3_FUN_SEL_V 0x3
+#define RTC_IO_SENSE3_FUN_SEL_S 12
+/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_SENSE3_SLP_SEL (BIT(11))
+#define RTC_IO_SENSE3_SLP_SEL_M (BIT(11))
+#define RTC_IO_SENSE3_SLP_SEL_V 0x1
+#define RTC_IO_SENSE3_SLP_SEL_S 11
+/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_SENSE3_SLP_IE (BIT(10))
+#define RTC_IO_SENSE3_SLP_IE_M (BIT(10))
+#define RTC_IO_SENSE3_SLP_IE_V 0x1
+#define RTC_IO_SENSE3_SLP_IE_S 10
+/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_SENSE3_FUN_IE (BIT(9))
+#define RTC_IO_SENSE3_FUN_IE_M (BIT(9))
+#define RTC_IO_SENSE3_FUN_IE_V 0x1
+#define RTC_IO_SENSE3_FUN_IE_S 9
+/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_SENSE4_FUN_SEL 0x00000003
+#define RTC_IO_SENSE4_FUN_SEL_M ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S))
+#define RTC_IO_SENSE4_FUN_SEL_V 0x3
+#define RTC_IO_SENSE4_FUN_SEL_S 7
+/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_SENSE4_SLP_SEL (BIT(6))
+#define RTC_IO_SENSE4_SLP_SEL_M (BIT(6))
+#define RTC_IO_SENSE4_SLP_SEL_V 0x1
+#define RTC_IO_SENSE4_SLP_SEL_S 6
+/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_SENSE4_SLP_IE (BIT(5))
+#define RTC_IO_SENSE4_SLP_IE_M (BIT(5))
+#define RTC_IO_SENSE4_SLP_IE_V 0x1
+#define RTC_IO_SENSE4_SLP_IE_S 5
+/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_SENSE4_FUN_IE (BIT(4))
+#define RTC_IO_SENSE4_FUN_IE_M (BIT(4))
+#define RTC_IO_SENSE4_FUN_IE_V 0x1
+#define RTC_IO_SENSE4_FUN_IE_S 4
+
+#define RTC_IO_ADC_PAD_REG (DR_REG_RTCIO_BASE + 0x80)
+/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_ADC1_HOLD (BIT(31))
+#define RTC_IO_ADC1_HOLD_M (BIT(31))
+#define RTC_IO_ADC1_HOLD_V 0x1
+#define RTC_IO_ADC1_HOLD_S 31
+/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_ADC2_HOLD (BIT(30))
+#define RTC_IO_ADC2_HOLD_M (BIT(30))
+#define RTC_IO_ADC2_HOLD_V 0x1
+#define RTC_IO_ADC2_HOLD_S 30
+/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_ADC1_MUX_SEL (BIT(29))
+#define RTC_IO_ADC1_MUX_SEL_M (BIT(29))
+#define RTC_IO_ADC1_MUX_SEL_V 0x1
+#define RTC_IO_ADC1_MUX_SEL_S 29
+/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_ADC2_MUX_SEL (BIT(28))
+#define RTC_IO_ADC2_MUX_SEL_M (BIT(28))
+#define RTC_IO_ADC2_MUX_SEL_V 0x1
+#define RTC_IO_ADC2_MUX_SEL_S 28
+/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_ADC1_FUN_SEL 0x00000003
+#define RTC_IO_ADC1_FUN_SEL_M ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S))
+#define RTC_IO_ADC1_FUN_SEL_V 0x3
+#define RTC_IO_ADC1_FUN_SEL_S 26
+/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_ADC1_SLP_SEL (BIT(25))
+#define RTC_IO_ADC1_SLP_SEL_M (BIT(25))
+#define RTC_IO_ADC1_SLP_SEL_V 0x1
+#define RTC_IO_ADC1_SLP_SEL_S 25
+/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_ADC1_SLP_IE (BIT(24))
+#define RTC_IO_ADC1_SLP_IE_M (BIT(24))
+#define RTC_IO_ADC1_SLP_IE_V 0x1
+#define RTC_IO_ADC1_SLP_IE_S 24
+/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_ADC1_FUN_IE (BIT(23))
+#define RTC_IO_ADC1_FUN_IE_M (BIT(23))
+#define RTC_IO_ADC1_FUN_IE_V 0x1
+#define RTC_IO_ADC1_FUN_IE_S 23
+/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_ADC2_FUN_SEL 0x00000003
+#define RTC_IO_ADC2_FUN_SEL_M ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S))
+#define RTC_IO_ADC2_FUN_SEL_V 0x3
+#define RTC_IO_ADC2_FUN_SEL_S 21
+/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_ADC2_SLP_SEL (BIT(20))
+#define RTC_IO_ADC2_SLP_SEL_M (BIT(20))
+#define RTC_IO_ADC2_SLP_SEL_V 0x1
+#define RTC_IO_ADC2_SLP_SEL_S 20
+/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_ADC2_SLP_IE (BIT(19))
+#define RTC_IO_ADC2_SLP_IE_M (BIT(19))
+#define RTC_IO_ADC2_SLP_IE_V 0x1
+#define RTC_IO_ADC2_SLP_IE_S 19
+/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_ADC2_FUN_IE (BIT(18))
+#define RTC_IO_ADC2_FUN_IE_M (BIT(18))
+#define RTC_IO_ADC2_FUN_IE_V 0x1
+#define RTC_IO_ADC2_FUN_IE_S 18
+
+#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x84)
+/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_PDAC1_DRV 0x00000003
+#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))
+#define RTC_IO_PDAC1_DRV_V 0x3
+#define RTC_IO_PDAC1_DRV_S 30
+/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_PDAC1_HOLD (BIT(29))
+#define RTC_IO_PDAC1_HOLD_M (BIT(29))
+#define RTC_IO_PDAC1_HOLD_V 0x1
+#define RTC_IO_PDAC1_HOLD_S 29
+/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_PDAC1_RDE (BIT(28))
+#define RTC_IO_PDAC1_RDE_M (BIT(28))
+#define RTC_IO_PDAC1_RDE_V 0x1
+#define RTC_IO_PDAC1_RDE_S 28
+/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_PDAC1_RUE (BIT(27))
+#define RTC_IO_PDAC1_RUE_M (BIT(27))
+#define RTC_IO_PDAC1_RUE_V 0x1
+#define RTC_IO_PDAC1_RUE_S 27
+/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: PAD DAC1 control code.*/
+#define RTC_IO_PDAC1_DAC 0x000000FF
+#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))
+#define RTC_IO_PDAC1_DAC_V 0xFF
+#define RTC_IO_PDAC1_DAC_S 19
+/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power
+ on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
+#define RTC_IO_PDAC1_XPD_DAC (BIT(18))
+#define RTC_IO_PDAC1_XPD_DAC_M (BIT(18))
+#define RTC_IO_PDAC1_XPD_DAC_V 0x1
+#define RTC_IO_PDAC1_XPD_DAC_S 18
+/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_PDAC1_MUX_SEL (BIT(17))
+#define RTC_IO_PDAC1_MUX_SEL_M (BIT(17))
+#define RTC_IO_PDAC1_MUX_SEL_V 0x1
+#define RTC_IO_PDAC1_MUX_SEL_S 17
+/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_PDAC1_FUN_SEL 0x00000003
+#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))
+#define RTC_IO_PDAC1_FUN_SEL_V 0x3
+#define RTC_IO_PDAC1_FUN_SEL_S 15
+/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_PDAC1_SLP_SEL (BIT(14))
+#define RTC_IO_PDAC1_SLP_SEL_M (BIT(14))
+#define RTC_IO_PDAC1_SLP_SEL_V 0x1
+#define RTC_IO_PDAC1_SLP_SEL_S 14
+/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_PDAC1_SLP_IE (BIT(13))
+#define RTC_IO_PDAC1_SLP_IE_M (BIT(13))
+#define RTC_IO_PDAC1_SLP_IE_V 0x1
+#define RTC_IO_PDAC1_SLP_IE_S 13
+/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_PDAC1_SLP_OE (BIT(12))
+#define RTC_IO_PDAC1_SLP_OE_M (BIT(12))
+#define RTC_IO_PDAC1_SLP_OE_V 0x1
+#define RTC_IO_PDAC1_SLP_OE_S 12
+/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_PDAC1_FUN_IE (BIT(11))
+#define RTC_IO_PDAC1_FUN_IE_M (BIT(11))
+#define RTC_IO_PDAC1_FUN_IE_V 0x1
+#define RTC_IO_PDAC1_FUN_IE_S 11
+/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Power on DAC1. Usually we need to tristate PDAC1 if we power
+ on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
+#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10))
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(10))
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10
+
+#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x88)
+/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_PDAC2_DRV 0x00000003
+#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))
+#define RTC_IO_PDAC2_DRV_V 0x3
+#define RTC_IO_PDAC2_DRV_S 30
+/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_PDAC2_HOLD (BIT(29))
+#define RTC_IO_PDAC2_HOLD_M (BIT(29))
+#define RTC_IO_PDAC2_HOLD_V 0x1
+#define RTC_IO_PDAC2_HOLD_S 29
+/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_PDAC2_RDE (BIT(28))
+#define RTC_IO_PDAC2_RDE_M (BIT(28))
+#define RTC_IO_PDAC2_RDE_V 0x1
+#define RTC_IO_PDAC2_RDE_S 28
+/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_PDAC2_RUE (BIT(27))
+#define RTC_IO_PDAC2_RUE_M (BIT(27))
+#define RTC_IO_PDAC2_RUE_V 0x1
+#define RTC_IO_PDAC2_RUE_S 27
+/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: PAD DAC2 control code.*/
+#define RTC_IO_PDAC2_DAC 0x000000FF
+#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))
+#define RTC_IO_PDAC2_DAC_V 0xFF
+#define RTC_IO_PDAC2_DAC_S 19
+/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Power on DAC2. Usually we need to tristate PDAC1 if we power
+ on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
+#define RTC_IO_PDAC2_XPD_DAC (BIT(18))
+#define RTC_IO_PDAC2_XPD_DAC_M (BIT(18))
+#define RTC_IO_PDAC2_XPD_DAC_V 0x1
+#define RTC_IO_PDAC2_XPD_DAC_S 18
+/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_PDAC2_MUX_SEL (BIT(17))
+#define RTC_IO_PDAC2_MUX_SEL_M (BIT(17))
+#define RTC_IO_PDAC2_MUX_SEL_V 0x1
+#define RTC_IO_PDAC2_MUX_SEL_S 17
+/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_PDAC2_FUN_SEL 0x00000003
+#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))
+#define RTC_IO_PDAC2_FUN_SEL_V 0x3
+#define RTC_IO_PDAC2_FUN_SEL_S 15
+/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_PDAC2_SLP_SEL (BIT(14))
+#define RTC_IO_PDAC2_SLP_SEL_M (BIT(14))
+#define RTC_IO_PDAC2_SLP_SEL_V 0x1
+#define RTC_IO_PDAC2_SLP_SEL_S 14
+/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_PDAC2_SLP_IE (BIT(13))
+#define RTC_IO_PDAC2_SLP_IE_M (BIT(13))
+#define RTC_IO_PDAC2_SLP_IE_V 0x1
+#define RTC_IO_PDAC2_SLP_IE_S 13
+/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_PDAC2_SLP_OE (BIT(12))
+#define RTC_IO_PDAC2_SLP_OE_M (BIT(12))
+#define RTC_IO_PDAC2_SLP_OE_V 0x1
+#define RTC_IO_PDAC2_SLP_OE_S 12
+/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_PDAC2_FUN_IE (BIT(11))
+#define RTC_IO_PDAC2_FUN_IE_M (BIT(11))
+#define RTC_IO_PDAC2_FUN_IE_V 0x1
+#define RTC_IO_PDAC2_FUN_IE_S 11
+/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Power on DAC2. Usually we need to tristate PDAC2 if we power
+ on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0*/
+#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10))
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(10))
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10
+
+#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c)
+/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_X32N_DRV 0x00000003
+#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S))
+#define RTC_IO_X32N_DRV_V 0x3
+#define RTC_IO_X32N_DRV_S 30
+/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_X32N_HOLD (BIT(29))
+#define RTC_IO_X32N_HOLD_M (BIT(29))
+#define RTC_IO_X32N_HOLD_V 0x1
+#define RTC_IO_X32N_HOLD_S 29
+/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_X32N_RDE (BIT(28))
+#define RTC_IO_X32N_RDE_M (BIT(28))
+#define RTC_IO_X32N_RDE_V 0x1
+#define RTC_IO_X32N_RDE_S 28
+/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_X32N_RUE (BIT(27))
+#define RTC_IO_X32N_RUE_M (BIT(27))
+#define RTC_IO_X32N_RUE_V 0x1
+#define RTC_IO_X32N_RUE_S 27
+/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_X32P_DRV 0x00000003
+#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S))
+#define RTC_IO_X32P_DRV_V 0x3
+#define RTC_IO_X32P_DRV_S 25
+/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_X32P_HOLD (BIT(24))
+#define RTC_IO_X32P_HOLD_M (BIT(24))
+#define RTC_IO_X32P_HOLD_V 0x1
+#define RTC_IO_X32P_HOLD_S 24
+/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_X32P_RDE (BIT(23))
+#define RTC_IO_X32P_RDE_M (BIT(23))
+#define RTC_IO_X32P_RDE_V 0x1
+#define RTC_IO_X32P_RDE_S 23
+/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_X32P_RUE (BIT(22))
+#define RTC_IO_X32P_RUE_M (BIT(22))
+#define RTC_IO_X32P_RUE_V 0x1
+#define RTC_IO_X32P_RUE_S 22
+/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */
+/*description: 32K XTAL bias current DAC.*/
+#define RTC_IO_DAC_XTAL_32K 0x00000003
+#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))
+#define RTC_IO_DAC_XTAL_32K_V 0x3
+#define RTC_IO_DAC_XTAL_32K_S 20
+/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Power up 32kHz crystal oscillator*/
+#define RTC_IO_XPD_XTAL_32K (BIT(19))
+#define RTC_IO_XPD_XTAL_32K_M (BIT(19))
+#define RTC_IO_XPD_XTAL_32K_V 0x1
+#define RTC_IO_XPD_XTAL_32K_S 19
+/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_X32N_MUX_SEL (BIT(18))
+#define RTC_IO_X32N_MUX_SEL_M (BIT(18))
+#define RTC_IO_X32N_MUX_SEL_V 0x1
+#define RTC_IO_X32N_MUX_SEL_S 18
+/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_X32P_MUX_SEL (BIT(17))
+#define RTC_IO_X32P_MUX_SEL_M (BIT(17))
+#define RTC_IO_X32P_MUX_SEL_V 0x1
+#define RTC_IO_X32P_MUX_SEL_S 17
+/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_X32N_FUN_SEL 0x00000003
+#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S))
+#define RTC_IO_X32N_FUN_SEL_V 0x3
+#define RTC_IO_X32N_FUN_SEL_S 15
+/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_X32N_SLP_SEL (BIT(14))
+#define RTC_IO_X32N_SLP_SEL_M (BIT(14))
+#define RTC_IO_X32N_SLP_SEL_V 0x1
+#define RTC_IO_X32N_SLP_SEL_S 14
+/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_X32N_SLP_IE (BIT(13))
+#define RTC_IO_X32N_SLP_IE_M (BIT(13))
+#define RTC_IO_X32N_SLP_IE_V 0x1
+#define RTC_IO_X32N_SLP_IE_S 13
+/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_X32N_SLP_OE (BIT(12))
+#define RTC_IO_X32N_SLP_OE_M (BIT(12))
+#define RTC_IO_X32N_SLP_OE_V 0x1
+#define RTC_IO_X32N_SLP_OE_S 12
+/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_X32N_FUN_IE (BIT(11))
+#define RTC_IO_X32N_FUN_IE_M (BIT(11))
+#define RTC_IO_X32N_FUN_IE_V 0x1
+#define RTC_IO_X32N_FUN_IE_S 11
+/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_X32P_FUN_SEL 0x00000003
+#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S))
+#define RTC_IO_X32P_FUN_SEL_V 0x3
+#define RTC_IO_X32P_FUN_SEL_S 9
+/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_X32P_SLP_SEL (BIT(8))
+#define RTC_IO_X32P_SLP_SEL_M (BIT(8))
+#define RTC_IO_X32P_SLP_SEL_V 0x1
+#define RTC_IO_X32P_SLP_SEL_S 8
+/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_X32P_SLP_IE (BIT(7))
+#define RTC_IO_X32P_SLP_IE_M (BIT(7))
+#define RTC_IO_X32P_SLP_IE_V 0x1
+#define RTC_IO_X32P_SLP_IE_S 7
+/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_X32P_SLP_OE (BIT(6))
+#define RTC_IO_X32P_SLP_OE_M (BIT(6))
+#define RTC_IO_X32P_SLP_OE_V 0x1
+#define RTC_IO_X32P_SLP_OE_S 6
+/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_X32P_FUN_IE (BIT(5))
+#define RTC_IO_X32P_FUN_IE_M (BIT(5))
+#define RTC_IO_X32P_FUN_IE_V 0x1
+#define RTC_IO_X32P_FUN_IE_S 5
+/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */
+/*description: 32K XTAL resistor bias control.*/
+#define RTC_IO_DRES_XTAL_32K 0x00000003
+#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))
+#define RTC_IO_DRES_XTAL_32K_V 0x3
+#define RTC_IO_DRES_XTAL_32K_S 3
+/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */
+/*description: 32K XTAL self-bias reference control.*/
+#define RTC_IO_DBIAS_XTAL_32K 0x00000003
+#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S))
+#define RTC_IO_DBIAS_XTAL_32K_V 0x3
+#define RTC_IO_DBIAS_XTAL_32K_S 1
+
+#define RTC_IO_TOUCH_CFG_REG (DR_REG_RTCIO_BASE + 0x90)
+/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: touch sensor bias power on.*/
+#define RTC_IO_TOUCH_XPD_BIAS (BIT(31))
+#define RTC_IO_TOUCH_XPD_BIAS_M (BIT(31))
+#define RTC_IO_TOUCH_XPD_BIAS_V 0x1
+#define RTC_IO_TOUCH_XPD_BIAS_S 31
+/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */
+/*description: touch sensor saw wave top voltage.*/
+#define RTC_IO_TOUCH_DREFH 0x00000003
+#define RTC_IO_TOUCH_DREFH_M ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S))
+#define RTC_IO_TOUCH_DREFH_V 0x3
+#define RTC_IO_TOUCH_DREFH_S 29
+/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
+/*description: touch sensor saw wave bottom voltage.*/
+#define RTC_IO_TOUCH_DREFL 0x00000003
+#define RTC_IO_TOUCH_DREFL_M ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S))
+#define RTC_IO_TOUCH_DREFL_V 0x3
+#define RTC_IO_TOUCH_DREFL_S 27
+/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */
+/*description: touch sensor saw wave voltage range.*/
+#define RTC_IO_TOUCH_DRANGE 0x00000003
+#define RTC_IO_TOUCH_DRANGE_M ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S))
+#define RTC_IO_TOUCH_DRANGE_V 0x3
+#define RTC_IO_TOUCH_DRANGE_S 25
+/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */
+/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When
+ BIAS_SLEEP this setting is available*/
+#define RTC_IO_TOUCH_DCUR 0x00000003
+#define RTC_IO_TOUCH_DCUR_M ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S))
+#define RTC_IO_TOUCH_DCUR_V 0x3
+#define RTC_IO_TOUCH_DCUR_S 23
+
+#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x94)
+/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD0_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD0_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD0_HOLD_S 31
+/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD0_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S))
+#define RTC_IO_TOUCH_PAD0_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD0_DRV_S 29
+/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD0_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD0_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD0_RDE_S 28
+/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD0_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD0_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD0_RUE_S 27
+/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD0_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))
+#define RTC_IO_TOUCH_PAD0_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD0_DAC_S 23
+/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD0_START (BIT(22))
+#define RTC_IO_TOUCH_PAD0_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD0_START_V 0x1
+#define RTC_IO_TOUCH_PAD0_START_S 22
+/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD0_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD0_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD0_XPD_S 20
+/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/
+#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x98)
+/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD1_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD1_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD1_HOLD_S 31
+/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD1_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S))
+#define RTC_IO_TOUCH_PAD1_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD1_DRV_S 29
+/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD1_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD1_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD1_RDE_S 28
+/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD1_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD1_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD1_RUE_S 27
+/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD1_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))
+#define RTC_IO_TOUCH_PAD1_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD1_DAC_S 23
+/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD1_START (BIT(22))
+#define RTC_IO_TOUCH_PAD1_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD1_START_V 0x1
+#define RTC_IO_TOUCH_PAD1_START_S 22
+/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD1_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD1_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD1_XPD_S 20
+/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/
+#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x9c)
+/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD2_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD2_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD2_HOLD_S 31
+/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD2_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S))
+#define RTC_IO_TOUCH_PAD2_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD2_DRV_S 29
+/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD2_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD2_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD2_RDE_S 28
+/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD2_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD2_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD2_RUE_S 27
+/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD2_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))
+#define RTC_IO_TOUCH_PAD2_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD2_DAC_S 23
+/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD2_START (BIT(22))
+#define RTC_IO_TOUCH_PAD2_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD2_START_V 0x1
+#define RTC_IO_TOUCH_PAD2_START_S 22
+/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD2_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD2_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD2_XPD_S 20
+/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/
+#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0xa0)
+/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD3_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD3_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD3_HOLD_S 31
+/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD3_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S))
+#define RTC_IO_TOUCH_PAD3_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD3_DRV_S 29
+/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD3_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD3_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD3_RDE_S 28
+/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD3_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD3_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD3_RUE_S 27
+/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD3_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))
+#define RTC_IO_TOUCH_PAD3_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD3_DAC_S 23
+/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD3_START (BIT(22))
+#define RTC_IO_TOUCH_PAD3_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD3_START_V 0x1
+#define RTC_IO_TOUCH_PAD3_START_S 22
+/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD3_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD3_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD3_XPD_S 20
+/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/
+#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0xa4)
+/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD4_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD4_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD4_HOLD_S 31
+/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD4_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S))
+#define RTC_IO_TOUCH_PAD4_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD4_DRV_S 29
+/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD4_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD4_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD4_RDE_S 28
+/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD4_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD4_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD4_RUE_S 27
+/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD4_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))
+#define RTC_IO_TOUCH_PAD4_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD4_DAC_S 23
+/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD4_START (BIT(22))
+#define RTC_IO_TOUCH_PAD4_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD4_START_V 0x1
+#define RTC_IO_TOUCH_PAD4_START_S 22
+/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD4_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD4_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD4_XPD_S 20
+/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/
+#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0xa8)
+/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD5_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD5_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD5_HOLD_S 31
+/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD5_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S))
+#define RTC_IO_TOUCH_PAD5_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD5_DRV_S 29
+/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD5_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD5_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD5_RDE_S 28
+/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD5_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD5_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD5_RUE_S 27
+/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD5_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))
+#define RTC_IO_TOUCH_PAD5_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD5_DAC_S 23
+/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD5_START (BIT(22))
+#define RTC_IO_TOUCH_PAD5_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD5_START_V 0x1
+#define RTC_IO_TOUCH_PAD5_START_S 22
+/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD5_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD5_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD5_XPD_S 20
+/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/
+#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0xac)
+/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD6_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD6_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD6_HOLD_S 31
+/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD6_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S))
+#define RTC_IO_TOUCH_PAD6_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD6_DRV_S 29
+/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD6_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD6_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD6_RDE_S 28
+/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD6_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD6_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD6_RUE_S 27
+/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD6_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))
+#define RTC_IO_TOUCH_PAD6_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD6_DAC_S 23
+/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD6_START (BIT(22))
+#define RTC_IO_TOUCH_PAD6_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD6_START_V 0x1
+#define RTC_IO_TOUCH_PAD6_START_S 22
+/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD6_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD6_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD6_XPD_S 20
+/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/
+#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xb0)
+/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/
+#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD7_HOLD_M (BIT(31))
+#define RTC_IO_TOUCH_PAD7_HOLD_V 0x1
+#define RTC_IO_TOUCH_PAD7_HOLD_S 31
+/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: the driver strength of the pad*/
+#define RTC_IO_TOUCH_PAD7_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S))
+#define RTC_IO_TOUCH_PAD7_DRV_V 0x3
+#define RTC_IO_TOUCH_PAD7_DRV_S 29
+/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: the pull down enable of the pad*/
+#define RTC_IO_TOUCH_PAD7_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28))
+#define RTC_IO_TOUCH_PAD7_RDE_V 0x1
+#define RTC_IO_TOUCH_PAD7_RDE_S 28
+/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: the pull up enable of the pad*/
+#define RTC_IO_TOUCH_PAD7_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27))
+#define RTC_IO_TOUCH_PAD7_RUE_V 0x1
+#define RTC_IO_TOUCH_PAD7_RUE_S 27
+/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD7_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))
+#define RTC_IO_TOUCH_PAD7_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD7_DAC_S 23
+/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD7_START (BIT(22))
+#define RTC_IO_TOUCH_PAD7_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD7_START_V 0x1
+#define RTC_IO_TOUCH_PAD7_START_S 22
+/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD7_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD7_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD7_XPD_S 20
+/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Ò1Ó select the digital function Ó0Óslection the rtc function*/
+#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19))
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19
+/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: the functional selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17
+/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: the sleep status selection signal of the pad*/
+#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16))
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16
+/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: the input enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15))
+#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1
+#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15
+/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: the output enable of the pad in sleep status*/
+#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14))
+#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1
+#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14
+/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: the input enable of the pad*/
+#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13))
+#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1
+#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13
+/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/
+#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_M (BIT(12))
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12
+
+#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xb4)
+/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD8_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S))
+#define RTC_IO_TOUCH_PAD8_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD8_DAC_S 23
+/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD8_START (BIT(22))
+#define RTC_IO_TOUCH_PAD8_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD8_START_V 0x1
+#define RTC_IO_TOUCH_PAD8_START_S 22
+/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD8_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD8_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD8_XPD_S 20
+/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
+#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19))
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_M (BIT(19))
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19
+
+#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xb8)
+/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: touch sensor slope control. 3-bit for each touch panel default 100.*/
+#define RTC_IO_TOUCH_PAD9_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S))
+#define RTC_IO_TOUCH_PAD9_DAC_V 0x7
+#define RTC_IO_TOUCH_PAD9_DAC_S 23
+/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: start touch sensor.*/
+#define RTC_IO_TOUCH_PAD9_START (BIT(22))
+#define RTC_IO_TOUCH_PAD9_START_M (BIT(22))
+#define RTC_IO_TOUCH_PAD9_START_V 0x1
+#define RTC_IO_TOUCH_PAD9_START_S 22
+/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: default touch sensor tie option. 0: tie low 1: tie high.*/
+#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21))
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21
+/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: touch sensor power on.*/
+#define RTC_IO_TOUCH_PAD9_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20))
+#define RTC_IO_TOUCH_PAD9_XPD_V 0x1
+#define RTC_IO_TOUCH_PAD9_XPD_S 20
+/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
+#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19))
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_M (BIT(19))
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_V 0x1
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19
+
+#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc)
+/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/
+#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F
+#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
+#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F
+#define RTC_IO_EXT_WAKEUP0_SEL_S 27
+
+#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xc0)
+/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select
+ GPIO2 ...Ò17Ó select GPIO17*/
+#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F
+#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))
+#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F
+#define RTC_IO_XTL_EXT_CTR_SEL_S 27
+
+#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xc4)
+/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/
+#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003
+#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S))
+#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3
+#define RTC_IO_SAR_I2C_SDA_SEL_S 30
+/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/
+#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003
+#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))
+#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3
+#define RTC_IO_SAR_I2C_SCL_SEL_S 28
+/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */
+/*description: */
+#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F
+#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S))
+#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F
+#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23
+
+#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0xc8)
+/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */
+/*description: date*/
+#define RTC_IO_IO_DATE 0x0FFFFFFF
+#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))
+#define RTC_IO_IO_DATE_V 0xFFFFFFF
+#define RTC_IO_IO_DATE_S 0
#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160
-#endif /* _SOC_RTC_IO_REG_H_ */
+
+
+
+#endif /*_SOC_RTC_IO_REG_H_ */
+
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef _SOC_SARADC_REG_H_\r
+#define _SOC_SARADC_REG_H_\r
+\r
+\r
+#include "soc.h"\r
+#define SARADC_SAR_READ_CTRL_REG (DR_REG_SARADC_BASE + 0x0000)\r
+/* SARADC_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: Invert SAR ADC1 data*/\r
+#define SARADC_SAR1_DATA_INV (BIT(28))\r
+#define SARADC_SAR1_DATA_INV_M (BIT(28))\r
+#define SARADC_SAR1_DATA_INV_V 0x1\r
+#define SARADC_SAR1_DATA_INV_S 28\r
+/* SARADC_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL*/\r
+#define SARADC_SAR1_DIG_FORCE (BIT(27))\r
+#define SARADC_SAR1_DIG_FORCE_M (BIT(27))\r
+#define SARADC_SAR1_DIG_FORCE_V 0x1\r
+#define SARADC_SAR1_DIG_FORCE_S 27\r
+/* SARADC_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */\r
+/*description: */\r
+#define SARADC_SAR1_SAMPLE_NUM 0x000000FF\r
+#define SARADC_SAR1_SAMPLE_NUM_M ((SARADC_SAR1_SAMPLE_NUM_V)<<(SARADC_SAR1_SAMPLE_NUM_S))\r
+#define SARADC_SAR1_SAMPLE_NUM_V 0xFF\r
+#define SARADC_SAR1_SAMPLE_NUM_S 19\r
+/* SARADC_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */\r
+/*description: */\r
+#define SARADC_SAR1_CLK_GATED (BIT(18))\r
+#define SARADC_SAR1_CLK_GATED_M (BIT(18))\r
+#define SARADC_SAR1_CLK_GATED_V 0x1\r
+#define SARADC_SAR1_CLK_GATED_S 18\r
+/* SARADC_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */\r
+/*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width\r
+ 11: for 12-bit width*/\r
+#define SARADC_SAR1_SAMPLE_BIT 0x00000003\r
+#define SARADC_SAR1_SAMPLE_BIT_M ((SARADC_SAR1_SAMPLE_BIT_V)<<(SARADC_SAR1_SAMPLE_BIT_S))\r
+#define SARADC_SAR1_SAMPLE_BIT_V 0x3\r
+#define SARADC_SAR1_SAMPLE_BIT_S 16\r
+/* SARADC_SAR1_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */\r
+/*description: sample cycles for SAR ADC1*/\r
+#define SARADC_SAR1_SAMPLE_CYCLE 0x000000FF\r
+#define SARADC_SAR1_SAMPLE_CYCLE_M ((SARADC_SAR1_SAMPLE_CYCLE_V)<<(SARADC_SAR1_SAMPLE_CYCLE_S))\r
+#define SARADC_SAR1_SAMPLE_CYCLE_V 0xFF\r
+#define SARADC_SAR1_SAMPLE_CYCLE_S 8\r
+/* SARADC_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */\r
+/*description: clock divider*/\r
+#define SARADC_SAR1_CLK_DIV 0x000000FF\r
+#define SARADC_SAR1_CLK_DIV_M ((SARADC_SAR1_CLK_DIV_V)<<(SARADC_SAR1_CLK_DIV_S))\r
+#define SARADC_SAR1_CLK_DIV_V 0xFF\r
+#define SARADC_SAR1_CLK_DIV_S 0\r
+\r
+#define SARADC_SAR_READ_STATUS1_REG (DR_REG_SARADC_BASE + 0x0004)\r
+/* SARADC_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define SARADC_SAR1_READER_STATUS 0xFFFFFFFF\r
+#define SARADC_SAR1_READER_STATUS_M ((SARADC_SAR1_READER_STATUS_V)<<(SARADC_SAR1_READER_STATUS_S))\r
+#define SARADC_SAR1_READER_STATUS_V 0xFFFFFFFF\r
+#define SARADC_SAR1_READER_STATUS_S 0\r
+\r
+#define SARADC_SAR_MEAS_WAIT1_REG (DR_REG_SARADC_BASE + 0x0008)\r
+/* SARADC_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */\r
+/*description: */\r
+#define SARADC_SAR_AMP_WAIT2 0x0000FFFF\r
+#define SARADC_SAR_AMP_WAIT2_M ((SARADC_SAR_AMP_WAIT2_V)<<(SARADC_SAR_AMP_WAIT2_S))\r
+#define SARADC_SAR_AMP_WAIT2_V 0xFFFF\r
+#define SARADC_SAR_AMP_WAIT2_S 16\r
+/* SARADC_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */\r
+/*description: */\r
+#define SARADC_SAR_AMP_WAIT1 0x0000FFFF\r
+#define SARADC_SAR_AMP_WAIT1_M ((SARADC_SAR_AMP_WAIT1_V)<<(SARADC_SAR_AMP_WAIT1_S))\r
+#define SARADC_SAR_AMP_WAIT1_V 0xFFFF\r
+#define SARADC_SAR_AMP_WAIT1_S 0\r
+\r
+#define SARADC_SAR_MEAS_WAIT2_REG (DR_REG_SARADC_BASE + 0x000c)\r
+/* SARADC_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */\r
+/*description: */\r
+#define SARADC_SAR2_RSTB_WAIT 0x000000FF\r
+#define SARADC_SAR2_RSTB_WAIT_M ((SARADC_SAR2_RSTB_WAIT_V)<<(SARADC_SAR2_RSTB_WAIT_S))\r
+#define SARADC_SAR2_RSTB_WAIT_V 0xFF\r
+#define SARADC_SAR2_RSTB_WAIT_S 20\r
+/* SARADC_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
+/*description: */\r
+#define SARADC_FORCE_XPD_SAR 0x00000003\r
+#define SARADC_FORCE_XPD_SAR_M ((SARADC_FORCE_XPD_SAR_V)<<(SARADC_FORCE_XPD_SAR_S))\r
+#define SARADC_FORCE_XPD_SAR_V 0x3\r
+#define SARADC_FORCE_XPD_SAR_S 18\r
+/* SARADC_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
+/*description: */\r
+#define SARADC_FORCE_XPD_AMP 0x00000003\r
+#define SARADC_FORCE_XPD_AMP_M ((SARADC_FORCE_XPD_AMP_V)<<(SARADC_FORCE_XPD_AMP_S))\r
+#define SARADC_FORCE_XPD_AMP_V 0x3\r
+#define SARADC_FORCE_XPD_AMP_S 16\r
+/* SARADC_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */\r
+/*description: */\r
+#define SARADC_SAR_AMP_WAIT3 0x0000FFFF\r
+#define SARADC_SAR_AMP_WAIT3_M ((SARADC_SAR_AMP_WAIT3_V)<<(SARADC_SAR_AMP_WAIT3_S))\r
+#define SARADC_SAR_AMP_WAIT3_V 0xFFFF\r
+#define SARADC_SAR_AMP_WAIT3_S 0\r
+\r
+#define SARADC_SAR_MEAS_CTRL_REG (DR_REG_SARADC_BASE + 0x0010)\r
+/* SARADC_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */\r
+/*description: */\r
+#define SARADC_SAR2_XPD_WAIT 0x000000FF\r
+#define SARADC_SAR2_XPD_WAIT_M ((SARADC_SAR2_XPD_WAIT_V)<<(SARADC_SAR2_XPD_WAIT_S))\r
+#define SARADC_SAR2_XPD_WAIT_V 0xFF\r
+#define SARADC_SAR2_XPD_WAIT_S 24\r
+/* SARADC_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */\r
+/*description: */\r
+#define SARADC_SAR_RSTB_FSM 0x0000000F\r
+#define SARADC_SAR_RSTB_FSM_M ((SARADC_SAR_RSTB_FSM_V)<<(SARADC_SAR_RSTB_FSM_S))\r
+#define SARADC_SAR_RSTB_FSM_V 0xF\r
+#define SARADC_SAR_RSTB_FSM_S 20\r
+/* SARADC_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */\r
+/*description: */\r
+#define SARADC_XPD_SAR_FSM 0x0000000F\r
+#define SARADC_XPD_SAR_FSM_M ((SARADC_XPD_SAR_FSM_V)<<(SARADC_XPD_SAR_FSM_S))\r
+#define SARADC_XPD_SAR_FSM_V 0xF\r
+#define SARADC_XPD_SAR_FSM_S 16\r
+/* SARADC_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */\r
+/*description: */\r
+#define SARADC_AMP_SHORT_REF_GND_FSM 0x0000000F\r
+#define SARADC_AMP_SHORT_REF_GND_FSM_M ((SARADC_AMP_SHORT_REF_GND_FSM_V)<<(SARADC_AMP_SHORT_REF_GND_FSM_S))\r
+#define SARADC_AMP_SHORT_REF_GND_FSM_V 0xF\r
+#define SARADC_AMP_SHORT_REF_GND_FSM_S 12\r
+/* SARADC_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */\r
+/*description: */\r
+#define SARADC_AMP_SHORT_REF_FSM 0x0000000F\r
+#define SARADC_AMP_SHORT_REF_FSM_M ((SARADC_AMP_SHORT_REF_FSM_V)<<(SARADC_AMP_SHORT_REF_FSM_S))\r
+#define SARADC_AMP_SHORT_REF_FSM_V 0xF\r
+#define SARADC_AMP_SHORT_REF_FSM_S 8\r
+/* SARADC_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */\r
+/*description: */\r
+#define SARADC_AMP_RST_FB_FSM 0x0000000F\r
+#define SARADC_AMP_RST_FB_FSM_M ((SARADC_AMP_RST_FB_FSM_V)<<(SARADC_AMP_RST_FB_FSM_S))\r
+#define SARADC_AMP_RST_FB_FSM_V 0xF\r
+#define SARADC_AMP_RST_FB_FSM_S 4\r
+/* SARADC_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */\r
+/*description: */\r
+#define SARADC_XPD_SAR_AMP_FSM 0x0000000F\r
+#define SARADC_XPD_SAR_AMP_FSM_M ((SARADC_XPD_SAR_AMP_FSM_V)<<(SARADC_XPD_SAR_AMP_FSM_S))\r
+#define SARADC_XPD_SAR_AMP_FSM_V 0xF\r
+#define SARADC_XPD_SAR_AMP_FSM_S 0\r
+\r
+#define SARADC_SAR_READ_STATUS2_REG (DR_REG_SARADC_BASE + 0x0014)\r
+/* SARADC_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define SARADC_SAR2_READER_STATUS 0xFFFFFFFF\r
+#define SARADC_SAR2_READER_STATUS_M ((SARADC_SAR2_READER_STATUS_V)<<(SARADC_SAR2_READER_STATUS_S))\r
+#define SARADC_SAR2_READER_STATUS_V 0xFFFFFFFF\r
+#define SARADC_SAR2_READER_STATUS_S 0\r
+\r
+#define SARADC_ULP_CP_SLEEP_CYC0_REG (DR_REG_SARADC_BASE + 0x0018)\r
+/* SARADC_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */\r
+/*description: sleep cycles for ULP-coprocessor timer*/\r
+#define SARADC_SLEEP_CYCLES_S0 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S0_M ((SARADC_SLEEP_CYCLES_S0_V)<<(SARADC_SLEEP_CYCLES_S0_S))\r
+#define SARADC_SLEEP_CYCLES_S0_V 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S0_S 0\r
+\r
+#define SARADC_ULP_CP_SLEEP_CYC1_REG (DR_REG_SARADC_BASE + 0x001c)\r
+/* SARADC_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */\r
+/*description: */\r
+#define SARADC_SLEEP_CYCLES_S1 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S1_M ((SARADC_SLEEP_CYCLES_S1_V)<<(SARADC_SLEEP_CYCLES_S1_S))\r
+#define SARADC_SLEEP_CYCLES_S1_V 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S1_S 0\r
+\r
+#define SARADC_ULP_CP_SLEEP_CYC2_REG (DR_REG_SARADC_BASE + 0x0020)\r
+/* SARADC_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */\r
+/*description: */\r
+#define SARADC_SLEEP_CYCLES_S2 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S2_M ((SARADC_SLEEP_CYCLES_S2_V)<<(SARADC_SLEEP_CYCLES_S2_S))\r
+#define SARADC_SLEEP_CYCLES_S2_V 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S2_S 0\r
+\r
+#define SARADC_ULP_CP_SLEEP_CYC3_REG (DR_REG_SARADC_BASE + 0x0024)\r
+/* SARADC_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */\r
+/*description: */\r
+#define SARADC_SLEEP_CYCLES_S3 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S3_M ((SARADC_SLEEP_CYCLES_S3_V)<<(SARADC_SLEEP_CYCLES_S3_S))\r
+#define SARADC_SLEEP_CYCLES_S3_V 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S3_S 0\r
+\r
+#define SARADC_ULP_CP_SLEEP_CYC4_REG (DR_REG_SARADC_BASE + 0x0028)\r
+/* SARADC_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */\r
+/*description: */\r
+#define SARADC_SLEEP_CYCLES_S4 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S4_M ((SARADC_SLEEP_CYCLES_S4_V)<<(SARADC_SLEEP_CYCLES_S4_S))\r
+#define SARADC_SLEEP_CYCLES_S4_V 0xFFFFFFFF\r
+#define SARADC_SLEEP_CYCLES_S4_S 0\r
+\r
+#define SARADC_SAR_START_FORCE_REG (DR_REG_SARADC_BASE + 0x002c)\r
+/* SARADC_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: N/A*/\r
+#define SARADC_SAR2_PWDET_EN (BIT(24))\r
+#define SARADC_SAR2_PWDET_EN_M (BIT(24))\r
+#define SARADC_SAR2_PWDET_EN_V 0x1\r
+#define SARADC_SAR2_PWDET_EN_S 24\r
+/* SARADC_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: stop SAR ADC1 conversion*/\r
+#define SARADC_SAR1_STOP (BIT(23))\r
+#define SARADC_SAR1_STOP_M (BIT(23))\r
+#define SARADC_SAR1_STOP_V 0x1\r
+#define SARADC_SAR1_STOP_S 23\r
+/* SARADC_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: stop SAR ADC2 conversion*/\r
+#define SARADC_SAR2_STOP (BIT(22))\r
+#define SARADC_SAR2_STOP_M (BIT(22))\r
+#define SARADC_SAR2_STOP_V 0x1\r
+#define SARADC_SAR2_STOP_S 22\r
+/* SARADC_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */\r
+/*description: initialized PC for ULP-coprocessor*/\r
+#define SARADC_PC_INIT 0x000007FF\r
+#define SARADC_PC_INIT_M ((SARADC_PC_INIT_V)<<(SARADC_PC_INIT_S))\r
+#define SARADC_PC_INIT_V 0x7FF\r
+#define SARADC_PC_INIT_S 11\r
+/* SARADC_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_SARCLK_EN (BIT(10))\r
+#define SARADC_SARCLK_EN_M (BIT(10))\r
+#define SARADC_SARCLK_EN_V 0x1\r
+#define SARADC_SARCLK_EN_S 10\r
+/* SARADC_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top\r
+ = 1*/\r
+#define SARADC_ULP_CP_START_TOP (BIT(9))\r
+#define SARADC_ULP_CP_START_TOP_M (BIT(9))\r
+#define SARADC_ULP_CP_START_TOP_V 0x1\r
+#define SARADC_ULP_CP_START_TOP_S 9\r
+/* SARADC_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer*/\r
+#define SARADC_ULP_CP_FORCE_START_TOP (BIT(8))\r
+#define SARADC_ULP_CP_FORCE_START_TOP_M (BIT(8))\r
+#define SARADC_ULP_CP_FORCE_START_TOP_V 0x1\r
+#define SARADC_ULP_CP_FORCE_START_TOP_S 8\r
+/* SARADC_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */\r
+/*description: SAR2_PWDET_CCT PA power detector capacitance tuning.*/\r
+#define SARADC_SAR2_PWDET_CCT 0x00000007\r
+#define SARADC_SAR2_PWDET_CCT_M ((SARADC_SAR2_PWDET_CCT_V)<<(SARADC_SAR2_PWDET_CCT_S))\r
+#define SARADC_SAR2_PWDET_CCT_V 0x7\r
+#define SARADC_SAR2_PWDET_CCT_S 5\r
+/* SARADC_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: SAR2_EN_TEST only active when reg_sar2_dig_force = 0*/\r
+#define SARADC_SAR2_EN_TEST (BIT(4))\r
+#define SARADC_SAR2_EN_TEST_M (BIT(4))\r
+#define SARADC_SAR2_EN_TEST_V 0x1\r
+#define SARADC_SAR2_EN_TEST_S 4\r
+/* SARADC_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */\r
+/*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/\r
+#define SARADC_SAR2_BIT_WIDTH 0x00000003\r
+#define SARADC_SAR2_BIT_WIDTH_M ((SARADC_SAR2_BIT_WIDTH_V)<<(SARADC_SAR2_BIT_WIDTH_S))\r
+#define SARADC_SAR2_BIT_WIDTH_V 0x3\r
+#define SARADC_SAR2_BIT_WIDTH_S 2\r
+/* SARADC_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */\r
+/*description: 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits*/\r
+#define SARADC_SAR1_BIT_WIDTH 0x00000003\r
+#define SARADC_SAR1_BIT_WIDTH_M ((SARADC_SAR1_BIT_WIDTH_V)<<(SARADC_SAR1_BIT_WIDTH_S))\r
+#define SARADC_SAR1_BIT_WIDTH_V 0x3\r
+#define SARADC_SAR1_BIT_WIDTH_S 0\r
+\r
+#define SARADC_SAR_MEM_WR_CTRL_REG (DR_REG_SARADC_BASE + 0x0030)\r
+/* SARADC_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: */\r
+#define SARADC_RTC_MEM_WR_OFFST_CLR (BIT(22))\r
+#define SARADC_RTC_MEM_WR_OFFST_CLR_M (BIT(22))\r
+#define SARADC_RTC_MEM_WR_OFFST_CLR_V 0x1\r
+#define SARADC_RTC_MEM_WR_OFFST_CLR_S 22\r
+/* SARADC_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */\r
+/*description: */\r
+#define SARADC_MEM_WR_ADDR_SIZE 0x000007FF\r
+#define SARADC_MEM_WR_ADDR_SIZE_M ((SARADC_MEM_WR_ADDR_SIZE_V)<<(SARADC_MEM_WR_ADDR_SIZE_S))\r
+#define SARADC_MEM_WR_ADDR_SIZE_V 0x7FF\r
+#define SARADC_MEM_WR_ADDR_SIZE_S 11\r
+/* SARADC_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */\r
+/*description: */\r
+#define SARADC_MEM_WR_ADDR_INIT 0x000007FF\r
+#define SARADC_MEM_WR_ADDR_INIT_M ((SARADC_MEM_WR_ADDR_INIT_V)<<(SARADC_MEM_WR_ADDR_INIT_S))\r
+#define SARADC_MEM_WR_ADDR_INIT_V 0x7FF\r
+#define SARADC_MEM_WR_ADDR_INIT_S 0\r
+\r
+#define SARADC_SAR_ATTEN1_REG (DR_REG_SARADC_BASE + 0x0034)\r
+/* SARADC_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */\r
+/*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/\r
+#define SARADC_SAR1_ATTEN 0xFFFFFFFF\r
+#define SARADC_SAR1_ATTEN_M ((SARADC_SAR1_ATTEN_V)<<(SARADC_SAR1_ATTEN_S))\r
+#define SARADC_SAR1_ATTEN_V 0xFFFFFFFF\r
+#define SARADC_SAR1_ATTEN_S 0\r
+\r
+#define SARADC_SAR_ATTEN2_REG (DR_REG_SARADC_BASE + 0x0038)\r
+/* SARADC_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */\r
+/*description: 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB*/\r
+#define SARADC_SAR2_ATTEN 0xFFFFFFFF\r
+#define SARADC_SAR2_ATTEN_M ((SARADC_SAR2_ATTEN_V)<<(SARADC_SAR2_ATTEN_S))\r
+#define SARADC_SAR2_ATTEN_V 0xFFFFFFFF\r
+#define SARADC_SAR2_ATTEN_S 0\r
+\r
+#define SARADC_SAR_SLAVE_ADDR1_REG (DR_REG_SARADC_BASE + 0x003c)\r
+/* SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */\r
+/*description: */\r
+#define SARADC_MEAS_STATUS 0x000000FF\r
+#define SARADC_MEAS_STATUS_M ((SARADC_MEAS_STATUS_V)<<(SARADC_MEAS_STATUS_S))\r
+#define SARADC_MEAS_STATUS_V 0xFF\r
+#define SARADC_MEAS_STATUS_S 22\r
+/* SARADC_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */\r
+/*description: */\r
+#define SARADC_I2C_SLAVE_ADDR0 0x000007FF\r
+#define SARADC_I2C_SLAVE_ADDR0_M ((SARADC_I2C_SLAVE_ADDR0_V)<<(SARADC_I2C_SLAVE_ADDR0_S))\r
+#define SARADC_I2C_SLAVE_ADDR0_V 0x7FF\r
+#define SARADC_I2C_SLAVE_ADDR0_S 11\r
+/* SARADC_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */\r
+/*description: */\r
+#define SARADC_I2C_SLAVE_ADDR1 0x000007FF\r
+#define SARADC_I2C_SLAVE_ADDR1_M ((SARADC_I2C_SLAVE_ADDR1_V)<<(SARADC_I2C_SLAVE_ADDR1_S))\r
+#define SARADC_I2C_SLAVE_ADDR1_V 0x7FF\r
+#define SARADC_I2C_SLAVE_ADDR1_S 0\r
+\r
+#define SARADC_SAR_SLAVE_ADDR2_REG (DR_REG_SARADC_BASE + 0x0040)\r
+/* SARADC_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */\r
+/*description: */\r
+#define SARADC_I2C_SLAVE_ADDR2 0x000007FF\r
+#define SARADC_I2C_SLAVE_ADDR2_M ((SARADC_I2C_SLAVE_ADDR2_V)<<(SARADC_I2C_SLAVE_ADDR2_S))\r
+#define SARADC_I2C_SLAVE_ADDR2_V 0x7FF\r
+#define SARADC_I2C_SLAVE_ADDR2_S 11\r
+/* SARADC_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */\r
+/*description: */\r
+#define SARADC_I2C_SLAVE_ADDR3 0x000007FF\r
+#define SARADC_I2C_SLAVE_ADDR3_M ((SARADC_I2C_SLAVE_ADDR3_V)<<(SARADC_I2C_SLAVE_ADDR3_S))\r
+#define SARADC_I2C_SLAVE_ADDR3_V 0x7FF\r
+#define SARADC_I2C_SLAVE_ADDR3_S 0\r
+\r
+#define SARADC_SAR_SLAVE_ADDR3_REG (DR_REG_SARADC_BASE + 0x0044)\r
+/* SARADC_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */\r
+/*description: indicate temperature sensor out ready*/\r
+#define SARADC_TSENS_RDY_OUT (BIT(30))\r
+#define SARADC_TSENS_RDY_OUT_M (BIT(30))\r
+#define SARADC_TSENS_RDY_OUT_V 0x1\r
+#define SARADC_TSENS_RDY_OUT_S 30\r
+/* SARADC_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */\r
+/*description: temperature sensor data out*/\r
+#define SARADC_TSENS_OUT 0x000000FF\r
+#define SARADC_TSENS_OUT_M ((SARADC_TSENS_OUT_V)<<(SARADC_TSENS_OUT_S))\r
+#define SARADC_TSENS_OUT_V 0xFF\r
+#define SARADC_TSENS_OUT_S 22\r
+/* SARADC_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */\r
+/*description: */\r
+#define SARADC_I2C_SLAVE_ADDR4 0x000007FF\r
+#define SARADC_I2C_SLAVE_ADDR4_M ((SARADC_I2C_SLAVE_ADDR4_V)<<(SARADC_I2C_SLAVE_ADDR4_S))\r
+#define SARADC_I2C_SLAVE_ADDR4_V 0x7FF\r
+#define SARADC_I2C_SLAVE_ADDR4_S 11\r
+/* SARADC_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */\r
+/*description: */\r
+#define SARADC_I2C_SLAVE_ADDR5 0x000007FF\r
+#define SARADC_I2C_SLAVE_ADDR5_M ((SARADC_I2C_SLAVE_ADDR5_V)<<(SARADC_I2C_SLAVE_ADDR5_S))\r
+#define SARADC_I2C_SLAVE_ADDR5_V 0x7FF\r
+#define SARADC_I2C_SLAVE_ADDR5_S 0\r
+\r
+#define SARADC_SAR_SLAVE_ADDR4_REG (DR_REG_SARADC_BASE + 0x0048)\r
+/* SARADC_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */\r
+/*description: indicate I2C done*/\r
+#define SARADC_I2C_DONE (BIT(30))\r
+#define SARADC_I2C_DONE_M (BIT(30))\r
+#define SARADC_I2C_DONE_V 0x1\r
+#define SARADC_I2C_DONE_S 30\r
+/* SARADC_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */\r
+/*description: I2C read data*/\r
+#define SARADC_I2C_RDATA 0x000000FF\r
+#define SARADC_I2C_RDATA_M ((SARADC_I2C_RDATA_V)<<(SARADC_I2C_RDATA_S))\r
+#define SARADC_I2C_RDATA_V 0xFF\r
+#define SARADC_I2C_RDATA_S 22\r
+/* SARADC_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */\r
+/*description: */\r
+#define SARADC_I2C_SLAVE_ADDR6 0x000007FF\r
+#define SARADC_I2C_SLAVE_ADDR6_M ((SARADC_I2C_SLAVE_ADDR6_V)<<(SARADC_I2C_SLAVE_ADDR6_S))\r
+#define SARADC_I2C_SLAVE_ADDR6_V 0x7FF\r
+#define SARADC_I2C_SLAVE_ADDR6_S 11\r
+/* SARADC_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */\r
+/*description: */\r
+#define SARADC_I2C_SLAVE_ADDR7 0x000007FF\r
+#define SARADC_I2C_SLAVE_ADDR7_M ((SARADC_I2C_SLAVE_ADDR7_V)<<(SARADC_I2C_SLAVE_ADDR7_S))\r
+#define SARADC_I2C_SLAVE_ADDR7_V 0x7FF\r
+#define SARADC_I2C_SLAVE_ADDR7_S 0\r
+\r
+#define SARADC_SAR_TSENS_CTRL_REG (DR_REG_SARADC_BASE + 0x004c)\r
+/* SARADC_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: temperature sensor dump out only active when reg_tsens_power_up_force = 1*/\r
+#define SARADC_TSENS_DUMP_OUT (BIT(26))\r
+#define SARADC_TSENS_DUMP_OUT_M (BIT(26))\r
+#define SARADC_TSENS_DUMP_OUT_V 0x1\r
+#define SARADC_TSENS_DUMP_OUT_S 26\r
+/* SARADC_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: 1: dump out & power up controlled by SW 0: by FSM*/\r
+#define SARADC_TSENS_POWER_UP_FORCE (BIT(25))\r
+#define SARADC_TSENS_POWER_UP_FORCE_M (BIT(25))\r
+#define SARADC_TSENS_POWER_UP_FORCE_V 0x1\r
+#define SARADC_TSENS_POWER_UP_FORCE_S 25\r
+/* SARADC_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: temperature sensor power up*/\r
+#define SARADC_TSENS_POWER_UP (BIT(24))\r
+#define SARADC_TSENS_POWER_UP_M (BIT(24))\r
+#define SARADC_TSENS_POWER_UP_V 0x1\r
+#define SARADC_TSENS_POWER_UP_S 24\r
+/* SARADC_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */\r
+/*description: temperature sensor clock divider*/\r
+#define SARADC_TSENS_CLK_DIV 0x000000FF\r
+#define SARADC_TSENS_CLK_DIV_M ((SARADC_TSENS_CLK_DIV_V)<<(SARADC_TSENS_CLK_DIV_S))\r
+#define SARADC_TSENS_CLK_DIV_V 0xFF\r
+#define SARADC_TSENS_CLK_DIV_S 16\r
+/* SARADC_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: invert temperature sensor data*/\r
+#define SARADC_TSENS_IN_INV (BIT(15))\r
+#define SARADC_TSENS_IN_INV_M (BIT(15))\r
+#define SARADC_TSENS_IN_INV_V 0x1\r
+#define SARADC_TSENS_IN_INV_S 15\r
+/* SARADC_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */\r
+/*description: */\r
+#define SARADC_TSENS_CLK_GATED (BIT(14))\r
+#define SARADC_TSENS_CLK_GATED_M (BIT(14))\r
+#define SARADC_TSENS_CLK_GATED_V 0x1\r
+#define SARADC_TSENS_CLK_GATED_S 14\r
+/* SARADC_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: */\r
+#define SARADC_TSENS_CLK_INV (BIT(13))\r
+#define SARADC_TSENS_CLK_INV_M (BIT(13))\r
+#define SARADC_TSENS_CLK_INV_V 0x1\r
+#define SARADC_TSENS_CLK_INV_S 13\r
+/* SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_TSENS_XPD_FORCE (BIT(12))\r
+#define SARADC_TSENS_XPD_FORCE_M (BIT(12))\r
+#define SARADC_TSENS_XPD_FORCE_V 0x1\r
+#define SARADC_TSENS_XPD_FORCE_S 12\r
+/* SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */\r
+/*description: */\r
+#define SARADC_TSENS_XPD_WAIT 0x00000FFF\r
+#define SARADC_TSENS_XPD_WAIT_M ((SARADC_TSENS_XPD_WAIT_V)<<(SARADC_TSENS_XPD_WAIT_S))\r
+#define SARADC_TSENS_XPD_WAIT_V 0xFFF\r
+#define SARADC_TSENS_XPD_WAIT_S 0\r
+\r
+#define SARADC_SAR_I2C_CTRL_REG (DR_REG_SARADC_BASE + 0x0050)\r
+/* SARADC_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: 1: I2C started by SW 0: I2C started by FSM*/\r
+#define SARADC_SAR_I2C_START_FORCE (BIT(29))\r
+#define SARADC_SAR_I2C_START_FORCE_M (BIT(29))\r
+#define SARADC_SAR_I2C_START_FORCE_V 0x1\r
+#define SARADC_SAR_I2C_START_FORCE_S 29\r
+/* SARADC_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: start I2C only active when reg_sar_i2c_start_force = 1*/\r
+#define SARADC_SAR_I2C_START (BIT(28))\r
+#define SARADC_SAR_I2C_START_M (BIT(28))\r
+#define SARADC_SAR_I2C_START_V 0x1\r
+#define SARADC_SAR_I2C_START_S 28\r
+/* SARADC_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */\r
+/*description: I2C control data only active when reg_sar_i2c_start_force = 1*/\r
+#define SARADC_SAR_I2C_CTRL 0x0FFFFFFF\r
+#define SARADC_SAR_I2C_CTRL_M ((SARADC_SAR_I2C_CTRL_V)<<(SARADC_SAR_I2C_CTRL_S))\r
+#define SARADC_SAR_I2C_CTRL_V 0xFFFFFFF\r
+#define SARADC_SAR_I2C_CTRL_S 0\r
+\r
+#define SARADC_SAR_MEAS_START1_REG (DR_REG_SARADC_BASE + 0x0054)\r
+/* SARADC_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1\r
+ pad enable bitmap is controlled by ULP-coprocessor*/\r
+#define SARADC_SAR1_EN_PAD_FORCE (BIT(31))\r
+#define SARADC_SAR1_EN_PAD_FORCE_M (BIT(31))\r
+#define SARADC_SAR1_EN_PAD_FORCE_V 0x1\r
+#define SARADC_SAR1_EN_PAD_FORCE_S 31\r
+/* SARADC_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */\r
+/*description: SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1*/\r
+#define SARADC_SAR1_EN_PAD 0x00000FFF\r
+#define SARADC_SAR1_EN_PAD_M ((SARADC_SAR1_EN_PAD_V)<<(SARADC_SAR1_EN_PAD_S))\r
+#define SARADC_SAR1_EN_PAD_V 0xFFF\r
+#define SARADC_SAR1_EN_PAD_S 19\r
+/* SARADC_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1\r
+ controller is started by ULP-coprocessor*/\r
+#define SARADC_MEAS1_START_FORCE (BIT(18))\r
+#define SARADC_MEAS1_START_FORCE_M (BIT(18))\r
+#define SARADC_MEAS1_START_FORCE_V 0x1\r
+#define SARADC_MEAS1_START_FORCE_S 18\r
+/* SARADC_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: SAR ADC1 controller (in RTC) starts conversion only active when\r
+ reg_meas1_start_force = 1*/\r
+#define SARADC_MEAS1_START_SAR (BIT(17))\r
+#define SARADC_MEAS1_START_SAR_M (BIT(17))\r
+#define SARADC_MEAS1_START_SAR_V 0x1\r
+#define SARADC_MEAS1_START_SAR_S 17\r
+/* SARADC_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: SAR ADC1 conversion done indication*/\r
+#define SARADC_MEAS1_DONE_SAR (BIT(16))\r
+#define SARADC_MEAS1_DONE_SAR_M (BIT(16))\r
+#define SARADC_MEAS1_DONE_SAR_V 0x1\r
+#define SARADC_MEAS1_DONE_SAR_S 16\r
+/* SARADC_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */\r
+/*description: SAR ADC1 data*/\r
+#define SARADC_MEAS1_DATA_SAR 0x0000FFFF\r
+#define SARADC_MEAS1_DATA_SAR_M ((SARADC_MEAS1_DATA_SAR_V)<<(SARADC_MEAS1_DATA_SAR_S))\r
+#define SARADC_MEAS1_DATA_SAR_V 0xFFFF\r
+#define SARADC_MEAS1_DATA_SAR_S 0\r
+\r
+#define SARADC_SAR_TOUCH_CTRL1_REG (DR_REG_SARADC_BASE + 0x0058)\r
+/* SARADC_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled\r
+ by FSM in ULP-coprocessor*/\r
+#define SARADC_HALL_PHASE_FORCE (BIT(27))\r
+#define SARADC_HALL_PHASE_FORCE_M (BIT(27))\r
+#define SARADC_HALL_PHASE_FORCE_V 0x1\r
+#define SARADC_HALL_PHASE_FORCE_S 27\r
+/* SARADC_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by\r
+ FSM in ULP-coprocessor*/\r
+#define SARADC_XPD_HALL_FORCE (BIT(26))\r
+#define SARADC_XPD_HALL_FORCE_M (BIT(26))\r
+#define SARADC_XPD_HALL_FORCE_V 0x1\r
+#define SARADC_XPD_HALL_FORCE_S 26\r
+/* SARADC_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */\r
+/*description: 1: wakeup interrupt is generated if SET1 is ��touched�� 0:\r
+ wakeup interrupt is generated only if SET1 & SET2 is both ��touched��*/\r
+#define SARADC_TOUCH_OUT_1EN (BIT(25))\r
+#define SARADC_TOUCH_OUT_1EN_M (BIT(25))\r
+#define SARADC_TOUCH_OUT_1EN_V 0x1\r
+#define SARADC_TOUCH_OUT_1EN_S 25\r
+/* SARADC_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: 1: when the counter is greater then the threshold the touch\r
+ pad is considered as ��touched�� 0: when the counter is less than the threshold the touch pad is considered as ��touched��*/\r
+#define SARADC_TOUCH_OUT_SEL (BIT(24))\r
+#define SARADC_TOUCH_OUT_SEL_M (BIT(24))\r
+#define SARADC_TOUCH_OUT_SEL_V 0x1\r
+#define SARADC_TOUCH_OUT_SEL_S 24\r
+/* SARADC_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */\r
+/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/\r
+#define SARADC_TOUCH_XPD_WAIT 0x000000FF\r
+#define SARADC_TOUCH_XPD_WAIT_M ((SARADC_TOUCH_XPD_WAIT_V)<<(SARADC_TOUCH_XPD_WAIT_S))\r
+#define SARADC_TOUCH_XPD_WAIT_V 0xFF\r
+#define SARADC_TOUCH_XPD_WAIT_S 16\r
+/* SARADC_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */\r
+/*description: the meas length (in 8MHz)*/\r
+#define SARADC_TOUCH_MEAS_DELAY 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_DELAY_M ((SARADC_TOUCH_MEAS_DELAY_V)<<(SARADC_TOUCH_MEAS_DELAY_S))\r
+#define SARADC_TOUCH_MEAS_DELAY_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_DELAY_S 0\r
+\r
+#define SARADC_SAR_TOUCH_THRES1_REG (DR_REG_SARADC_BASE + 0x005c)\r
+/* SARADC_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 0*/\r
+#define SARADC_TOUCH_OUT_TH0 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH0_M ((SARADC_TOUCH_OUT_TH0_V)<<(SARADC_TOUCH_OUT_TH0_S))\r
+#define SARADC_TOUCH_OUT_TH0_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH0_S 16\r
+/* SARADC_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 1*/\r
+#define SARADC_TOUCH_OUT_TH1 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH1_M ((SARADC_TOUCH_OUT_TH1_V)<<(SARADC_TOUCH_OUT_TH1_S))\r
+#define SARADC_TOUCH_OUT_TH1_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH1_S 0\r
+\r
+#define SARADC_SAR_TOUCH_THRES2_REG (DR_REG_SARADC_BASE + 0x0060)\r
+/* SARADC_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 2*/\r
+#define SARADC_TOUCH_OUT_TH2 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH2_M ((SARADC_TOUCH_OUT_TH2_V)<<(SARADC_TOUCH_OUT_TH2_S))\r
+#define SARADC_TOUCH_OUT_TH2_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH2_S 16\r
+/* SARADC_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 3*/\r
+#define SARADC_TOUCH_OUT_TH3 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH3_M ((SARADC_TOUCH_OUT_TH3_V)<<(SARADC_TOUCH_OUT_TH3_S))\r
+#define SARADC_TOUCH_OUT_TH3_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH3_S 0\r
+\r
+#define SARADC_SAR_TOUCH_THRES3_REG (DR_REG_SARADC_BASE + 0x0064)\r
+/* SARADC_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 4*/\r
+#define SARADC_TOUCH_OUT_TH4 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH4_M ((SARADC_TOUCH_OUT_TH4_V)<<(SARADC_TOUCH_OUT_TH4_S))\r
+#define SARADC_TOUCH_OUT_TH4_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH4_S 16\r
+/* SARADC_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 5*/\r
+#define SARADC_TOUCH_OUT_TH5 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH5_M ((SARADC_TOUCH_OUT_TH5_V)<<(SARADC_TOUCH_OUT_TH5_S))\r
+#define SARADC_TOUCH_OUT_TH5_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH5_S 0\r
+\r
+#define SARADC_SAR_TOUCH_THRES4_REG (DR_REG_SARADC_BASE + 0x0068)\r
+/* SARADC_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 6*/\r
+#define SARADC_TOUCH_OUT_TH6 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH6_M ((SARADC_TOUCH_OUT_TH6_V)<<(SARADC_TOUCH_OUT_TH6_S))\r
+#define SARADC_TOUCH_OUT_TH6_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH6_S 16\r
+/* SARADC_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 7*/\r
+#define SARADC_TOUCH_OUT_TH7 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH7_M ((SARADC_TOUCH_OUT_TH7_V)<<(SARADC_TOUCH_OUT_TH7_S))\r
+#define SARADC_TOUCH_OUT_TH7_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH7_S 0\r
+\r
+#define SARADC_SAR_TOUCH_THRES5_REG (DR_REG_SARADC_BASE + 0x006c)\r
+/* SARADC_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 8*/\r
+#define SARADC_TOUCH_OUT_TH8 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH8_M ((SARADC_TOUCH_OUT_TH8_V)<<(SARADC_TOUCH_OUT_TH8_S))\r
+#define SARADC_TOUCH_OUT_TH8_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH8_S 16\r
+/* SARADC_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the threshold for touch pad 9*/\r
+#define SARADC_TOUCH_OUT_TH9 0x0000FFFF\r
+#define SARADC_TOUCH_OUT_TH9_M ((SARADC_TOUCH_OUT_TH9_V)<<(SARADC_TOUCH_OUT_TH9_S))\r
+#define SARADC_TOUCH_OUT_TH9_V 0xFFFF\r
+#define SARADC_TOUCH_OUT_TH9_S 0\r
+\r
+#define SARADC_SAR_TOUCH_OUT1_REG (DR_REG_SARADC_BASE + 0x0070)\r
+/* SARADC_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 0*/\r
+#define SARADC_TOUCH_MEAS_OUT0 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT0_M ((SARADC_TOUCH_MEAS_OUT0_V)<<(SARADC_TOUCH_MEAS_OUT0_S))\r
+#define SARADC_TOUCH_MEAS_OUT0_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT0_S 16\r
+/* SARADC_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 1*/\r
+#define SARADC_TOUCH_MEAS_OUT1 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT1_M ((SARADC_TOUCH_MEAS_OUT1_V)<<(SARADC_TOUCH_MEAS_OUT1_S))\r
+#define SARADC_TOUCH_MEAS_OUT1_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT1_S 0\r
+\r
+#define SARADC_SAR_TOUCH_OUT2_REG (DR_REG_SARADC_BASE + 0x0074)\r
+/* SARADC_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 2*/\r
+#define SARADC_TOUCH_MEAS_OUT2 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT2_M ((SARADC_TOUCH_MEAS_OUT2_V)<<(SARADC_TOUCH_MEAS_OUT2_S))\r
+#define SARADC_TOUCH_MEAS_OUT2_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT2_S 16\r
+/* SARADC_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 3*/\r
+#define SARADC_TOUCH_MEAS_OUT3 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT3_M ((SARADC_TOUCH_MEAS_OUT3_V)<<(SARADC_TOUCH_MEAS_OUT3_S))\r
+#define SARADC_TOUCH_MEAS_OUT3_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT3_S 0\r
+\r
+#define SARADC_SAR_TOUCH_OUT3_REG (DR_REG_SARADC_BASE + 0x0078)\r
+/* SARADC_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 4*/\r
+#define SARADC_TOUCH_MEAS_OUT4 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT4_M ((SARADC_TOUCH_MEAS_OUT4_V)<<(SARADC_TOUCH_MEAS_OUT4_S))\r
+#define SARADC_TOUCH_MEAS_OUT4_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT4_S 16\r
+/* SARADC_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 5*/\r
+#define SARADC_TOUCH_MEAS_OUT5 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT5_M ((SARADC_TOUCH_MEAS_OUT5_V)<<(SARADC_TOUCH_MEAS_OUT5_S))\r
+#define SARADC_TOUCH_MEAS_OUT5_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT5_S 0\r
+\r
+#define SARADC_SAR_TOUCH_OUT4_REG (DR_REG_SARADC_BASE + 0x007c)\r
+/* SARADC_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 6*/\r
+#define SARADC_TOUCH_MEAS_OUT6 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT6_M ((SARADC_TOUCH_MEAS_OUT6_V)<<(SARADC_TOUCH_MEAS_OUT6_S))\r
+#define SARADC_TOUCH_MEAS_OUT6_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT6_S 16\r
+/* SARADC_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 7*/\r
+#define SARADC_TOUCH_MEAS_OUT7 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT7_M ((SARADC_TOUCH_MEAS_OUT7_V)<<(SARADC_TOUCH_MEAS_OUT7_S))\r
+#define SARADC_TOUCH_MEAS_OUT7_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT7_S 0\r
+\r
+#define SARADC_SAR_TOUCH_OUT5_REG (DR_REG_SARADC_BASE + 0x0080)\r
+/* SARADC_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 8*/\r
+#define SARADC_TOUCH_MEAS_OUT8 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT8_M ((SARADC_TOUCH_MEAS_OUT8_V)<<(SARADC_TOUCH_MEAS_OUT8_S))\r
+#define SARADC_TOUCH_MEAS_OUT8_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT8_S 16\r
+/* SARADC_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: the counter for touch pad 9*/\r
+#define SARADC_TOUCH_MEAS_OUT9 0x0000FFFF\r
+#define SARADC_TOUCH_MEAS_OUT9_M ((SARADC_TOUCH_MEAS_OUT9_V)<<(SARADC_TOUCH_MEAS_OUT9_S))\r
+#define SARADC_TOUCH_MEAS_OUT9_V 0xFFFF\r
+#define SARADC_TOUCH_MEAS_OUT9_S 0\r
+\r
+#define SARADC_SAR_TOUCH_CTRL2_REG (DR_REG_SARADC_BASE + 0x0084)\r
+/* SARADC_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */\r
+/*description: to clear reg_touch_meas_en*/\r
+#define SARADC_TOUCH_MEAS_EN_CLR (BIT(30))\r
+#define SARADC_TOUCH_MEAS_EN_CLR_M (BIT(30))\r
+#define SARADC_TOUCH_MEAS_EN_CLR_V 0x1\r
+#define SARADC_TOUCH_MEAS_EN_CLR_S 30\r
+/* SARADC_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */\r
+/*description: sleep cycles for timer*/\r
+#define SARADC_TOUCH_SLEEP_CYCLES 0x0000FFFF\r
+#define SARADC_TOUCH_SLEEP_CYCLES_M ((SARADC_TOUCH_SLEEP_CYCLES_V)<<(SARADC_TOUCH_SLEEP_CYCLES_S))\r
+#define SARADC_TOUCH_SLEEP_CYCLES_V 0xFFFF\r
+#define SARADC_TOUCH_SLEEP_CYCLES_S 14\r
+/* SARADC_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */\r
+/*description: 1: to start touch fsm by SW 0: to start touch fsm by timer*/\r
+#define SARADC_TOUCH_START_FORCE (BIT(13))\r
+#define SARADC_TOUCH_START_FORCE_M (BIT(13))\r
+#define SARADC_TOUCH_START_FORCE_V 0x1\r
+#define SARADC_TOUCH_START_FORCE_S 13\r
+/* SARADC_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */\r
+/*description: 1: start touch fsm valid when reg_touch_start_force is set*/\r
+#define SARADC_TOUCH_START_EN (BIT(12))\r
+#define SARADC_TOUCH_START_EN_M (BIT(12))\r
+#define SARADC_TOUCH_START_EN_V 0x1\r
+#define SARADC_TOUCH_START_EN_S 12\r
+/* SARADC_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */\r
+/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START\r
+ & TOUCH_XPD is controlled by registers*/\r
+#define SARADC_TOUCH_START_FSM_EN (BIT(11))\r
+#define SARADC_TOUCH_START_FSM_EN_M (BIT(11))\r
+#define SARADC_TOUCH_START_FSM_EN_V 0x1\r
+#define SARADC_TOUCH_START_FSM_EN_S 11\r
+/* SARADC_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */\r
+/*description: fsm set 1 to indicate touch touch meas is done*/\r
+#define SARADC_TOUCH_MEAS_DONE (BIT(10))\r
+#define SARADC_TOUCH_MEAS_DONE_M (BIT(10))\r
+#define SARADC_TOUCH_MEAS_DONE_V 0x1\r
+#define SARADC_TOUCH_MEAS_DONE_S 10\r
+/* SARADC_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: 10-bit register to indicate which pads are ��touched��*/\r
+#define SARADC_TOUCH_MEAS_EN 0x000003FF\r
+#define SARADC_TOUCH_MEAS_EN_M ((SARADC_TOUCH_MEAS_EN_V)<<(SARADC_TOUCH_MEAS_EN_S))\r
+#define SARADC_TOUCH_MEAS_EN_V 0x3FF\r
+#define SARADC_TOUCH_MEAS_EN_S 0\r
+\r
+#define SARADC_SAR_TOUCH_ENABLE_REG (DR_REG_SARADC_BASE + 0x008c)\r
+/* SARADC_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */\r
+/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is\r
+ ��touched�� only if at least one of touch pad in SET1 is ��touched��.*/\r
+#define SARADC_TOUCH_PAD_OUTEN1 0x000003FF\r
+#define SARADC_TOUCH_PAD_OUTEN1_M ((SARADC_TOUCH_PAD_OUTEN1_V)<<(SARADC_TOUCH_PAD_OUTEN1_S))\r
+#define SARADC_TOUCH_PAD_OUTEN1_V 0x3FF\r
+#define SARADC_TOUCH_PAD_OUTEN1_S 20\r
+/* SARADC_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */\r
+/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is\r
+ ��touched�� only if at least one of touch pad in SET2 is ��touched��.*/\r
+#define SARADC_TOUCH_PAD_OUTEN2 0x000003FF\r
+#define SARADC_TOUCH_PAD_OUTEN2_M ((SARADC_TOUCH_PAD_OUTEN2_V)<<(SARADC_TOUCH_PAD_OUTEN2_S))\r
+#define SARADC_TOUCH_PAD_OUTEN2_V 0x3FF\r
+#define SARADC_TOUCH_PAD_OUTEN2_S 10\r
+/* SARADC_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */\r
+/*description: Bitmap defining the working set during the measurement.*/\r
+#define SARADC_TOUCH_PAD_WORKEN 0x000003FF\r
+#define SARADC_TOUCH_PAD_WORKEN_M ((SARADC_TOUCH_PAD_WORKEN_V)<<(SARADC_TOUCH_PAD_WORKEN_S))\r
+#define SARADC_TOUCH_PAD_WORKEN_V 0x3FF\r
+#define SARADC_TOUCH_PAD_WORKEN_S 0\r
+\r
+#define SARADC_SAR_READ_CTRL2_REG (DR_REG_SARADC_BASE + 0x0090)\r
+/* SARADC_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: Invert SAR ADC2 data*/\r
+#define SARADC_SAR2_DATA_INV (BIT(29))\r
+#define SARADC_SAR2_DATA_INV_M (BIT(29))\r
+#define SARADC_SAR2_DATA_INV_V 0x1\r
+#define SARADC_SAR2_DATA_INV_S 29\r
+/* SARADC_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR\r
+ ADC2 controlled by RTC ADC2 CTRL*/\r
+#define SARADC_SAR2_DIG_FORCE (BIT(28))\r
+#define SARADC_SAR2_DIG_FORCE_M (BIT(28))\r
+#define SARADC_SAR2_DIG_FORCE_V 0x1\r
+#define SARADC_SAR2_DIG_FORCE_S 28\r
+/* SARADC_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_SAR2_PWDET_FORCE (BIT(27))\r
+#define SARADC_SAR2_PWDET_FORCE_M (BIT(27))\r
+#define SARADC_SAR2_PWDET_FORCE_V 0x1\r
+#define SARADC_SAR2_PWDET_FORCE_S 27\r
+/* SARADC_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */\r
+/*description: */\r
+#define SARADC_SAR2_SAMPLE_NUM 0x000000FF\r
+#define SARADC_SAR2_SAMPLE_NUM_M ((SARADC_SAR2_SAMPLE_NUM_V)<<(SARADC_SAR2_SAMPLE_NUM_S))\r
+#define SARADC_SAR2_SAMPLE_NUM_V 0xFF\r
+#define SARADC_SAR2_SAMPLE_NUM_S 19\r
+/* SARADC_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */\r
+/*description: */\r
+#define SARADC_SAR2_CLK_GATED (BIT(18))\r
+#define SARADC_SAR2_CLK_GATED_M (BIT(18))\r
+#define SARADC_SAR2_CLK_GATED_V 0x1\r
+#define SARADC_SAR2_CLK_GATED_S 18\r
+/* SARADC_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */\r
+/*description: 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width\r
+ 11: for 12-bit width*/\r
+#define SARADC_SAR2_SAMPLE_BIT 0x00000003\r
+#define SARADC_SAR2_SAMPLE_BIT_M ((SARADC_SAR2_SAMPLE_BIT_V)<<(SARADC_SAR2_SAMPLE_BIT_S))\r
+#define SARADC_SAR2_SAMPLE_BIT_V 0x3\r
+#define SARADC_SAR2_SAMPLE_BIT_S 16\r
+/* SARADC_SAR2_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */\r
+/*description: sample cycles for SAR ADC2*/\r
+#define SARADC_SAR2_SAMPLE_CYCLE 0x000000FF\r
+#define SARADC_SAR2_SAMPLE_CYCLE_M ((SARADC_SAR2_SAMPLE_CYCLE_V)<<(SARADC_SAR2_SAMPLE_CYCLE_S))\r
+#define SARADC_SAR2_SAMPLE_CYCLE_V 0xFF\r
+#define SARADC_SAR2_SAMPLE_CYCLE_S 8\r
+/* SARADC_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */\r
+/*description: clock divider*/\r
+#define SARADC_SAR2_CLK_DIV 0x000000FF\r
+#define SARADC_SAR2_CLK_DIV_M ((SARADC_SAR2_CLK_DIV_V)<<(SARADC_SAR2_CLK_DIV_S))\r
+#define SARADC_SAR2_CLK_DIV_V 0xFF\r
+#define SARADC_SAR2_CLK_DIV_S 0\r
+\r
+#define SARADC_SAR_MEAS_START2_REG (DR_REG_SARADC_BASE + 0x0094)\r
+/* SARADC_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2\r
+ pad enable bitmap is controlled by ULP-coprocessor*/\r
+#define SARADC_SAR2_EN_PAD_FORCE (BIT(31))\r
+#define SARADC_SAR2_EN_PAD_FORCE_M (BIT(31))\r
+#define SARADC_SAR2_EN_PAD_FORCE_V 0x1\r
+#define SARADC_SAR2_EN_PAD_FORCE_S 31\r
+/* SARADC_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */\r
+/*description: SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1*/\r
+#define SARADC_SAR2_EN_PAD 0x00000FFF\r
+#define SARADC_SAR2_EN_PAD_M ((SARADC_SAR2_EN_PAD_V)<<(SARADC_SAR2_EN_PAD_S))\r
+#define SARADC_SAR2_EN_PAD_V 0xFFF\r
+#define SARADC_SAR2_EN_PAD_S 19\r
+/* SARADC_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2\r
+ controller is started by ULP-coprocessor*/\r
+#define SARADC_MEAS2_START_FORCE (BIT(18))\r
+#define SARADC_MEAS2_START_FORCE_M (BIT(18))\r
+#define SARADC_MEAS2_START_FORCE_V 0x1\r
+#define SARADC_MEAS2_START_FORCE_S 18\r
+/* SARADC_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: SAR ADC2 controller (in RTC) starts conversion only active when\r
+ reg_meas2_start_force = 1*/\r
+#define SARADC_MEAS2_START_SAR (BIT(17))\r
+#define SARADC_MEAS2_START_SAR_M (BIT(17))\r
+#define SARADC_MEAS2_START_SAR_V 0x1\r
+#define SARADC_MEAS2_START_SAR_S 17\r
+/* SARADC_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: SAR ADC2 conversion done indication*/\r
+#define SARADC_MEAS2_DONE_SAR (BIT(16))\r
+#define SARADC_MEAS2_DONE_SAR_M (BIT(16))\r
+#define SARADC_MEAS2_DONE_SAR_V 0x1\r
+#define SARADC_MEAS2_DONE_SAR_S 16\r
+/* SARADC_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */\r
+/*description: SAR ADC2 data*/\r
+#define SARADC_MEAS2_DATA_SAR 0x0000FFFF\r
+#define SARADC_MEAS2_DATA_SAR_M ((SARADC_MEAS2_DATA_SAR_V)<<(SARADC_MEAS2_DATA_SAR_S))\r
+#define SARADC_MEAS2_DATA_SAR_V 0xFFFF\r
+#define SARADC_MEAS2_DATA_SAR_S 0\r
+\r
+#define SARADC_SAR_DAC_CTRL1_REG (DR_REG_SARADC_BASE + 0x0098)\r
+/* SARADC_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: 1: invert PDAC_CLK*/\r
+#define SARADC_DAC_CLK_INV (BIT(25))\r
+#define SARADC_DAC_CLK_INV_M (BIT(25))\r
+#define SARADC_DAC_CLK_INV_V 0x1\r
+#define SARADC_DAC_CLK_INV_S 25\r
+/* SARADC_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: 1: force PDAC_CLK to high*/\r
+#define SARADC_DAC_CLK_FORCE_HIGH (BIT(24))\r
+#define SARADC_DAC_CLK_FORCE_HIGH_M (BIT(24))\r
+#define SARADC_DAC_CLK_FORCE_HIGH_V 0x1\r
+#define SARADC_DAC_CLK_FORCE_HIGH_S 24\r
+/* SARADC_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: 1: force PDAC_CLK to low*/\r
+#define SARADC_DAC_CLK_FORCE_LOW (BIT(23))\r
+#define SARADC_DAC_CLK_FORCE_LOW_M (BIT(23))\r
+#define SARADC_DAC_CLK_FORCE_LOW_V 0x1\r
+#define SARADC_DAC_CLK_FORCE_LOW_S 23\r
+/* SARADC_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA*/\r
+#define SARADC_DAC_DIG_FORCE (BIT(22))\r
+#define SARADC_DAC_DIG_FORCE_M (BIT(22))\r
+#define SARADC_DAC_DIG_FORCE_V 0x1\r
+#define SARADC_DAC_DIG_FORCE_S 22\r
+/* SARADC_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */\r
+/*description: */\r
+#define SARADC_DEBUG_BIT_SEL 0x0000001F\r
+#define SARADC_DEBUG_BIT_SEL_M ((SARADC_DEBUG_BIT_SEL_V)<<(SARADC_DEBUG_BIT_SEL_S))\r
+#define SARADC_DEBUG_BIT_SEL_V 0x1F\r
+#define SARADC_DEBUG_BIT_SEL_S 17\r
+/* SARADC_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: 1: enable CW generator 0: disable CW generator*/\r
+#define SARADC_SW_TONE_EN (BIT(16))\r
+#define SARADC_SW_TONE_EN_M (BIT(16))\r
+#define SARADC_SW_TONE_EN_V 0x1\r
+#define SARADC_SW_TONE_EN_S 16\r
+/* SARADC_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */\r
+/*description: frequency step for CW generator can be used to adjust the frequency*/\r
+#define SARADC_SW_FSTEP 0x0000FFFF\r
+#define SARADC_SW_FSTEP_M ((SARADC_SW_FSTEP_V)<<(SARADC_SW_FSTEP_S))\r
+#define SARADC_SW_FSTEP_V 0xFFFF\r
+#define SARADC_SW_FSTEP_S 0\r
+\r
+#define SARADC_SAR_DAC_CTRL2_REG (DR_REG_SARADC_BASE + 0x009c)\r
+/* SARADC_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */\r
+/*description: 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to\r
+ select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/\r
+#define SARADC_DAC_CW_EN2 (BIT(25))\r
+#define SARADC_DAC_CW_EN2_M (BIT(25))\r
+#define SARADC_DAC_CW_EN2_V 0x1\r
+#define SARADC_DAC_CW_EN2_S 25\r
+/* SARADC_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
+/*description: 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to\r
+ select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/\r
+#define SARADC_DAC_CW_EN1 (BIT(24))\r
+#define SARADC_DAC_CW_EN1_M (BIT(24))\r
+#define SARADC_DAC_CW_EN1_V 0x1\r
+#define SARADC_DAC_CW_EN1_S 24\r
+/* SARADC_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */\r
+/*description: 00: do not invert any bits 01: invert all bits 10: invert MSB\r
+ 11: invert all bits except MSB*/\r
+#define SARADC_DAC_INV2 0x00000003\r
+#define SARADC_DAC_INV2_M ((SARADC_DAC_INV2_V)<<(SARADC_DAC_INV2_S))\r
+#define SARADC_DAC_INV2_V 0x3\r
+#define SARADC_DAC_INV2_S 22\r
+/* SARADC_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */\r
+/*description: 00: do not invert any bits 01: invert all bits 10: invert MSB\r
+ 11: invert all bits except MSB*/\r
+#define SARADC_DAC_INV1 0x00000003\r
+#define SARADC_DAC_INV1_M ((SARADC_DAC_INV1_V)<<(SARADC_DAC_INV1_S))\r
+#define SARADC_DAC_INV1_V 0x3\r
+#define SARADC_DAC_INV1_S 20\r
+/* SARADC_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */\r
+/*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/\r
+#define SARADC_DAC_SCALE2 0x00000003\r
+#define SARADC_DAC_SCALE2_M ((SARADC_DAC_SCALE2_V)<<(SARADC_DAC_SCALE2_S))\r
+#define SARADC_DAC_SCALE2_V 0x3\r
+#define SARADC_DAC_SCALE2_S 18\r
+/* SARADC_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */\r
+/*description: 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8*/\r
+#define SARADC_DAC_SCALE1 0x00000003\r
+#define SARADC_DAC_SCALE1_M ((SARADC_DAC_SCALE1_V)<<(SARADC_DAC_SCALE1_S))\r
+#define SARADC_DAC_SCALE1_V 0x3\r
+#define SARADC_DAC_SCALE1_S 16\r
+/* SARADC_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */\r
+/*description: DC offset for DAC2 CW generator*/\r
+#define SARADC_DAC_DC2 0x000000FF\r
+#define SARADC_DAC_DC2_M ((SARADC_DAC_DC2_V)<<(SARADC_DAC_DC2_S))\r
+#define SARADC_DAC_DC2_V 0xFF\r
+#define SARADC_DAC_DC2_S 8\r
+/* SARADC_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */\r
+/*description: DC offset for DAC1 CW generator*/\r
+#define SARADC_DAC_DC1 0x000000FF\r
+#define SARADC_DAC_DC1_M ((SARADC_DAC_DC1_V)<<(SARADC_DAC_DC1_S))\r
+#define SARADC_DAC_DC1_V 0xFF\r
+#define SARADC_DAC_DC1_S 0\r
+\r
+#define SARADC_SAR_MEAS_CTRL2_REG (DR_REG_SARADC_BASE + 0x0a0)\r
+/* SARADC_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */\r
+/*description: */\r
+#define SARADC_AMP_SHORT_REF_GND_FORCE 0x00000003\r
+#define SARADC_AMP_SHORT_REF_GND_FORCE_M ((SARADC_AMP_SHORT_REF_GND_FORCE_V)<<(SARADC_AMP_SHORT_REF_GND_FORCE_S))\r
+#define SARADC_AMP_SHORT_REF_GND_FORCE_V 0x3\r
+#define SARADC_AMP_SHORT_REF_GND_FORCE_S 17\r
+/* SARADC_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */\r
+/*description: */\r
+#define SARADC_AMP_SHORT_REF_FORCE 0x00000003\r
+#define SARADC_AMP_SHORT_REF_FORCE_M ((SARADC_AMP_SHORT_REF_FORCE_V)<<(SARADC_AMP_SHORT_REF_FORCE_S))\r
+#define SARADC_AMP_SHORT_REF_FORCE_V 0x3\r
+#define SARADC_AMP_SHORT_REF_FORCE_S 15\r
+/* SARADC_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */\r
+/*description: */\r
+#define SARADC_AMP_RST_FB_FORCE 0x00000003\r
+#define SARADC_AMP_RST_FB_FORCE_M ((SARADC_AMP_RST_FB_FORCE_V)<<(SARADC_AMP_RST_FB_FORCE_S))\r
+#define SARADC_AMP_RST_FB_FORCE_V 0x3\r
+#define SARADC_AMP_RST_FB_FORCE_S 13\r
+/* SARADC_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */\r
+/*description: */\r
+#define SARADC_SAR2_RSTB_FORCE 0x00000003\r
+#define SARADC_SAR2_RSTB_FORCE_M ((SARADC_SAR2_RSTB_FORCE_V)<<(SARADC_SAR2_RSTB_FORCE_S))\r
+#define SARADC_SAR2_RSTB_FORCE_V 0x3\r
+#define SARADC_SAR2_RSTB_FORCE_S 11\r
+/* SARADC_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_SAR_RSTB_FSM_IDLE (BIT(10))\r
+#define SARADC_SAR_RSTB_FSM_IDLE_M (BIT(10))\r
+#define SARADC_SAR_RSTB_FSM_IDLE_V 0x1\r
+#define SARADC_SAR_RSTB_FSM_IDLE_S 10\r
+/* SARADC_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_XPD_SAR_FSM_IDLE (BIT(9))\r
+#define SARADC_XPD_SAR_FSM_IDLE_M (BIT(9))\r
+#define SARADC_XPD_SAR_FSM_IDLE_V 0x1\r
+#define SARADC_XPD_SAR_FSM_IDLE_S 9\r
+/* SARADC_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE (BIT(8))\r
+#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(8))\r
+#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1\r
+#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_S 8\r
+/* SARADC_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_AMP_SHORT_REF_FSM_IDLE (BIT(7))\r
+#define SARADC_AMP_SHORT_REF_FSM_IDLE_M (BIT(7))\r
+#define SARADC_AMP_SHORT_REF_FSM_IDLE_V 0x1\r
+#define SARADC_AMP_SHORT_REF_FSM_IDLE_S 7\r
+/* SARADC_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_AMP_RST_FB_FSM_IDLE (BIT(6))\r
+#define SARADC_AMP_RST_FB_FSM_IDLE_M (BIT(6))\r
+#define SARADC_AMP_RST_FB_FSM_IDLE_V 0x1\r
+#define SARADC_AMP_RST_FB_FSM_IDLE_S 6\r
+/* SARADC_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_XPD_SAR_AMP_FSM_IDLE (BIT(5))\r
+#define SARADC_XPD_SAR_AMP_FSM_IDLE_M (BIT(5))\r
+#define SARADC_XPD_SAR_AMP_FSM_IDLE_V 0x1\r
+#define SARADC_XPD_SAR_AMP_FSM_IDLE_S 5\r
+/* SARADC_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: */\r
+#define SARADC_SAR1_DAC_XPD_FSM_IDLE (BIT(4))\r
+#define SARADC_SAR1_DAC_XPD_FSM_IDLE_M (BIT(4))\r
+#define SARADC_SAR1_DAC_XPD_FSM_IDLE_V 0x1\r
+#define SARADC_SAR1_DAC_XPD_FSM_IDLE_S 4\r
+/* SARADC_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */\r
+/*description: */\r
+#define SARADC_SAR1_DAC_XPD_FSM 0x0000000F\r
+#define SARADC_SAR1_DAC_XPD_FSM_M ((SARADC_SAR1_DAC_XPD_FSM_V)<<(SARADC_SAR1_DAC_XPD_FSM_S))\r
+#define SARADC_SAR1_DAC_XPD_FSM_V 0xF\r
+#define SARADC_SAR1_DAC_XPD_FSM_S 0\r
+\r
+#define SARADC_SAR_NOUSE_REG (DR_REG_SARADC_BASE + 0x00F8)\r
+/* SARADC_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: */\r
+#define SARADC_SAR_NOUSE 0xFFFFFFFF\r
+#define SARADC_SAR_NOUSE_M ((SARADC_SAR_NOUSE_V)<<(SARADC_SAR_NOUSE_S))\r
+#define SARADC_SAR_NOUSE_V 0xFFFFFFFF\r
+#define SARADC_SAR_NOUSE_S 0\r
+\r
+#define SARADC_SARDATE_REG (DR_REG_SARADC_BASE + 0x00FC)\r
+/* SARADC_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605180 ; */\r
+/*description: */\r
+#define SARADC_SAR_DATE 0x0FFFFFFF\r
+#define SARADC_SAR_DATE_M ((SARADC_SAR_DATE_V)<<(SARADC_SAR_DATE_S))\r
+#define SARADC_SAR_DATE_V 0xFFFFFFF\r
+#define SARADC_SAR_DATE_S 0\r
+\r
+\r
+\r
+\r
+#endif /*_SOC_SARADC_REG_H_ */\r
+\r
+\r
#define BIT0 0x00000001
//}}
+#define PRO_CPU_NUM (0)
+#define APP_CPU_NUM (1)
+
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
//}}
#define DR_REG_DPORT_BASE 0x3ff00000
-#define DR_REG_UART_BASE 0x3ff40000
-#define DR_REG_SPI1_BASE 0x3ff42000
-#define DR_REG_SPI0_BASE 0x3ff43000
-#define DR_REG_GPIO_BASE 0x3ff44000
-#define DR_REG_FE2_BASE 0x3ff45000
-#define DR_REG_FE_BASE 0x3ff46000
-#define DR_REG_TIMER_BASE 0x3ff47000
-#define DR_REG_RTCCNTL_BASE 0x3ff48000
-#define DR_REG_RTCIO_BASE 0x3ff48400
-
-#define DR_REG_RTCMEM0_BASE 0x3ff61000
-#define DR_REG_RTCMEM1_BASE 0x3ff62000
-#define DR_REG_RTCMEM2_BASE 0x3ff63000
-
-#define DR_REG_IO_MUX_BASE 0x3ff49000
-#define DR_REG_WDG_BASE 0x3ff4A000
-#define DR_REG_HINF_BASE 0x3ff4B000
-#define DR_REG_UHCI1_BASE 0x3ff4C000
-#define DR_REG_I2C_BASE 0x3ff4E000
-#define DR_REG_I2S_BASE 0x3ff4F000
-#define DR_REG_I2S1_BASE 0x3ff6D000
-#define DR_REG_UART1_BASE 0x3ff50000
-#define DR_REG_BT_BASE 0x3ff51000
-#define DR_REG_I2C_EXT_BASE 0x3ff53000
-#define DR_REG_UHCI0_BASE 0x3ff54000
-#define DR_REG_SLCHOST_BASE 0x3ff55000
-#define DR_REG_RMT_BASE 0x3ff56000
-#define DR_REG_PCNT_BASE 0x3ff57000
-#define DR_REG_SLC_BASE 0x3ff58000
-#define DR_REG_LEDC_BASE 0x3ff59000
-#define DR_REG_EFUSE_BASE 0x3ff5A000
-#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
-#define DR_REG_BB_BASE 0x3ff5C000
-#define DR_REG_PWM_BASE 0x3ff5E000
-#define DR_REG_TIMERS_BASE(i) (0x3ff5F000 + i * (0x1000))
-#define DR_REG_GPIO_SD_BASE 0x3ff44f00
-
-//}}
-#define REG_SPI_BASE(i) (DR_REG_SPI0_BASE - i*(0x1000))
-#define PERIPHS_TIMER_BASEDDR DR_REG_TIMER_BASE
+#define DR_REG_UART_BASE 0x3ff40000
+#define DR_REG_SPI1_BASE 0x3ff42000
+#define DR_REG_SPI0_BASE 0x3ff43000
+#define DR_REG_GPIO_BASE 0x3ff44000
+#define DR_REG_GPIO_SD_BASE 0x3ff44f00
+#define DR_REG_FE2_BASE 0x3ff45000
+#define DR_REG_FE_BASE 0x3ff46000
+#define DR_REG_RTCCNTL_BASE 0x3ff48000
+#define DR_REG_RTCIO_BASE 0x3ff48400
+#define DR_REG_SARADC_BASE 0x3ff48800
+#define DR_REG_IO_MUX_BASE 0x3ff49000
+#define DR_REG_RTCMEM0_BASE 0x3ff61000
+#define DR_REG_RTCMEM1_BASE 0x3ff62000
+#define DR_REG_RTCMEM2_BASE 0x3ff63000
+#define DR_REG_HINF_BASE 0x3ff4B000
+#define DR_REG_UHCI1_BASE 0x3ff4C000
+#define DR_REG_I2S_BASE 0x3ff4F000
+#define DR_REG_UART1_BASE 0x3ff50000
+#define DR_REG_BT_BASE 0x3ff51000
+#define DR_REG_I2C_EXT_BASE 0x3ff53000
+#define DR_REG_UHCI0_BASE 0x3ff54000
+#define DR_REG_SLCHOST_BASE 0x3ff55000
+#define DR_REG_RMT_BASE 0x3ff56000
+#define DR_REG_PCNT_BASE 0x3ff57000
+#define DR_REG_SLC_BASE 0x3ff58000
+#define DR_REG_LEDC_BASE 0x3ff59000
+#define DR_REG_EFUSE_BASE 0x3ff5A000
+#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
+#define DR_REG_PWM_BASE 0x3ff5E000
+#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
+#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
+#define DR_REG_SPI2_BASE 0x3ff64000
+#define DR_REG_SPI3_BASE 0x3ff65000
+#define DR_REG_I2C1_EXT_BASE 0x3ff67000
+#define DR_REG_SDMMC_BASE 0x3ff68000
+#define DR_REG_EMAC_BASE 0x3ff69000
+#define DR_REG_PWM1_BASE 0x3ff6C000
+#define DR_REG_I2S1_BASE 0x3ff6D000
+#define DR_REG_UART2_BASE 0x3ff6E000
+#define DR_REG_PWM2_BASE 0x3ff6F000
+#define DR_REG_PWM3_BASE 0x3ff70000
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
//Interrupt hardware source table
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
-
+//Other interrupt number should be managed by the user
#endif /* _ESP32_SOC_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef __SPI_REG_H__\r
+#define __SPI_REG_H__\r
+\r
+\r
+#include "soc.h"\r
+#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 )))\r
+\r
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)\r
+/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: Read flash enable. Read flash operation will be triggered when\r
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/\r
+#define SPI_FLASH_READ (BIT(31))\r
+#define SPI_FLASH_READ_M (BIT(31))\r
+#define SPI_FLASH_READ_V 0x1\r
+#define SPI_FLASH_READ_S 31\r
+/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: Write flash enable. Write enable command will be sent when the\r
+ bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/\r
+#define SPI_FLASH_WREN (BIT(30))\r
+#define SPI_FLASH_WREN_M (BIT(30))\r
+#define SPI_FLASH_WREN_V 0x1\r
+#define SPI_FLASH_WREN_S 30\r
+/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: Write flash disable. Write disable command will be sent when\r
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/\r
+#define SPI_FLASH_WRDI (BIT(29))\r
+#define SPI_FLASH_WRDI_M (BIT(29))\r
+#define SPI_FLASH_WRDI_V 0x1\r
+#define SPI_FLASH_WRDI_S 29\r
+/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is\r
+ set. The bit will be cleared once the operation done. 1: enable 0: disable.*/\r
+#define SPI_FLASH_RDID (BIT(28))\r
+#define SPI_FLASH_RDID_M (BIT(28))\r
+#define SPI_FLASH_RDID_V 0x1\r
+#define SPI_FLASH_RDID_S 28\r
+/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: Read status register-1. Read status operation will be triggered\r
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_RDSR (BIT(27))\r
+#define SPI_FLASH_RDSR_M (BIT(27))\r
+#define SPI_FLASH_RDSR_V 0x1\r
+#define SPI_FLASH_RDSR_S 27\r
+/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: Write status register enable. Write status operation will\r
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_WRSR (BIT(26))\r
+#define SPI_FLASH_WRSR_M (BIT(26))\r
+#define SPI_FLASH_WRSR_V 0x1\r
+#define SPI_FLASH_WRSR_S 26\r
+/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: Page program enable(1 byte ~256 bytes data to be programmed).\r
+ Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/\r
+#define SPI_FLASH_PP (BIT(25))\r
+#define SPI_FLASH_PP_M (BIT(25))\r
+#define SPI_FLASH_PP_V 0x1\r
+#define SPI_FLASH_PP_S 25\r
+/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered\r
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_SE (BIT(24))\r
+#define SPI_FLASH_SE_M (BIT(24))\r
+#define SPI_FLASH_SE_V 0x1\r
+#define SPI_FLASH_SE_S 24\r
+/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: Block erase enable(32KB) . Block erase operation will be triggered\r
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_BE (BIT(23))\r
+#define SPI_FLASH_BE_M (BIT(23))\r
+#define SPI_FLASH_BE_V 0x1\r
+#define SPI_FLASH_BE_S 23\r
+/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: Chip erase enable. Chip erase operation will be triggered when\r
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_CE (BIT(22))\r
+#define SPI_FLASH_CE_M (BIT(22))\r
+#define SPI_FLASH_CE_V 0x1\r
+#define SPI_FLASH_CE_S 22\r
+/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: Drive Flash into power down. An operation will be triggered\r
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_DP (BIT(21))\r
+#define SPI_FLASH_DP_M (BIT(21))\r
+#define SPI_FLASH_DP_V 0x1\r
+#define SPI_FLASH_DP_S 21\r
+/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: This bit combined with reg_resandres bit releases Flash from\r
+ the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_RES (BIT(20))\r
+#define SPI_FLASH_RES_M (BIT(20))\r
+#define SPI_FLASH_RES_V 0x1\r
+#define SPI_FLASH_RES_S 20\r
+/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: Drive Flash into high performance mode. The bit will be cleared\r
+ once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_HPM (BIT(19))\r
+#define SPI_FLASH_HPM_M (BIT(19))\r
+#define SPI_FLASH_HPM_V 0x1\r
+#define SPI_FLASH_HPM_S 19\r
+/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: User define command enable. An operation will be triggered when\r
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_USR (BIT(18))\r
+#define SPI_USR_M (BIT(18))\r
+#define SPI_USR_V 0x1\r
+#define SPI_USR_S 18\r
+/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: program erase suspend bit program erase suspend operation will\r
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_PES (BIT(17))\r
+#define SPI_FLASH_PES_M (BIT(17))\r
+#define SPI_FLASH_PES_V 0x1\r
+#define SPI_FLASH_PES_S 17\r
+/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: program erase resume bit program erase suspend operation will\r
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/\r
+#define SPI_FLASH_PER (BIT(16))\r
+#define SPI_FLASH_PER_M (BIT(16))\r
+#define SPI_FLASH_PER_V 0x1\r
+#define SPI_FLASH_PER_S 16\r
+\r
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)\r
+/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */\r
+/*description: [31:8]:address to slave [7:0]:Reserved.*/\r
+#define SPI_USR_ADDR_VALUE 0xFFFFFFFF\r
+#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))\r
+#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF\r
+#define SPI_USR_ADDR_VALUE_S 0\r
+\r
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)\r
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/\r
+#define SPI_WR_BIT_ORDER (BIT(26))\r
+#define SPI_WR_BIT_ORDER_M (BIT(26))\r
+#define SPI_WR_BIT_ORDER_V 0x1\r
+#define SPI_WR_BIT_ORDER_S 26\r
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/\r
+#define SPI_RD_BIT_ORDER (BIT(25))\r
+#define SPI_RD_BIT_ORDER_M (BIT(25))\r
+#define SPI_RD_BIT_ORDER_V 0x1\r
+#define SPI_RD_BIT_ORDER_S 25\r
+/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: In the read operations address phase and read-data phase apply\r
+ 4 signals. 1: enable 0: disable.*/\r
+#define SPI_FREAD_QIO (BIT(24))\r
+#define SPI_FREAD_QIO_M (BIT(24))\r
+#define SPI_FREAD_QIO_V 0x1\r
+#define SPI_FREAD_QIO_S 24\r
+/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: In the read operations address phase and read-data phase apply\r
+ 2 signals. 1: enable 0: disable.*/\r
+#define SPI_FREAD_DIO (BIT(23))\r
+#define SPI_FREAD_DIO_M (BIT(23))\r
+#define SPI_FREAD_DIO_V 0x1\r
+#define SPI_FREAD_DIO_S 23\r
+/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: two bytes data will be written to status register when it is\r
+ set. 1: enable 0: disable.*/\r
+#define SPI_WRSR_2B (BIT(22))\r
+#define SPI_WRSR_2B_M (BIT(22))\r
+#define SPI_WRSR_2B_V 0x1\r
+#define SPI_WRSR_2B_S 22\r
+/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */\r
+/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/\r
+#define SPI_WP_REG (BIT(21))\r
+#define SPI_WP_REG_M (BIT(21))\r
+#define SPI_WP_REG_V 0x1\r
+#define SPI_WP_REG_S 21\r
+/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/\r
+#define SPI_FREAD_QUAD (BIT(20))\r
+#define SPI_FREAD_QUAD_M (BIT(20))\r
+#define SPI_FREAD_QUAD_V 0x1\r
+#define SPI_FREAD_QUAD_S 20\r
+/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */\r
+/*description: The Device ID is read out to SPI_RD_STATUS register£¬ this bit\r
+ combine with spi_flash_res bit. 1: enable 0: disable.*/\r
+#define SPI_RESANDRES (BIT(15))\r
+#define SPI_RESANDRES_M (BIT(15))\r
+#define SPI_RESANDRES_V 0x1\r
+#define SPI_RESANDRES_S 15\r
+/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/\r
+#define SPI_FREAD_DUAL (BIT(14))\r
+#define SPI_FREAD_DUAL_M (BIT(14))\r
+#define SPI_FREAD_DUAL_V 0x1\r
+#define SPI_FREAD_DUAL_S 14\r
+/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
+/*description: This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout\r
+ and spi_fread_dout. 1: enable 0: disable.*/\r
+#define SPI_FASTRD_MODE (BIT(13))\r
+#define SPI_FASTRD_MODE_M (BIT(13))\r
+#define SPI_FASTRD_MODE_V 0x1\r
+#define SPI_FASTRD_MODE_S 13\r
+/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/\r
+#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))\r
+#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12))\r
+#define SPI_WAIT_FLASH_IDLE_EN_V 0x1\r
+#define SPI_WAIT_FLASH_IDLE_EN_S 12\r
+/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: For SPI1 enable crc32 when writing encrypted data to flash.\r
+ 1: enable 0:disable*/\r
+#define SPI_TX_CRC_EN (BIT(11))\r
+#define SPI_TX_CRC_EN_M (BIT(11))\r
+#define SPI_TX_CRC_EN_V 0x1\r
+#define SPI_TX_CRC_EN_S 11\r
+/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */\r
+/*description: For SPI1 initialize crc32 module before writing encrypted data\r
+ to flash. Active low.*/\r
+#define SPI_FCS_CRC_EN (BIT(10))\r
+#define SPI_FCS_CRC_EN_M (BIT(10))\r
+#define SPI_FCS_CRC_EN_V 0x1\r
+#define SPI_FCS_CRC_EN_S 10\r
+\r
+#define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC)\r
+/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */\r
+/*description: SPI cs signal is delayed by spi clock cycles*/\r
+#define SPI_CS_HOLD_DELAY 0x0000000F\r
+#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S))\r
+#define SPI_CS_HOLD_DELAY_V 0xF\r
+#define SPI_CS_HOLD_DELAY_S 28\r
+/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */\r
+/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/\r
+#define SPI_CS_HOLD_DELAY_RES 0x00000FFF\r
+#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S))\r
+#define SPI_CS_HOLD_DELAY_RES_V 0xFFF\r
+#define SPI_CS_HOLD_DELAY_RES_S 16\r
+\r
+#define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10)\r
+/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */\r
+/*description: In the slave mode£¬it is the status for master to read out.*/\r
+#define SPI_STATUS_EXT 0x000000FF\r
+#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S))\r
+#define SPI_STATUS_EXT_V 0xFF\r
+#define SPI_STATUS_EXT_S 24\r
+/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */\r
+/*description: Mode bits in the flash fast read mode£¬ it is combined with spi_fastrd_mode bit.*/\r
+#define SPI_WB_MODE 0x000000FF\r
+#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S))\r
+#define SPI_WB_MODE_V 0xFF\r
+#define SPI_WB_MODE_S 16\r
+/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */\r
+/*description: In the slave mode£¬ it is the status for master to read out.*/\r
+#define SPI_STATUS 0x0000FFFF\r
+#define SPI_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S))\r
+#define SPI_STATUS_V 0xFFFF\r
+#define SPI_STATUS_S 0\r
+\r
+#define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14)\r
+/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */\r
+/*description: spi_cs signal is delayed by system clock cycles*/\r
+#define SPI_CS_DELAY_NUM 0x0000000F\r
+#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S))\r
+#define SPI_CS_DELAY_NUM_V 0xF\r
+#define SPI_CS_DELAY_NUM_S 28\r
+/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */\r
+/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge\r
+ or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/\r
+#define SPI_CS_DELAY_MODE 0x00000003\r
+#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S))\r
+#define SPI_CS_DELAY_MODE_V 0x3\r
+#define SPI_CS_DELAY_MODE_S 26\r
+/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */\r
+/*description: MOSI signals are delayed by system clock cycles*/\r
+#define SPI_MOSI_DELAY_NUM 0x00000007\r
+#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S))\r
+#define SPI_MOSI_DELAY_NUM_V 0x7\r
+#define SPI_MOSI_DELAY_NUM_S 23\r
+/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */\r
+/*description: MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge\r
+ or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/\r
+#define SPI_MOSI_DELAY_MODE 0x00000003\r
+#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S))\r
+#define SPI_MOSI_DELAY_MODE_V 0x3\r
+#define SPI_MOSI_DELAY_MODE_S 21\r
+/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */\r
+/*description: MISO signals are delayed by system clock cycles*/\r
+#define SPI_MISO_DELAY_NUM 0x00000007\r
+#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S))\r
+#define SPI_MISO_DELAY_NUM_V 0x7\r
+#define SPI_MISO_DELAY_NUM_S 18\r
+/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */\r
+/*description: MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge\r
+ or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/\r
+#define SPI_MISO_DELAY_MODE 0x00000003\r
+#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S))\r
+#define SPI_MISO_DELAY_MODE_V 0x3\r
+#define SPI_MISO_DELAY_MODE_S 16\r
+/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */\r
+/*description: modify spi clock duty ratio when the value is lager than 8£¬\r
+ the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/\r
+#define SPI_CK_OUT_HIGH_MODE 0x0000000F\r
+#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S))\r
+#define SPI_CK_OUT_HIGH_MODE_V 0xF\r
+#define SPI_CK_OUT_HIGH_MODE_S 12\r
+/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */\r
+/*description: modify spi clock duty ratio when the value is lager than 8£¬\r
+ the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/\r
+#define SPI_CK_OUT_LOW_MODE 0x0000000F\r
+#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S))\r
+#define SPI_CK_OUT_LOW_MODE_V 0xF\r
+#define SPI_CK_OUT_LOW_MODE_S 8\r
+/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */\r
+/*description: delay cycles of cs pin by spi clock£¬ this bits combined with spi_cs_hold bit.*/\r
+#define SPI_HOLD_TIME 0x0000000F\r
+#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S))\r
+#define SPI_HOLD_TIME_V 0xF\r
+#define SPI_HOLD_TIME_S 4\r
+/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */\r
+/*description: (cycles-1) of ¡°prepare¡± phase by spi clock£¬ this bits combined\r
+ with spi_cs_setup bit.*/\r
+#define SPI_SETUP_TIME 0x0000000F\r
+#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S))\r
+#define SPI_SETUP_TIME_V 0xF\r
+#define SPI_SETUP_TIME_S 0\r
+\r
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18)\r
+/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */\r
+/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is\r
+ divided from system clock.*/\r
+#define SPI_CLK_EQU_SYSCLK (BIT(31))\r
+#define SPI_CLK_EQU_SYSCLK_M (BIT(31))\r
+#define SPI_CLK_EQU_SYSCLK_V 0x1\r
+#define SPI_CLK_EQU_SYSCLK_S 31\r
+/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */\r
+/*description: In the master mode it is pre-divider of spi_clk.*/\r
+#define SPI_CLKDIV_PRE 0x00001FFF\r
+#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))\r
+#define SPI_CLKDIV_PRE_V 0x1FFF\r
+#define SPI_CLKDIV_PRE_S 18\r
+/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */\r
+/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency\r
+ is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/\r
+#define SPI_CLKCNT_N 0x0000003F\r
+#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))\r
+#define SPI_CLKCNT_N_V 0x3F\r
+#define SPI_CLKCNT_N_S 12\r
+/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */\r
+/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In\r
+ the slave mode it must be 0.*/\r
+#define SPI_CLKCNT_H 0x0000003F\r
+#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))\r
+#define SPI_CLKCNT_H_V 0x3F\r
+#define SPI_CLKCNT_H_S 6\r
+/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */\r
+/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave\r
+ mode it must be 0.*/\r
+#define SPI_CLKCNT_L 0x0000003F\r
+#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))\r
+#define SPI_CLKCNT_L_V 0x3F\r
+#define SPI_CLKCNT_L_S 0\r
+\r
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C)\r
+/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */\r
+/*description: This bit enable the command phase of an operation.*/\r
+#define SPI_USR_COMMAND (BIT(31))\r
+#define SPI_USR_COMMAND_M (BIT(31))\r
+#define SPI_USR_COMMAND_V 0x1\r
+#define SPI_USR_COMMAND_S 31\r
+/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: This bit enable the address phase of an operation.*/\r
+#define SPI_USR_ADDR (BIT(30))\r
+#define SPI_USR_ADDR_M (BIT(30))\r
+#define SPI_USR_ADDR_V 0x1\r
+#define SPI_USR_ADDR_S 30\r
+/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: This bit enable the dummy phase of an operation.*/\r
+#define SPI_USR_DUMMY (BIT(29))\r
+#define SPI_USR_DUMMY_M (BIT(29))\r
+#define SPI_USR_DUMMY_V 0x1\r
+#define SPI_USR_DUMMY_S 29\r
+/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: This bit enable the read-data phase of an operation.*/\r
+#define SPI_USR_MISO (BIT(28))\r
+#define SPI_USR_MISO_M (BIT(28))\r
+#define SPI_USR_MISO_V 0x1\r
+#define SPI_USR_MISO_S 28\r
+/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: This bit enable the write-data phase of an operation.*/\r
+#define SPI_USR_MOSI (BIT(27))\r
+#define SPI_USR_MOSI_M (BIT(27))\r
+#define SPI_USR_MOSI_V 0x1\r
+#define SPI_USR_MOSI_S 27\r
+/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: spi clock is disable in dummy phase when the bit is enable.*/\r
+#define SPI_USR_DUMMY_IDLE (BIT(26))\r
+#define SPI_USR_DUMMY_IDLE_M (BIT(26))\r
+#define SPI_USR_DUMMY_IDLE_V 0x1\r
+#define SPI_USR_DUMMY_IDLE_S 26\r
+/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
+/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15.\r
+ 1: enable 0: disable.*/\r
+#define SPI_USR_MOSI_HIGHPART (BIT(25))\r
+#define SPI_USR_MOSI_HIGHPART_M (BIT(25))\r
+#define SPI_USR_MOSI_HIGHPART_V 0x1\r
+#define SPI_USR_MOSI_HIGHPART_S 25\r
+/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
+/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15.\r
+ 1: enable 0: disable.*/\r
+#define SPI_USR_MISO_HIGHPART (BIT(24))\r
+#define SPI_USR_MISO_HIGHPART_M (BIT(24))\r
+#define SPI_USR_MISO_HIGHPART_V 0x1\r
+#define SPI_USR_MISO_HIGHPART_S 24\r
+/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/\r
+#define SPI_USR_PREP_HOLD (BIT(23))\r
+#define SPI_USR_PREP_HOLD_M (BIT(23))\r
+#define SPI_USR_PREP_HOLD_V 0x1\r
+#define SPI_USR_PREP_HOLD_S 23\r
+/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
+/*description: spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/\r
+#define SPI_USR_CMD_HOLD (BIT(22))\r
+#define SPI_USR_CMD_HOLD_M (BIT(22))\r
+#define SPI_USR_CMD_HOLD_V 0x1\r
+#define SPI_USR_CMD_HOLD_S 22\r
+/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */\r
+/*description: spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/\r
+#define SPI_USR_ADDR_HOLD (BIT(21))\r
+#define SPI_USR_ADDR_HOLD_M (BIT(21))\r
+#define SPI_USR_ADDR_HOLD_V 0x1\r
+#define SPI_USR_ADDR_HOLD_S 21\r
+/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/\r
+#define SPI_USR_DUMMY_HOLD (BIT(20))\r
+#define SPI_USR_DUMMY_HOLD_M (BIT(20))\r
+#define SPI_USR_DUMMY_HOLD_V 0x1\r
+#define SPI_USR_DUMMY_HOLD_S 20\r
+/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */\r
+/*description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/\r
+#define SPI_USR_DIN_HOLD (BIT(19))\r
+#define SPI_USR_DIN_HOLD_M (BIT(19))\r
+#define SPI_USR_DIN_HOLD_V 0x1\r
+#define SPI_USR_DIN_HOLD_S 19\r
+/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/\r
+#define SPI_USR_DOUT_HOLD (BIT(18))\r
+#define SPI_USR_DOUT_HOLD_M (BIT(18))\r
+#define SPI_USR_DOUT_HOLD_V 0x1\r
+#define SPI_USR_DOUT_HOLD_S 18\r
+/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: It is combined with hold bits to set the polarity of spi hold\r
+ line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/\r
+#define SPI_USR_HOLD_POL (BIT(17))\r
+#define SPI_USR_HOLD_POL_M (BIT(17))\r
+#define SPI_USR_HOLD_POL_V 0x1\r
+#define SPI_USR_HOLD_POL_S 17\r
+/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: Set the bit to enable 3-line half duplex communication mosi\r
+ and miso signals share the same pin. 1: enable 0: disable.*/\r
+#define SPI_SIO (BIT(16))\r
+#define SPI_SIO_M (BIT(16))\r
+#define SPI_SIO_V 0x1\r
+#define SPI_SIO_S 16\r
+/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: In the write operations address phase and read-data phase apply 4 signals.*/\r
+#define SPI_FWRITE_QIO (BIT(15))\r
+#define SPI_FWRITE_QIO_M (BIT(15))\r
+#define SPI_FWRITE_QIO_V 0x1\r
+#define SPI_FWRITE_QIO_S 15\r
+/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: In the write operations address phase and read-data phase apply 2 signals.*/\r
+#define SPI_FWRITE_DIO (BIT(14))\r
+#define SPI_FWRITE_DIO_M (BIT(14))\r
+#define SPI_FWRITE_DIO_V 0x1\r
+#define SPI_FWRITE_DIO_S 14\r
+/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: In the write operations read-data phase apply 4 signals*/\r
+#define SPI_FWRITE_QUAD (BIT(13))\r
+#define SPI_FWRITE_QUAD_M (BIT(13))\r
+#define SPI_FWRITE_QUAD_V 0x1\r
+#define SPI_FWRITE_QUAD_S 13\r
+/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: In the write operations read-data phase apply 2 signals*/\r
+#define SPI_FWRITE_DUAL (BIT(12))\r
+#define SPI_FWRITE_DUAL_M (BIT(12))\r
+#define SPI_FWRITE_DUAL_V 0x1\r
+#define SPI_FWRITE_DUAL_S 12\r
+/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/\r
+#define SPI_WR_BYTE_ORDER (BIT(11))\r
+#define SPI_WR_BYTE_ORDER_M (BIT(11))\r
+#define SPI_WR_BYTE_ORDER_V 0x1\r
+#define SPI_WR_BYTE_ORDER_S 11\r
+/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/\r
+#define SPI_RD_BYTE_ORDER (BIT(10))\r
+#define SPI_RD_BYTE_ORDER_M (BIT(10))\r
+#define SPI_RD_BYTE_ORDER_V 0x1\r
+#define SPI_RD_BYTE_ORDER_S 10\r
+/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/\r
+#define SPI_CK_OUT_EDGE (BIT(7))\r
+#define SPI_CK_OUT_EDGE_M (BIT(7))\r
+#define SPI_CK_OUT_EDGE_V 0x1\r
+#define SPI_CK_OUT_EDGE_S 7\r
+/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */\r
+/*description: In the slave mode the bit is same as spi_ck_out_edge in master\r
+ mode. It is combined with spi_miso_delay_mode bits.*/\r
+#define SPI_CK_I_EDGE (BIT(6))\r
+#define SPI_CK_I_EDGE_M (BIT(6))\r
+#define SPI_CK_I_EDGE_V 0x1\r
+#define SPI_CK_I_EDGE_S 6\r
+/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/\r
+#define SPI_CS_SETUP (BIT(5))\r
+#define SPI_CS_SETUP_M (BIT(5))\r
+#define SPI_CS_SETUP_V 0x1\r
+#define SPI_CS_SETUP_S 5\r
+/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/\r
+#define SPI_CS_HOLD (BIT(4))\r
+#define SPI_CS_HOLD_M (BIT(4))\r
+#define SPI_CS_HOLD_V 0x1\r
+#define SPI_CS_HOLD_S 4\r
+/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/\r
+#define SPI_DOUTDIN (BIT(0))\r
+#define SPI_DOUTDIN_M (BIT(0))\r
+#define SPI_DOUTDIN_V 0x1\r
+#define SPI_DOUTDIN_S 0\r
+\r
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20)\r
+/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */\r
+/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/\r
+#define SPI_USR_ADDR_BITLEN 0x0000003F\r
+#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))\r
+#define SPI_USR_ADDR_BITLEN_V 0x3F\r
+#define SPI_USR_ADDR_BITLEN_S 26\r
+/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */\r
+/*description: The length in spi_clk cycles of dummy phase. The register value\r
+ shall be (cycle_num-1).*/\r
+#define SPI_USR_DUMMY_CYCLELEN 0x000000FF\r
+#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))\r
+#define SPI_USR_DUMMY_CYCLELEN_V 0xFF\r
+#define SPI_USR_DUMMY_CYCLELEN_S 0\r
+\r
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x24)\r
+/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */\r
+/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/\r
+#define SPI_USR_COMMAND_BITLEN 0x0000000F\r
+#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))\r
+#define SPI_USR_COMMAND_BITLEN_V 0xF\r
+#define SPI_USR_COMMAND_BITLEN_S 28\r
+/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */\r
+/*description: The value of command.*/\r
+#define SPI_USR_COMMAND_VALUE 0x0000FFFF\r
+#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))\r
+#define SPI_USR_COMMAND_VALUE_V 0xFFFF\r
+#define SPI_USR_COMMAND_VALUE_S 0\r
+\r
+#define SPI_MOSI_DLEN_REG(i) (REG_SPI_BASE(i) + 0x28)\r
+/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */\r
+/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/\r
+#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF\r
+#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S))\r
+#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF\r
+#define SPI_USR_MOSI_DBITLEN_S 0\r
+\r
+#define SPI_MISO_DLEN_REG(i) (REG_SPI_BASE(i) + 0x2C)\r
+/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */\r
+/*description: The length in bits of read-data. The register value shall be (bit_num-1).*/\r
+#define SPI_USR_MISO_DBITLEN 0x00FFFFFF\r
+#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S))\r
+#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF\r
+#define SPI_USR_MISO_DBITLEN_S 0\r
+\r
+#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + 0x30)\r
+/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: In the slave mode this register are the status register for the\r
+ master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/\r
+#define SPI_SLV_WR_ST 0xFFFFFFFF\r
+#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S))\r
+#define SPI_SLV_WR_ST_V 0xFFFFFFFF\r
+#define SPI_SLV_WR_ST_S 0\r
+\r
+#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + 0x34)\r
+/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: spi cs line keep low when the bit is set.*/\r
+#define SPI_CS_KEEP_ACTIVE (BIT(30))\r
+#define SPI_CS_KEEP_ACTIVE_M (BIT(30))\r
+#define SPI_CS_KEEP_ACTIVE_V 0x1\r
+#define SPI_CS_KEEP_ACTIVE_S 30\r
+/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/\r
+#define SPI_CK_IDLE_EDGE (BIT(29))\r
+#define SPI_CK_IDLE_EDGE_M (BIT(29))\r
+#define SPI_CK_IDLE_EDGE_V 0x1\r
+#define SPI_CK_IDLE_EDGE_S 29\r
+/* SPI_MASTER_CK_SEL : R/W ;bitpos:[15:11] ;default: 5'b0 ; */\r
+/*description: In the master mode spi cs line is enable as spi clk it is combined\r
+ with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/\r
+#define SPI_MASTER_CK_SEL 0x0000001F\r
+#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S))\r
+#define SPI_MASTER_CK_SEL_V 0x1F\r
+#define SPI_MASTER_CK_SEL_S 11\r
+/* SPI_MASTER_CS_POL : R/W ;bitpos:[10:6] ;default: 5'b0 ; */\r
+/*description: In the master mode the bits are the polarity of spi cs line\r
+ the value is equivalent to spi_cs ^ spi_master_cs_pol.*/\r
+#define SPI_MASTER_CS_POL 0x0000001F\r
+#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))\r
+#define SPI_MASTER_CS_POL_V 0x1F\r
+#define SPI_MASTER_CS_POL_S 6\r
+/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: 1: spi clk out disable 0: spi clk out enable*/\r
+#define SPI_CK_DIS (BIT(5))\r
+#define SPI_CK_DIS_M (BIT(5))\r
+#define SPI_CK_DIS_V 0x1\r
+#define SPI_CK_DIS_S 5\r
+/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */\r
+/*description: SPI CS2 pin enable£¬ 1: disable CS2£¬ 0: spi_cs2 signal is from/to CS2 pin*/\r
+#define SPI_CS2_DIS (BIT(2))\r
+#define SPI_CS2_DIS_M (BIT(2))\r
+#define SPI_CS2_DIS_V 0x1\r
+#define SPI_CS2_DIS_S 2\r
+/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */\r
+/*description: SPI CS1 pin enable£¬ 1: disable CS1£¬ 0: spi_cs1 signal is from/to CS1 pin*/\r
+#define SPI_CS1_DIS (BIT(1))\r
+#define SPI_CS1_DIS_M (BIT(1))\r
+#define SPI_CS1_DIS_V 0x1\r
+#define SPI_CS1_DIS_S 1\r
+/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: SPI CS0 pin enable£¬ 1: disable CS0£¬ 0: spi_cs0 signal is from/to CS0 pin*/\r
+#define SPI_CS0_DIS (BIT(0))\r
+#define SPI_CS0_DIS_M (BIT(0))\r
+#define SPI_CS0_DIS_V 0x1\r
+#define SPI_CS0_DIS_S 0\r
+\r
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x38)\r
+/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: Software reset enable£¬ reset the spi clock line cs line and data lines.*/\r
+#define SPI_SYNC_RESET (BIT(31))\r
+#define SPI_SYNC_RESET_M (BIT(31))\r
+#define SPI_SYNC_RESET_V 0x1\r
+#define SPI_SYNC_RESET_S 31\r
+/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: 1: slave mode 0: master mode.*/\r
+#define SPI_SLAVE_MODE (BIT(30))\r
+#define SPI_SLAVE_MODE_M (BIT(30))\r
+#define SPI_SLAVE_MODE_V 0x1\r
+#define SPI_SLAVE_MODE_S 30\r
+/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: write and read buffer enable in the slave mode*/\r
+#define SPI_SLV_WR_RD_BUF_EN (BIT(29))\r
+#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29))\r
+#define SPI_SLV_WR_RD_BUF_EN_V 0x1\r
+#define SPI_SLV_WR_RD_BUF_EN_S 29\r
+/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: write and read status enable in the slave mode*/\r
+#define SPI_SLV_WR_RD_STA_EN (BIT(28))\r
+#define SPI_SLV_WR_RD_STA_EN_M (BIT(28))\r
+#define SPI_SLV_WR_RD_STA_EN_V 0x1\r
+#define SPI_SLV_WR_RD_STA_EN_S 28\r
+/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
+/*description: 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode\r
+ commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/\r
+#define SPI_SLV_CMD_DEFINE (BIT(27))\r
+#define SPI_SLV_CMD_DEFINE_M (BIT(27))\r
+#define SPI_SLV_CMD_DEFINE_V 0x1\r
+#define SPI_SLV_CMD_DEFINE_S 27\r
+/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */\r
+/*description: The operations counter in both the master mode and the slave\r
+ mode. 4: read-status*/\r
+#define SPI_TRANS_CNT 0x0000000F\r
+#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S))\r
+#define SPI_TRANS_CNT_V 0xF\r
+#define SPI_TRANS_CNT_S 23\r
+/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */\r
+/*description: In the slave mode it is the state of spi state machine.*/\r
+#define SPI_SLV_LAST_STATE 0x00000007\r
+#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S))\r
+#define SPI_SLV_LAST_STATE_V 0x7\r
+#define SPI_SLV_LAST_STATE_S 20\r
+/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */\r
+/*description: In the slave mode it is the value of command.*/\r
+#define SPI_SLV_LAST_COMMAND 0x00000007\r
+#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))\r
+#define SPI_SLV_LAST_COMMAND_V 0x7\r
+#define SPI_SLV_LAST_COMMAND_S 17\r
+/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */\r
+/*description: In the slave mode this bits used to synchronize the input spi\r
+ cs signal and eliminate spi cs jitter.*/\r
+#define SPI_CS_I_MODE 0x00000003\r
+#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S))\r
+#define SPI_CS_I_MODE_V 0x3\r
+#define SPI_CS_I_MODE_S 10\r
+/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */\r
+/*description: Interrupt enable bits for the below 5 sources*/\r
+#define SPI_INT_EN 0x0000001F\r
+#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S))\r
+#define SPI_INT_EN_V 0x1F\r
+#define SPI_INT_EN_S 5\r
+/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for the completion of any operation in\r
+ both the master mode and the slave mode.*/\r
+#define SPI_TRANS_DONE (BIT(4))\r
+#define SPI_TRANS_DONE_M (BIT(4))\r
+#define SPI_TRANS_DONE_V 0x1\r
+#define SPI_TRANS_DONE_S 4\r
+/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for the completion of write-status operation\r
+ in the slave mode.*/\r
+#define SPI_SLV_WR_STA_DONE (BIT(3))\r
+#define SPI_SLV_WR_STA_DONE_M (BIT(3))\r
+#define SPI_SLV_WR_STA_DONE_V 0x1\r
+#define SPI_SLV_WR_STA_DONE_S 3\r
+/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for the completion of read-status operation\r
+ in the slave mode.*/\r
+#define SPI_SLV_RD_STA_DONE (BIT(2))\r
+#define SPI_SLV_RD_STA_DONE_M (BIT(2))\r
+#define SPI_SLV_RD_STA_DONE_V 0x1\r
+#define SPI_SLV_RD_STA_DONE_S 2\r
+/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for the completion of write-buffer operation\r
+ in the slave mode.*/\r
+#define SPI_SLV_WR_BUF_DONE (BIT(1))\r
+#define SPI_SLV_WR_BUF_DONE_M (BIT(1))\r
+#define SPI_SLV_WR_BUF_DONE_V 0x1\r
+#define SPI_SLV_WR_BUF_DONE_S 1\r
+/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The interrupt raw bit for the completion of read-buffer operation\r
+ in the slave mode.*/\r
+#define SPI_SLV_RD_BUF_DONE (BIT(0))\r
+#define SPI_SLV_RD_BUF_DONE_M (BIT(0))\r
+#define SPI_SLV_RD_BUF_DONE_V 0x1\r
+#define SPI_SLV_RD_BUF_DONE_S 0\r
+\r
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x3C)\r
+/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */\r
+/*description: In the slave mode it is the length of status bit.*/\r
+#define SPI_SLV_STATUS_BITLEN 0x0000001F\r
+#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S))\r
+#define SPI_SLV_STATUS_BITLEN_V 0x1F\r
+#define SPI_SLV_STATUS_BITLEN_S 27\r
+/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: In the slave mode enable fast read status.*/\r
+#define SPI_SLV_STATUS_FAST_EN (BIT(26))\r
+#define SPI_SLV_STATUS_FAST_EN_M (BIT(26))\r
+#define SPI_SLV_STATUS_FAST_EN_V 0x1\r
+#define SPI_SLV_STATUS_FAST_EN_S 26\r
+/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */\r
+/*description: In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read\r
+ register of SPI_RD_STATUS.*/\r
+#define SPI_SLV_STATUS_READBACK (BIT(25))\r
+#define SPI_SLV_STATUS_READBACK_M (BIT(25))\r
+#define SPI_SLV_STATUS_READBACK_V 0x1\r
+#define SPI_SLV_STATUS_READBACK_S 25\r
+/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */\r
+/*description: In the slave mode it is the address length in bits for read-buffer\r
+ operation. The register value shall be (bit_num-1).*/\r
+#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F\r
+#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S))\r
+#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F\r
+#define SPI_SLV_RD_ADDR_BITLEN_S 10\r
+/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */\r
+/*description: In the slave mode it is the address length in bits for write-buffer\r
+ operation. The register value shall be (bit_num-1).*/\r
+#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F\r
+#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S))\r
+#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F\r
+#define SPI_SLV_WR_ADDR_BITLEN_S 4\r
+/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: In the slave mode it is the enable bit of dummy phase for write-status\r
+ operations.*/\r
+#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))\r
+#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3))\r
+#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1\r
+#define SPI_SLV_WRSTA_DUMMY_EN_S 3\r
+/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: In the slave mode it is the enable bit of dummy phase for read-status\r
+ operations.*/\r
+#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))\r
+#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2))\r
+#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1\r
+#define SPI_SLV_RDSTA_DUMMY_EN_S 2\r
+/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: In the slave mode it is the enable bit of dummy phase for write-buffer\r
+ operations.*/\r
+#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))\r
+#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1))\r
+#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1\r
+#define SPI_SLV_WRBUF_DUMMY_EN_S 1\r
+/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: In the slave mode it is the enable bit of dummy phase for read-buffer\r
+ operations.*/\r
+#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))\r
+#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0))\r
+#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1\r
+#define SPI_SLV_RDBUF_DUMMY_EN_S 0\r
+\r
+#define SPI_SLAVE2_REG(i) (REG_SPI_BASE(i) + 0x40)\r
+/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */\r
+/*description: In the slave mode it is the length in spi_clk cycles of dummy\r
+ phase for write-buffer operations. The register value shall be (cycle_num-1).*/\r
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF\r
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S))\r
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF\r
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24\r
+/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */\r
+/*description: In the slave mode it is the length in spi_clk cycles of dummy\r
+ phase for read-buffer operations. The register value shall be (cycle_num-1).*/\r
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF\r
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S))\r
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF\r
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16\r
+/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */\r
+/*description: In the slave mode it is the length in spi_clk cycles of dummy\r
+ phase for write-status operations. The register value shall be (cycle_num-1).*/\r
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF\r
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S))\r
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF\r
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8\r
+/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */\r
+/*description: In the slave mode it is the length in spi_clk cycles of dummy\r
+ phase for read-status operations. The register value shall be (cycle_num-1).*/\r
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF\r
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S))\r
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF\r
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0\r
+\r
+#define SPI_SLAVE3_REG(i) (REG_SPI_BASE(i) + 0x44)\r
+/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */\r
+/*description: In the slave mode it is the value of write-status command.*/\r
+#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF\r
+#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S))\r
+#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF\r
+#define SPI_SLV_WRSTA_CMD_VALUE_S 24\r
+/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */\r
+/*description: In the slave mode it is the value of read-status command.*/\r
+#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF\r
+#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S))\r
+#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF\r
+#define SPI_SLV_RDSTA_CMD_VALUE_S 16\r
+/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */\r
+/*description: In the slave mode it is the value of write-buffer command.*/\r
+#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF\r
+#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S))\r
+#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF\r
+#define SPI_SLV_WRBUF_CMD_VALUE_S 8\r
+/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */\r
+/*description: In the slave mode it is the value of read-buffer command.*/\r
+#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF\r
+#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S))\r
+#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF\r
+#define SPI_SLV_RDBUF_CMD_VALUE_S 0\r
+\r
+#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x48)\r
+/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */\r
+/*description: In the slave mode it is the length in bits for write-buffer operations.\r
+ The register value shall be (bit_num-1).*/\r
+#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF\r
+#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S))\r
+#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF\r
+#define SPI_SLV_WRBUF_DBITLEN_S 0\r
+\r
+#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + 0x4C)\r
+/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */\r
+/*description: In the slave mode it is the length in bits for read-buffer operations.\r
+ The register value shall be (bit_num-1).*/\r
+#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF\r
+#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S))\r
+#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF\r
+#define SPI_SLV_RDBUF_DBITLEN_S 0\r
+\r
+#define SPI_CACHE_FCTRL_REG(i) (REG_SPI_BASE(i) + 0x50)\r
+/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: For SPI0 spi1 send suspend command before cache read flash \r
+ 1: enable 0:disable.*/\r
+#define SPI_CACHE_FLASH_PES_EN (BIT(3))\r
+#define SPI_CACHE_FLASH_PES_EN_M (BIT(3))\r
+#define SPI_CACHE_FLASH_PES_EN_V 0x1\r
+#define SPI_CACHE_FLASH_PES_EN_S 3\r
+/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/\r
+#define SPI_CACHE_FLASH_USR_CMD (BIT(2))\r
+#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2))\r
+#define SPI_CACHE_FLASH_USR_CMD_V 0x1\r
+#define SPI_CACHE_FLASH_USR_CMD_S 2\r
+/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/\r
+#define SPI_CACHE_USR_CMD_4BYTE (BIT(1))\r
+#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1))\r
+#define SPI_CACHE_USR_CMD_4BYTE_V 0x1\r
+#define SPI_CACHE_USR_CMD_4BYTE_S 1\r
+/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: For SPI0 Cache access enable 1: enable 0:disable.*/\r
+#define SPI_CACHE_REQ_EN (BIT(0))\r
+#define SPI_CACHE_REQ_EN_M (BIT(0))\r
+#define SPI_CACHE_REQ_EN_V 0x1\r
+#define SPI_CACHE_REQ_EN_S 0\r
+\r
+#define SPI_CACHE_SCTRL_REG(i) (REG_SPI_BASE(i) + 0x54)\r
+/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */\r
+/*description: For SPI0 In the spi sram mode cache write sram for user define command*/\r
+#define SPI_CACHE_SRAM_USR_WCMD (BIT(28))\r
+#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28))\r
+#define SPI_CACHE_SRAM_USR_WCMD_V 0x1\r
+#define SPI_CACHE_SRAM_USR_WCMD_S 28\r
+/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */\r
+/*description: For SPI0 In the sram mode it is the length in bits of address\r
+ phase. The register value shall be (bit_num-1).*/\r
+#define SPI_SRAM_ADDR_BITLEN 0x0000003F\r
+#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S))\r
+#define SPI_SRAM_ADDR_BITLEN_V 0x3F\r
+#define SPI_SRAM_ADDR_BITLEN_S 22\r
+/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */\r
+/*description: For SPI0 In the sram mode it is the length in bits of address\r
+ phase. The register value shall be (bit_num-1).*/\r
+#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF\r
+#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S))\r
+#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF\r
+#define SPI_SRAM_DUMMY_CYCLELEN_S 14\r
+/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */\r
+/*description: For SPI0 In the sram mode it is the byte length of spi read sram data.*/\r
+#define SPI_SRAM_BYTES_LEN 0x000000FF\r
+#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S))\r
+#define SPI_SRAM_BYTES_LEN_V 0xFF\r
+#define SPI_SRAM_BYTES_LEN_S 6\r
+/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */\r
+/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/\r
+#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))\r
+#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5))\r
+#define SPI_CACHE_SRAM_USR_RCMD_V 0x1\r
+#define SPI_CACHE_SRAM_USR_RCMD_S 5\r
+/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */\r
+/*description: For SPI0 In the spi sram mode it is the enable bit of dummy\r
+ phase for read operations.*/\r
+#define SPI_USR_RD_SRAM_DUMMY (BIT(4))\r
+#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4))\r
+#define SPI_USR_RD_SRAM_DUMMY_V 0x1\r
+#define SPI_USR_RD_SRAM_DUMMY_S 4\r
+/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: For SPI0 In the spi sram mode it is the enable bit of dummy\r
+ phase for write operations.*/\r
+#define SPI_USR_WR_SRAM_DUMMY (BIT(3))\r
+#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3))\r
+#define SPI_USR_WR_SRAM_DUMMY_V 0x1\r
+#define SPI_USR_WR_SRAM_DUMMY_S 3\r
+/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/\r
+#define SPI_USR_SRAM_QIO (BIT(2))\r
+#define SPI_USR_SRAM_QIO_M (BIT(2))\r
+#define SPI_USR_SRAM_QIO_V 0x1\r
+#define SPI_USR_SRAM_QIO_S 2\r
+/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/\r
+#define SPI_USR_SRAM_DIO (BIT(1))\r
+#define SPI_USR_SRAM_DIO_M (BIT(1))\r
+#define SPI_USR_SRAM_DIO_V 0x1\r
+#define SPI_USR_SRAM_DIO_S 1\r
+\r
+#define SPI_SRAM_CMD_REG(i) (REG_SPI_BASE(i) + 0x58)\r
+/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation\r
+ will be triggered when the bit is set. The bit will be cleared once the operation done*/\r
+#define SPI_SRAM_RSTIO (BIT(4))\r
+#define SPI_SRAM_RSTIO_M (BIT(4))\r
+#define SPI_SRAM_RSTIO_V 0x1\r
+#define SPI_SRAM_RSTIO_S 4\r
+/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will\r
+ be send when the bit is set. The bit will be cleared once the operation done.*/\r
+#define SPI_SRAM_QIO (BIT(1))\r
+#define SPI_SRAM_QIO_M (BIT(1))\r
+#define SPI_SRAM_QIO_V 0x1\r
+#define SPI_SRAM_QIO_S 1\r
+/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will\r
+ be send when the bit is set. The bit will be cleared once the operation done.*/\r
+#define SPI_SRAM_DIO (BIT(0))\r
+#define SPI_SRAM_DIO_M (BIT(0))\r
+#define SPI_SRAM_DIO_V 0x1\r
+#define SPI_SRAM_DIO_S 0\r
+\r
+#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + 0x5C)\r
+/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */\r
+/*description: For SPI0 When cache mode is enable it is the length in bits of\r
+ command phase for SRAM. The register value shall be (bit_num-1).*/\r
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F\r
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S))\r
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF\r
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28\r
+/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: For SPI0 When cache mode is enable it is the read command value\r
+ of command phase for SRAM.*/\r
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF\r
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S))\r
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF\r
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0\r
+\r
+#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + 0x60)\r
+/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */\r
+/*description: For SPI0 When cache mode is enable it is the in bits of command\r
+ phase for SRAM. The register value shall be (bit_num-1).*/\r
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F\r
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S))\r
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF\r
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28\r
+/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
+/*description: For SPI0 When cache mode is enable it is the write command value\r
+ of command phase for SRAM.*/\r
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF\r
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S))\r
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF\r
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0\r
+\r
+#define SPI_SLV_RD_BIT_REG(i) (REG_SPI_BASE(i) + 0x64)\r
+/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */\r
+/*description: In the slave mode it is the bit length of read data. The value\r
+ is the length - 1.*/\r
+#define SPI_SLV_RDATA_BIT 0x00FFFFFF\r
+#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S))\r
+#define SPI_SLV_RDATA_BIT_V 0xFFFFFF\r
+#define SPI_SLV_RDATA_BIT_S 0\r
+\r
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x80)\r
+/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF0 0xFFFFFFFF\r
+#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S))\r
+#define SPI_BUF0_V 0xFFFFFFFF\r
+#define SPI_BUF0_S 0\r
+\r
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x84)\r
+/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF1 0xFFFFFFFF\r
+#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S))\r
+#define SPI_BUF1_V 0xFFFFFFFF\r
+#define SPI_BUF1_S 0\r
+\r
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x88)\r
+/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF2 0xFFFFFFFF\r
+#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S))\r
+#define SPI_BUF2_V 0xFFFFFFFF\r
+#define SPI_BUF2_S 0\r
+\r
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x8C)\r
+/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF3 0xFFFFFFFF\r
+#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S))\r
+#define SPI_BUF3_V 0xFFFFFFFF\r
+#define SPI_BUF3_S 0\r
+\r
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x90)\r
+/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF4 0xFFFFFFFF\r
+#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S))\r
+#define SPI_BUF4_V 0xFFFFFFFF\r
+#define SPI_BUF4_S 0\r
+\r
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x94)\r
+/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF5 0xFFFFFFFF\r
+#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S))\r
+#define SPI_BUF5_V 0xFFFFFFFF\r
+#define SPI_BUF5_S 0\r
+\r
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x98)\r
+/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF6 0xFFFFFFFF\r
+#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S))\r
+#define SPI_BUF6_V 0xFFFFFFFF\r
+#define SPI_BUF6_S 0\r
+\r
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x9C)\r
+/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF7 0xFFFFFFFF\r
+#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S))\r
+#define SPI_BUF7_V 0xFFFFFFFF\r
+#define SPI_BUF7_S 0\r
+\r
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xA0)\r
+/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF8 0xFFFFFFFF\r
+#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S))\r
+#define SPI_BUF8_V 0xFFFFFFFF\r
+#define SPI_BUF8_S 0\r
+\r
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xA4)\r
+/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF9 0xFFFFFFFF\r
+#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S))\r
+#define SPI_BUF9_V 0xFFFFFFFF\r
+#define SPI_BUF9_S 0\r
+\r
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xA8)\r
+/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF10 0xFFFFFFFF\r
+#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S))\r
+#define SPI_BUF10_V 0xFFFFFFFF\r
+#define SPI_BUF10_S 0\r
+\r
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xAC)\r
+/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF11 0xFFFFFFFF\r
+#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S))\r
+#define SPI_BUF11_V 0xFFFFFFFF\r
+#define SPI_BUF11_S 0\r
+\r
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xB0)\r
+/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF12 0xFFFFFFFF\r
+#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S))\r
+#define SPI_BUF12_V 0xFFFFFFFF\r
+#define SPI_BUF12_S 0\r
+\r
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xB4)\r
+/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF13 0xFFFFFFFF\r
+#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S))\r
+#define SPI_BUF13_V 0xFFFFFFFF\r
+#define SPI_BUF13_S 0\r
+\r
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xB8)\r
+/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF14 0xFFFFFFFF\r
+#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S))\r
+#define SPI_BUF14_V 0xFFFFFFFF\r
+#define SPI_BUF14_S 0\r
+\r
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xBC)\r
+/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: data buffer*/\r
+#define SPI_BUF15 0xFFFFFFFF\r
+#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S))\r
+#define SPI_BUF15_V 0xFFFFFFFF\r
+#define SPI_BUF15_S 0\r
+\r
+#define SPI_TX_CRC_REG(i) (REG_SPI_BASE(i) + 0xC0)\r
+/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: For SPI1 the value of crc32 for 256 bits data.*/\r
+#define SPI_TX_CRC_DATA 0xFFFFFFFF\r
+#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S))\r
+#define SPI_TX_CRC_DATA_V 0xFFFFFFFF\r
+#define SPI_TX_CRC_DATA_S 0\r
+\r
+#define SPI_EXT0_REG(i) (REG_SPI_BASE(i) + 0xF0)\r
+/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */\r
+/*description: page program delay enable.*/\r
+#define SPI_T_PP_ENA (BIT(31))\r
+#define SPI_T_PP_ENA_M (BIT(31))\r
+#define SPI_T_PP_ENA_V 0x1\r
+#define SPI_T_PP_ENA_S 31\r
+/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */\r
+/*description: page program delay time shift .*/\r
+#define SPI_T_PP_SHIFT 0x0000000F\r
+#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S))\r
+#define SPI_T_PP_SHIFT_V 0xF\r
+#define SPI_T_PP_SHIFT_S 16\r
+/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */\r
+/*description: page program delay time by system clock.*/\r
+#define SPI_T_PP_TIME 0x00000FFF\r
+#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S))\r
+#define SPI_T_PP_TIME_V 0xFFF\r
+#define SPI_T_PP_TIME_S 0\r
+\r
+#define SPI_EXT1_REG(i) (REG_SPI_BASE(i) + 0xF4)\r
+/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */\r
+/*description: erase flash delay enable.*/\r
+#define SPI_T_ERASE_ENA (BIT(31))\r
+#define SPI_T_ERASE_ENA_M (BIT(31))\r
+#define SPI_T_ERASE_ENA_V 0x1\r
+#define SPI_T_ERASE_ENA_S 31\r
+/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */\r
+/*description: erase flash delay time shift.*/\r
+#define SPI_T_ERASE_SHIFT 0x0000000F\r
+#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S))\r
+#define SPI_T_ERASE_SHIFT_V 0xF\r
+#define SPI_T_ERASE_SHIFT_S 16\r
+/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */\r
+/*description: erase flash delay time by system clock.*/\r
+#define SPI_T_ERASE_TIME 0x00000FFF\r
+#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S))\r
+#define SPI_T_ERASE_TIME_V 0xFFF\r
+#define SPI_T_ERASE_TIME_S 0\r
+\r
+#define SPI_EXT2_REG(i) (REG_SPI_BASE(i) + 0xF8)\r
+/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */\r
+/*description: The status of spi state machine .*/\r
+#define SPI_ST 0x00000007\r
+#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S))\r
+#define SPI_ST_V 0x7\r
+#define SPI_ST_S 0\r
+\r
+#define SPI_EXT3_REG(i) (REG_SPI_BASE(i) + 0xFC)\r
+/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */\r
+/*description: This register is for two SPI masters to share the same cs clock\r
+ and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/\r
+#define SPI_INT_HOLD_ENA 0x00000003\r
+#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S))\r
+#define SPI_INT_HOLD_ENA_V 0x3\r
+#define SPI_INT_HOLD_ENA_S 0\r
+\r
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x100)\r
+/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: spi dma continue tx/rx data.*/\r
+#define SPI_DMA_CONTINUE (BIT(16))\r
+#define SPI_DMA_CONTINUE_M (BIT(16))\r
+#define SPI_DMA_CONTINUE_V 0x1\r
+#define SPI_DMA_CONTINUE_S 16\r
+/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: spi dma write data stop when in continue tx/rx mode.*/\r
+#define SPI_DMA_TX_STOP (BIT(15))\r
+#define SPI_DMA_TX_STOP_M (BIT(15))\r
+#define SPI_DMA_TX_STOP_V 0x1\r
+#define SPI_DMA_TX_STOP_S 15\r
+/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: spi dma read data stop when in continue tx/rx mode.*/\r
+#define SPI_DMA_RX_STOP (BIT(14))\r
+#define SPI_DMA_RX_STOP_M (BIT(14))\r
+#define SPI_DMA_RX_STOP_V 0x1\r
+#define SPI_DMA_RX_STOP_S 14\r
+/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: spi dma read data from memory in burst mode.*/\r
+#define SPI_OUT_DATA_BURST_EN (BIT(12))\r
+#define SPI_OUT_DATA_BURST_EN_M (BIT(12))\r
+#define SPI_OUT_DATA_BURST_EN_V 0x1\r
+#define SPI_OUT_DATA_BURST_EN_S 12\r
+/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: read descriptor use burst mode when write data to memory.*/\r
+#define SPI_INDSCR_BURST_EN (BIT(11))\r
+#define SPI_INDSCR_BURST_EN_M (BIT(11))\r
+#define SPI_INDSCR_BURST_EN_V 0x1\r
+#define SPI_INDSCR_BURST_EN_S 11\r
+/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: read descriptor use burst mode when read data for memory.*/\r
+#define SPI_OUTDSCR_BURST_EN (BIT(10))\r
+#define SPI_OUTDSCR_BURST_EN_M (BIT(10))\r
+#define SPI_OUTDSCR_BURST_EN_V 0x1\r
+#define SPI_OUTDSCR_BURST_EN_S 10\r
+/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */\r
+/*description: out eof flag generation mode . 1: when dma pop all data from\r
+ fifo 0:when ahb push all data to fifo.*/\r
+#define SPI_OUT_EOF_MODE (BIT(9))\r
+#define SPI_OUT_EOF_MODE_M (BIT(9))\r
+#define SPI_OUT_EOF_MODE_V 0x1\r
+#define SPI_OUT_EOF_MODE_S 9\r
+/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: when the link is empty jump to next automatically.*/\r
+#define SPI_OUT_AUTO_WRBACK (BIT(8))\r
+#define SPI_OUT_AUTO_WRBACK_M (BIT(8))\r
+#define SPI_OUT_AUTO_WRBACK_V 0x1\r
+#define SPI_OUT_AUTO_WRBACK_S 8\r
+/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: Set bit to test out link.*/\r
+#define SPI_OUT_LOOP_TEST (BIT(7))\r
+#define SPI_OUT_LOOP_TEST_M (BIT(7))\r
+#define SPI_OUT_LOOP_TEST_V 0x1\r
+#define SPI_OUT_LOOP_TEST_S 7\r
+/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set bit to test in link.*/\r
+#define SPI_IN_LOOP_TEST (BIT(6))\r
+#define SPI_IN_LOOP_TEST_M (BIT(6))\r
+#define SPI_IN_LOOP_TEST_V 0x1\r
+#define SPI_IN_LOOP_TEST_S 6\r
+/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: reset spi dma ahb master.*/\r
+#define SPI_AHBM_RST (BIT(5))\r
+#define SPI_AHBM_RST_M (BIT(5))\r
+#define SPI_AHBM_RST_V 0x1\r
+#define SPI_AHBM_RST_S 5\r
+/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: reset spi dma ahb master fifo pointer.*/\r
+#define SPI_AHBM_FIFO_RST (BIT(4))\r
+#define SPI_AHBM_FIFO_RST_M (BIT(4))\r
+#define SPI_AHBM_FIFO_RST_V 0x1\r
+#define SPI_AHBM_FIFO_RST_S 4\r
+/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/\r
+#define SPI_OUT_RST (BIT(3))\r
+#define SPI_OUT_RST_M (BIT(3))\r
+#define SPI_OUT_RST_V 0x1\r
+#define SPI_OUT_RST_S 3\r
+/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/\r
+#define SPI_IN_RST (BIT(2))\r
+#define SPI_IN_RST_M (BIT(2))\r
+#define SPI_IN_RST_V 0x1\r
+#define SPI_IN_RST_S 2\r
+\r
+#define SPI_DMA_OUT_LINK_REG(i) (REG_SPI_BASE(i) + 0x104)\r
+/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: Set the bit to mount on new outlink descriptors.*/\r
+#define SPI_OUTLINK_RESTART (BIT(30))\r
+#define SPI_OUTLINK_RESTART_M (BIT(30))\r
+#define SPI_OUTLINK_RESTART_V 0x1\r
+#define SPI_OUTLINK_RESTART_S 30\r
+/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: Set the bit to start to use outlink descriptor.*/\r
+#define SPI_OUTLINK_START (BIT(29))\r
+#define SPI_OUTLINK_START_M (BIT(29))\r
+#define SPI_OUTLINK_START_V 0x1\r
+#define SPI_OUTLINK_START_S 29\r
+/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: Set the bit to stop to use outlink descriptor.*/\r
+#define SPI_OUTLINK_STOP (BIT(28))\r
+#define SPI_OUTLINK_STOP_M (BIT(28))\r
+#define SPI_OUTLINK_STOP_V 0x1\r
+#define SPI_OUTLINK_STOP_S 28\r
+/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The address of the first outlink descriptor.*/\r
+#define SPI_OUTLINK_ADDR 0x000FFFFF\r
+#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S))\r
+#define SPI_OUTLINK_ADDR_V 0xFFFFF\r
+#define SPI_OUTLINK_ADDR_S 0\r
+\r
+#define SPI_DMA_IN_LINK_REG(i) (REG_SPI_BASE(i) + 0x108)\r
+/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: Set the bit to mount on new inlink descriptors.*/\r
+#define SPI_INLINK_RESTART (BIT(30))\r
+#define SPI_INLINK_RESTART_M (BIT(30))\r
+#define SPI_INLINK_RESTART_V 0x1\r
+#define SPI_INLINK_RESTART_S 30\r
+/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: Set the bit to start to use inlink descriptor.*/\r
+#define SPI_INLINK_START (BIT(29))\r
+#define SPI_INLINK_START_M (BIT(29))\r
+#define SPI_INLINK_START_V 0x1\r
+#define SPI_INLINK_START_S 29\r
+/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
+/*description: Set the bit to stop to use inlink descriptor.*/\r
+#define SPI_INLINK_STOP (BIT(28))\r
+#define SPI_INLINK_STOP_M (BIT(28))\r
+#define SPI_INLINK_STOP_V 0x1\r
+#define SPI_INLINK_STOP_S 28\r
+/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */\r
+/*description: when the bit is set inlink descriptor returns to the next descriptor\r
+ while a packet is wrong*/\r
+#define SPI_INLINK_AUTO_RET (BIT(20))\r
+#define SPI_INLINK_AUTO_RET_M (BIT(20))\r
+#define SPI_INLINK_AUTO_RET_V 0x1\r
+#define SPI_INLINK_AUTO_RET_S 20\r
+/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */\r
+/*description: The address of the first inlink descriptor.*/\r
+#define SPI_INLINK_ADDR 0x000FFFFF\r
+#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S))\r
+#define SPI_INLINK_ADDR_V 0xFFFFF\r
+#define SPI_INLINK_ADDR_S 0\r
+\r
+#define SPI_DMA_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10C)\r
+/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: spi dma write data status bit.*/\r
+#define SPI_DMA_TX_EN (BIT(1))\r
+#define SPI_DMA_TX_EN_M (BIT(1))\r
+#define SPI_DMA_TX_EN_V 0x1\r
+#define SPI_DMA_TX_EN_S 1\r
+/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: spi dma read data status bit.*/\r
+#define SPI_DMA_RX_EN (BIT(0))\r
+#define SPI_DMA_RX_EN_M (BIT(0))\r
+#define SPI_DMA_RX_EN_V 0x1\r
+#define SPI_DMA_RX_EN_S 0\r
+\r
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x110)\r
+/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The enable bit for sending all the packets to host done.*/\r
+#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))\r
+#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8))\r
+#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1\r
+#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8\r
+/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The enable bit for sending a packet to host done.*/\r
+#define SPI_OUT_EOF_INT_ENA (BIT(7))\r
+#define SPI_OUT_EOF_INT_ENA_M (BIT(7))\r
+#define SPI_OUT_EOF_INT_ENA_V 0x1\r
+#define SPI_OUT_EOF_INT_ENA_S 7\r
+/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The enable bit for completing usage of a outlink descriptor .*/\r
+#define SPI_OUT_DONE_INT_ENA (BIT(6))\r
+#define SPI_OUT_DONE_INT_ENA_M (BIT(6))\r
+#define SPI_OUT_DONE_INT_ENA_V 0x1\r
+#define SPI_OUT_DONE_INT_ENA_S 6\r
+/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The enable bit for completing receiving all the packets from host.*/\r
+#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))\r
+#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5))\r
+#define SPI_IN_SUC_EOF_INT_ENA_V 0x1\r
+#define SPI_IN_SUC_EOF_INT_ENA_S 5\r
+/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The enable bit for receiving error.*/\r
+#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))\r
+#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4))\r
+#define SPI_IN_ERR_EOF_INT_ENA_V 0x1\r
+#define SPI_IN_ERR_EOF_INT_ENA_S 4\r
+/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The enable bit for completing usage of a inlink descriptor.*/\r
+#define SPI_IN_DONE_INT_ENA (BIT(3))\r
+#define SPI_IN_DONE_INT_ENA_M (BIT(3))\r
+#define SPI_IN_DONE_INT_ENA_V 0x1\r
+#define SPI_IN_DONE_INT_ENA_S 3\r
+/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The enable bit for inlink descriptor error.*/\r
+#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))\r
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2))\r
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1\r
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2\r
+/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The enable bit for outlink descriptor error.*/\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1))\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1\r
+/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The enable bit for lack of enough inlink descriptors.*/\r
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))\r
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0))\r
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1\r
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0\r
+\r
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x114)\r
+/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The raw bit for sending all the packets to host done.*/\r
+#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))\r
+#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8))\r
+#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1\r
+#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8\r
+/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The raw bit for sending a packet to host done.*/\r
+#define SPI_OUT_EOF_INT_RAW (BIT(7))\r
+#define SPI_OUT_EOF_INT_RAW_M (BIT(7))\r
+#define SPI_OUT_EOF_INT_RAW_V 0x1\r
+#define SPI_OUT_EOF_INT_RAW_S 7\r
+/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The raw bit for completing usage of a outlink descriptor.*/\r
+#define SPI_OUT_DONE_INT_RAW (BIT(6))\r
+#define SPI_OUT_DONE_INT_RAW_M (BIT(6))\r
+#define SPI_OUT_DONE_INT_RAW_V 0x1\r
+#define SPI_OUT_DONE_INT_RAW_S 6\r
+/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The raw bit for completing receiving all the packets from host.*/\r
+#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))\r
+#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5))\r
+#define SPI_IN_SUC_EOF_INT_RAW_V 0x1\r
+#define SPI_IN_SUC_EOF_INT_RAW_S 5\r
+/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The raw bit for receiving error.*/\r
+#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))\r
+#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4))\r
+#define SPI_IN_ERR_EOF_INT_RAW_V 0x1\r
+#define SPI_IN_ERR_EOF_INT_RAW_S 4\r
+/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The raw bit for completing usage of a inlink descriptor.*/\r
+#define SPI_IN_DONE_INT_RAW (BIT(3))\r
+#define SPI_IN_DONE_INT_RAW_M (BIT(3))\r
+#define SPI_IN_DONE_INT_RAW_V 0x1\r
+#define SPI_IN_DONE_INT_RAW_S 3\r
+/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The raw bit for inlink descriptor error.*/\r
+#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))\r
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2))\r
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1\r
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2\r
+/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The raw bit for outlink descriptor error.*/\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1))\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1\r
+/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The raw bit for lack of enough inlink descriptors.*/\r
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))\r
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0))\r
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1\r
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0\r
+\r
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x118)\r
+/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The status bit for sending all the packets to host done.*/\r
+#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))\r
+#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8))\r
+#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1\r
+#define SPI_OUT_TOTAL_EOF_INT_ST_S 8\r
+/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The status bit for sending a packet to host done.*/\r
+#define SPI_OUT_EOF_INT_ST (BIT(7))\r
+#define SPI_OUT_EOF_INT_ST_M (BIT(7))\r
+#define SPI_OUT_EOF_INT_ST_V 0x1\r
+#define SPI_OUT_EOF_INT_ST_S 7\r
+/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The status bit for completing usage of a outlink descriptor.*/\r
+#define SPI_OUT_DONE_INT_ST (BIT(6))\r
+#define SPI_OUT_DONE_INT_ST_M (BIT(6))\r
+#define SPI_OUT_DONE_INT_ST_V 0x1\r
+#define SPI_OUT_DONE_INT_ST_S 6\r
+/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The status bit for completing receiving all the packets from host.*/\r
+#define SPI_IN_SUC_EOF_INT_ST (BIT(5))\r
+#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5))\r
+#define SPI_IN_SUC_EOF_INT_ST_V 0x1\r
+#define SPI_IN_SUC_EOF_INT_ST_S 5\r
+/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The status bit for receiving error.*/\r
+#define SPI_IN_ERR_EOF_INT_ST (BIT(4))\r
+#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4))\r
+#define SPI_IN_ERR_EOF_INT_ST_V 0x1\r
+#define SPI_IN_ERR_EOF_INT_ST_S 4\r
+/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The status bit for completing usage of a inlink descriptor.*/\r
+#define SPI_IN_DONE_INT_ST (BIT(3))\r
+#define SPI_IN_DONE_INT_ST_M (BIT(3))\r
+#define SPI_IN_DONE_INT_ST_V 0x1\r
+#define SPI_IN_DONE_INT_ST_S 3\r
+/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The status bit for inlink descriptor error.*/\r
+#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))\r
+#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2))\r
+#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1\r
+#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2\r
+/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The status bit for outlink descriptor error.*/\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1))\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1\r
+/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The status bit for lack of enough inlink descriptors.*/\r
+#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))\r
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0))\r
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1\r
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0\r
+\r
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x11C)\r
+/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: The clear bit for sending all the packets to host done.*/\r
+#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))\r
+#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8))\r
+#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1\r
+#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8\r
+/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: The clear bit for sending a packet to host done.*/\r
+#define SPI_OUT_EOF_INT_CLR (BIT(7))\r
+#define SPI_OUT_EOF_INT_CLR_M (BIT(7))\r
+#define SPI_OUT_EOF_INT_CLR_V 0x1\r
+#define SPI_OUT_EOF_INT_CLR_S 7\r
+/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: The clear bit for completing usage of a outlink descriptor.*/\r
+#define SPI_OUT_DONE_INT_CLR (BIT(6))\r
+#define SPI_OUT_DONE_INT_CLR_M (BIT(6))\r
+#define SPI_OUT_DONE_INT_CLR_V 0x1\r
+#define SPI_OUT_DONE_INT_CLR_S 6\r
+/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: The clear bit for completing receiving all the packets from host.*/\r
+#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))\r
+#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5))\r
+#define SPI_IN_SUC_EOF_INT_CLR_V 0x1\r
+#define SPI_IN_SUC_EOF_INT_CLR_S 5\r
+/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: The clear bit for receiving error.*/\r
+#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))\r
+#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4))\r
+#define SPI_IN_ERR_EOF_INT_CLR_V 0x1\r
+#define SPI_IN_ERR_EOF_INT_CLR_S 4\r
+/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: The clear bit for completing usage of a inlink descriptor.*/\r
+#define SPI_IN_DONE_INT_CLR (BIT(3))\r
+#define SPI_IN_DONE_INT_CLR_M (BIT(3))\r
+#define SPI_IN_DONE_INT_CLR_V 0x1\r
+#define SPI_IN_DONE_INT_CLR_S 3\r
+/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: The clear bit for inlink descriptor error.*/\r
+#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))\r
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2))\r
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1\r
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2\r
+/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: The clear bit for outlink descriptor error.*/\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1))\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1\r
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1\r
+/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: The clear bit for lack of enough inlink descriptors.*/\r
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))\r
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0))\r
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1\r
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0\r
+\r
+#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x120)\r
+/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The inlink descriptor address when spi dma produce receiving error.*/\r
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF\r
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S))\r
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF\r
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0\r
+\r
+#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x124)\r
+/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/\r
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF\r
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S))\r
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF\r
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0\r
+\r
+#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x128)\r
+/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The content of current in descriptor pointer.*/\r
+#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF\r
+#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S))\r
+#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF\r
+#define SPI_DMA_INLINK_DSCR_S 0\r
+\r
+#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x12C)\r
+/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The content of next in descriptor pointer.*/\r
+#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF\r
+#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S))\r
+#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF\r
+#define SPI_DMA_INLINK_DSCR_BF0_S 0\r
+\r
+#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x130)\r
+/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The content of current in descriptor data buffer pointer.*/\r
+#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF\r
+#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S))\r
+#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF\r
+#define SPI_DMA_INLINK_DSCR_BF1_S 0\r
+\r
+#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x134)\r
+/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The address of buffer relative to the outlink descriptor that produce eof.*/\r
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF\r
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S))\r
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF\r
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0\r
+\r
+#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + 0x138)\r
+/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The last outlink descriptor address when spi dma produce to_eof.*/\r
+#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF\r
+#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S))\r
+#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF\r
+#define SPI_DMA_OUT_EOF_DES_ADDR_S 0\r
+\r
+#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + 0x13C)\r
+/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The content of current out descriptor pointer.*/\r
+#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF\r
+#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S))\r
+#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF\r
+#define SPI_DMA_OUTLINK_DSCR_S 0\r
+\r
+#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + 0x140)\r
+/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The content of next out descriptor pointer.*/\r
+#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF\r
+#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S))\r
+#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF\r
+#define SPI_DMA_OUTLINK_DSCR_BF0_S 0\r
+\r
+#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + 0x144)\r
+/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: The content of current out descriptor data buffer pointer.*/\r
+#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF\r
+#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S))\r
+#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF\r
+#define SPI_DMA_OUTLINK_DSCR_BF1_S 0\r
+\r
+#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + 0x148)\r
+/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: spi dma read data from memory status.*/\r
+#define SPI_DMA_OUT_STATUS 0xFFFFFFFF\r
+#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S))\r
+#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF\r
+#define SPI_DMA_OUT_STATUS_S 0\r
+\r
+#define SPI_DMA_TSTATUS_REG(i) (REG_SPI_BASE(i) + 0x14C)\r
+/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */\r
+/*description: spi dma write data to memory status.*/\r
+#define SPI_DMA_IN_STATUS 0xFFFFFFFF\r
+#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S))\r
+#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF\r
+#define SPI_DMA_IN_STATUS_S 0\r
+\r
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x3FC)\r
+/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */\r
+/*description: SPI register version.*/\r
+#define SPI_DATE 0x0FFFFFFF\r
+#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))\r
+#define SPI_DATE_V 0xFFFFFFF\r
+#define SPI_DATE_S 0\r
+\r
+\r
+\r
+\r
+#endif /*__SPI_REG_H__ */\r
+\r
+\r
+++ /dev/null
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SPI_REG_H_
-#define _SOC_SPI_REG_H_
-
-#include "soc.h"
-
-#define SPI_CMD( i ) (REG_SPI_BASE( i ) + 0x0)
-#define SPI_FLASH_READ (BIT(31))
-#define SPI_FLASH_WREN (BIT(30))
-#define SPI_FLASH_WRDI (BIT(29))
-#define SPI_FLASH_RDID (BIT(28))
-#define SPI_FLASH_RDSR (BIT(27))
-#define SPI_FLASH_WRSR (BIT(26))
-#define SPI_FLASH_PP (BIT(25))
-#define SPI_FLASH_SE (BIT(24))
-#define SPI_FLASH_BE (BIT(23))
-#define SPI_FLASH_CE (BIT(22))
-#define SPI_FLASH_DP (BIT(21))
-#define SPI_FLASH_RES (BIT(20))
-#define SPI_FLASH_HPM (BIT(19))
-#define SPI_USR (BIT(18))
-#define SPI_FLASH_PES (BIT(17))
-#define SPI_FLASH_PER (BIT(16))
-#define SPI_ADDR( i ) (REG_SPI_BASE( i ) + 0x4)
-#define SPI_CTRL( i ) (REG_SPI_BASE( i ) + 0x8)
-#define SPI_WR_BIT_ORDER (BIT(26))
-#define SPI_RD_BIT_ORDER (BIT(25))
-#define SPI_FREAD_QIO (BIT(24))
-#define SPI_FREAD_DIO (BIT(23))
-#define SPI_WRSR_2B (BIT(22))
-#define SPI_WP_REG (BIT(21))
-#define SPI_FREAD_QUAD (BIT(20))
-#define SPI_RESANDRES (BIT(15))
-#define SPI_FREAD_DUAL (BIT(14))
-#define SPI_FASTRD_MODE (BIT(13))
-#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))
-#define SPI_TX_CRC_EN (BIT(11))
-#define SPI_FCS_CRC_EN (BIT(10))
-#define SPI_CTRL1( i ) (REG_SPI_BASE( i ) + 0xC)
-#define SPI_CS_HOLD_DELAY 0x0000000F
-#define SPI_CS_HOLD_DELAY_S 28
-#define SPI_CS_HOLD_DELAY_RES 0x00000FFF
-#define SPI_CS_HOLD_DELAY_RES_S 16
-#define SPI_RD_STATUS( i ) (REG_SPI_BASE( i ) + 0x10)
-#define SPI_STATUS_EXT 0x000000FF
-#define SPI_STATUS_EXT_S 24
-#define SPI_WB_MODE 0x000000FF
-#define SPI_WB_MODE_S 16
-#define SPI_STATUS 0x0000FFFF
-#define SPI_STATUS_S 0
-
-#define SPI_CTRL2( i ) (REG_SPI_BASE( i ) + 0x14)
-#define SPI_CS_DELAY_NUM 0x0000000F
-#define SPI_CS_DELAY_NUM_S 28
-#define SPI_CS_DELAY_MODE 0x00000003
-#define SPI_CS_DELAY_MODE_S 26
-#define SPI_MOSI_DELAY_NUM 0x00000007
-#define SPI_MOSI_DELAY_NUM_S 23
-#define SPI_MOSI_DELAY_MODE 0x00000003
-#define SPI_MOSI_DELAY_MODE_S 21
-#define SPI_MISO_DELAY_NUM 0x00000007
-#define SPI_MISO_DELAY_NUM_S 18
-#define SPI_MISO_DELAY_MODE 0x00000003
-#define SPI_MISO_DELAY_MODE_S 16
-#define SPI_CK_OUT_HIGH_MODE 0x0000000F
-#define SPI_CK_OUT_HIGH_MODE_S 12
-#define SPI_CK_OUT_LOW_MODE 0x0000000F
-#define SPI_CK_OUT_LOW_MODE_S 8
-#define SPI_HOLD_TIME 0x0000000F
-#define SPI_HOLD_TIME_S 4
-#define SPI_SETUP_TIME 0x0000000F
-#define SPI_SETUP_TIME_S 0
-
-#define SPI_CLOCK( i ) (REG_SPI_BASE( i ) + 0x18)
-#define SPI_CLK_EQU_SYSCLK (BIT(31))
-#define SPI_CLKDIV_PRE 0x00001FFF
-#define SPI_CLKDIV_PRE_S 18
-#define SPI_CLKCNT_N 0x0000003F
-#define SPI_CLKCNT_N_S 12
-#define SPI_CLKCNT_H 0x0000003F
-#define SPI_CLKCNT_H_S 6
-#define SPI_CLKCNT_L 0x0000003F
-#define SPI_CLKCNT_L_S 0
-
-#define SPI_USER( i ) (REG_SPI_BASE( i ) + 0x1C)
-#define SPI_USR_COMMAND (BIT(31))
-#define SPI_USR_ADDR (BIT(30))
-#define SPI_USR_DUMMY (BIT(29))
-#define SPI_USR_MISO (BIT(28))
-#define SPI_USR_MOSI (BIT(27))
-#define SPI_USR_DUMMY_IDLE (BIT(26))
-#define SPI_USR_MOSI_HIGHPART (BIT(25))
-#define SPI_USR_MISO_HIGHPART (BIT(24))
-#define SPI_USR_PREP_HOLD (BIT(23))
-#define SPI_USR_CMD_HOLD (BIT(22))
-#define SPI_USR_ADDR_HOLD (BIT(21))
-#define SPI_USR_DUMMY_HOLD (BIT(20))
-#define SPI_USR_DIN_HOLD (BIT(19))
-#define SPI_USR_DOUT_HOLD (BIT(18))
-#define SPI_USR_HOLD_POL (BIT(17))
-#define SPI_SIO (BIT(16))
-#define SPI_FWRITE_QIO (BIT(15))
-#define SPI_FWRITE_DIO (BIT(14))
-#define SPI_FWRITE_QUAD (BIT(13))
-#define SPI_FWRITE_DUAL (BIT(12))
-#define SPI_WR_BYTE_ORDER (BIT(11))
-#define SPI_RD_BYTE_ORDER (BIT(10))
-#define SPI_CK_OUT_EDGE (BIT(7))
-#define SPI_CK_I_EDGE (BIT(6))
-#define SPI_CS_SETUP (BIT(5))
-#define SPI_CS_HOLD (BIT(4))
-#define SPI_DOUTDIN (BIT(0))
-
-#define SPI_USER1( i ) (REG_SPI_BASE( i ) + 0x20)
-#define SPI_USR_ADDR_BITLEN 0x0000003F
-#define SPI_USR_ADDR_BITLEN_S 26
-#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
-#define SPI_USR_DUMMY_CYCLELEN_S 0
-
-#define SPI_USER2( i ) (REG_SPI_BASE( i ) + 0x24)
-#define SPI_USR_COMMAND_BITLEN 0x0000000F
-#define SPI_USR_COMMAND_BITLEN_S 28
-#define SPI_USR_COMMAND_VALUE 0x0000FFFF
-#define SPI_USR_COMMAND_VALUE_S 0
-
-#define SPI_MOSI_DLEN( i ) (REG_SPI_BASE( i ) + 0x28)
-#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF
-#define SPI_USR_MOSI_DBITLEN_S 0
-
-#define SPI_MISO_DLEN( i ) (REG_SPI_BASE( i ) + 0x2C)
-#define SPI_USR_MISO_DBITLEN 0x00FFFFFF
-#define SPI_USR_MISO_DBITLEN_S 0
-
-#define SPI_SLV_WR_STATUS( i ) (REG_SPI_BASE( i ) + 0x30)
-#define SPI_PIN( i ) (REG_SPI_BASE( i ) + 0x34)
-#define SPI_CS_KEEP_ACTIVE (BIT(30))
-#define SPI_CK_IDLE_EDGE (BIT(29))
-#define SPI_CSCK_SEL (BIT(19))
-#define SPI_MASTER_CK_SEL 0x0000001F
-#define SPI_MASTER_CK_SEL_S 11
-#define SPI_MASTER_CS_POL 0x0000001F
-#define SPI_MASTER_CS_POL_S 6
-#define SPI_CK_DIS (BIT(5))
-#define SPI_CS2_DIS (BIT(2))
-#define SPI_CS1_DIS (BIT(1))
-#define SPI_CS0_DIS (BIT(0))
-
-#define SPI_SLAVE( i ) (REG_SPI_BASE( i ) + 0x38)
-#define SPI_SYNC_RESET (BIT(31))
-#define SPI_SLAVE_MODE (BIT(30))
-#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
-#define SPI_SLV_WR_RD_STA_EN (BIT(28))
-#define SPI_SLV_CMD_DEFINE (BIT(27))
-#define SPI_TRANS_CNT 0x0000000F
-#define SPI_TRANS_CNT_S 23
-#define SPI_SLV_LAST_STATE 0x00000007
-#define SPI_SLV_LAST_STATE_S 20
-#define SPI_SLV_LAST_COMMAND 0x00000007
-#define SPI_SLV_LAST_COMMAND_S 17
-#define SPI_CS_I_MODE 0x00000003
-#define SPI_CS_I_MODE_S 10
-#define SPI_INT_EN 0x0000001F
-#define SPI_INT_EN_S 5
-#define SPI_TRANS_DONE (BIT(4))
-#define SPI_SLV_WR_STA_DONE (BIT(3))
-#define SPI_SLV_RD_STA_DONE (BIT(2))
-#define SPI_SLV_WR_BUF_DONE (BIT(1))
-#define SPI_SLV_RD_BUF_DONE (BIT(0))
-
-#define SPI_SLAVE1( i ) (REG_SPI_BASE( i ) + 0x3C)
-#define SPI_SLV_STATUS_BITLEN 0x0000001F
-#define SPI_SLV_STATUS_BITLEN_S 27
-#define SPI_SLV_STATUS_FAST_EN (BIT(26))
-#define SPI_SLV_STATUS_READBACK (BIT(25))
-#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
-#define SPI_SLV_RD_ADDR_BITLEN_S 10
-#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
-#define SPI_SLV_WR_ADDR_BITLEN_S 4
-#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
-#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
-#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
-#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
-
-#define SPI_SLAVE2( i ) (REG_SPI_BASE( i ) + 0x40)
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0
-
-#define SPI_SLAVE3( i ) (REG_SPI_BASE( i ) + 0x44)
-#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
-#define SPI_SLV_WRSTA_CMD_VALUE_S 24
-#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
-#define SPI_SLV_RDSTA_CMD_VALUE_S 16
-#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
-#define SPI_SLV_WRBUF_CMD_VALUE_S 8
-#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
-#define SPI_SLV_RDBUF_CMD_VALUE_S 0
-
-#define SPI_SLV_WRBUF_DLEN( i ) (REG_SPI_BASE( i ) + 0x48)
-#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF
-#define SPI_SLV_WRBUF_DBITLEN_S 0
-
-#define SPI_SLV_RDBUF_DLEN( i ) (REG_SPI_BASE( i ) + 0x4C)
-#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF
-#define SPI_SLV_RDBUF_DBITLEN_S 0
-
-#define SPI_CACHE_FCTRL( i ) (REG_SPI_BASE( i ) + 0x50)
-#define SPI_CACHE_FLASH_PES_EN (BIT(3))
-#define SPI_CACHE_FLASH_USR_CMD (BIT(2))
-#define SPI_CACHE_USR_CMD_4BYTE (BIT(1))
-#define SPI_CACHE_REQ_EN (BIT(0))
-
-#define SPI_CACHE_SCTRL( i ) (REG_SPI_BASE( i ) + 0x54)
-#define SPI_CACHE_SRAM_USR_WCMD (BIT(28))
-#define SPI_SRAM_ADDR_BITLEN 0x0000003F
-#define SPI_SRAM_ADDR_BITLEN_S 22
-#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF
-#define SPI_SRAM_DUMMY_CYCLELEN_S 14
-#define SPI_SRAM_BYTES_LEN 0x000000FF
-#define SPI_SRAM_BYTES_LEN_S 6
-#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))
-#define SPI_USR_RD_SRAM_DUMMY (BIT(4))
-#define SPI_USR_WR_SRAM_DUMMY (BIT(3))
-#define SPI_USR_SRAM_QIO (BIT(2))
-#define SPI_USR_SRAM_DIO (BIT(1))
-#define SPI_SRAM_CMD( i ) (REG_SPI_BASE( i ) + 0x58)
-#define SPI_SRAM_RSTIO (BIT(4))
-#define SPI_SRAM_QIO (BIT(1))
-#define SPI_SRAM_DIO (BIT(0))
-
-#define SPI_SRAM_DRD_CMD( i ) (REG_SPI_BASE( i ) + 0x5C)
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
-
-#define SPI_SRAM_DWR_CMD( i ) (REG_SPI_BASE( i ) + 0x60)
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
-
-#define SPI_SLV_RD_BIT( i ) (REG_SPI_BASE( i ) + 0x64)
-#define SPI_SLV_RDATA_BIT 0x00FFFFFF
-#define SPI_SLV_RDATA_BIT_S 0
-
-#define SPI_W0( i ) (REG_SPI_BASE( i ) + 0x80)
-#define SPI_W1( i ) (REG_SPI_BASE( i ) + 0x84)
-#define SPI_W2( i ) (REG_SPI_BASE( i ) + 0x88)
-#define SPI_W3( i ) (REG_SPI_BASE( i ) + 0x8C)
-#define SPI_W4( i ) (REG_SPI_BASE( i ) + 0x90)
-#define SPI_W5( i ) (REG_SPI_BASE( i ) + 0x94)
-#define SPI_W6( i ) (REG_SPI_BASE( i ) + 0x98)
-#define SPI_W7( i ) (REG_SPI_BASE( i ) + 0x9C)
-#define SPI_W8( i ) (REG_SPI_BASE( i ) + 0xA0)
-#define SPI_W9( i ) (REG_SPI_BASE( i ) + 0xA4)
-#define SPI_W10( i ) (REG_SPI_BASE( i ) + 0xA8)
-#define SPI_W11( i ) (REG_SPI_BASE( i ) + 0xAC)
-#define SPI_W12( i ) (REG_SPI_BASE( i ) + 0xB0)
-#define SPI_W13( i ) (REG_SPI_BASE( i ) + 0xB4)
-#define SPI_W14( i ) (REG_SPI_BASE( i ) + 0xB8)
-#define SPI_W15( i ) (REG_SPI_BASE( i ) + 0xBC)
-#define SPI_TX_CRC( i ) (REG_SPI_BASE( i ) + 0xC0)
-#define SPI_EXT0( i ) (REG_SPI_BASE( i ) + 0xF0)
-#define SPI_T_PP_ENA (BIT(31))
-#define SPI_T_PP_SHIFT 0x0000000F
-#define SPI_T_PP_SHIFT_S 16
-#define SPI_T_PP_TIME 0x00000FFF
-#define SPI_T_PP_TIME_S 0
-
-#define SPI_EXT1( i ) (REG_SPI_BASE( i ) + 0xF4)
-#define SPI_T_ERASE_ENA (BIT(31))
-#define SPI_T_ERASE_SHIFT 0x0000000F
-#define SPI_T_ERASE_SHIFT_S 16
-#define SPI_T_ERASE_TIME 0x00000FFF
-#define SPI_T_ERASE_TIME_S 0
-
-#define SPI_EXT2( i ) (REG_SPI_BASE( i ) + 0xF8)
-#define SPI_ST 0x00000007
-#define SPI_ST_S 0
-
-#define SPI_EXT3( i ) (REG_SPI_BASE( i ) + 0xFC)
-#define SPI_INT_HOLD_ENA 0x00000003
-#define SPI_INT_HOLD_ENA_S 0
-
-#define SPI_DMA_CONF( i ) (REG_SPI_BASE( i ) + 0x100)
-#define SPI_DMA_CONTINUE (BIT(16))
-#define SPI_DMA_TX_STOP (BIT(15))
-#define SPI_DMA_RX_STOP (BIT(14))
-#define SPI_OUT_DATA_BURST_EN (BIT(12))
-#define SPI_INDSCR_BURST_EN (BIT(11))
-#define SPI_OUTDSCR_BURST_EN (BIT(10))
-#define SPI_OUT_EOF_MODE (BIT(9))
-#define SPI_OUT_AUTO_WRBACK (BIT(8))
-#define SPI_OUT_LOOP_TEST (BIT(7))
-#define SPI_IN_LOOP_TEST (BIT(6))
-#define SPI_AHBM_RST (BIT(5))
-#define SPI_AHBM_FIFO_RST (BIT(4))
-#define SPI_OUT_RST (BIT(3))
-#define SPI_IN_RST (BIT(2))
-#define SPI_DMA_OUT_LINK( i ) (REG_SPI_BASE( i ) + 0x104)
-#define SPI_OUTLINK_RESTART (BIT(30))
-#define SPI_OUTLINK_START (BIT(29))
-#define SPI_OUTLINK_STOP (BIT(28))
-#define SPI_OUTLINK_ADDR 0x000FFFFF
-#define SPI_OUTLINK_ADDR_S 0
-
-#define SPI_DMA_IN_LINK( i ) (REG_SPI_BASE( i ) + 0x108)
-#define SPI_INLINK_RESTART (BIT(30))
-#define SPI_INLINK_START (BIT(29))
-#define SPI_INLINK_STOP (BIT(28))
-#define SPI_INLINK_AUTO_RET (BIT(20))
-#define SPI_INLINK_ADDR 0x000FFFFF
-#define SPI_INLINK_ADDR_S 0
-
-#define SPI_DMA_STATUS( i ) (REG_SPI_BASE( i ) + 0x10C)
-#define SPI_DMA_TX_EN (BIT(1))
-#define SPI_DMA_RX_EN (BIT(0))
-
-#define SPI_DMA_INT_ENA( i ) (REG_SPI_BASE( i ) + 0x110)
-#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))
-#define SPI_OUT_EOF_INT_ENA (BIT(7))
-#define SPI_OUT_DONE_INT_ENA (BIT(6))
-#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))
-#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))
-#define SPI_IN_DONE_INT_ENA (BIT(3))
-#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))
-
-#define SPI_DMA_INT_RAW( i ) (REG_SPI_BASE( i ) + 0x114)
-#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))
-#define SPI_OUT_EOF_INT_RAW (BIT(7))
-#define SPI_OUT_DONE_INT_RAW (BIT(6))
-#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))
-#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))
-#define SPI_IN_DONE_INT_RAW (BIT(3))
-#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))
-
-#define SPI_DMA_INT_ST( i ) (REG_SPI_BASE( i ) + 0x118)
-#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))
-#define SPI_OUT_EOF_INT_ST (BIT(7))
-#define SPI_OUT_DONE_INT_ST (BIT(6))
-#define SPI_IN_SUC_EOF_INT_ST (BIT(5))
-#define SPI_IN_ERR_EOF_INT_ST (BIT(4))
-#define SPI_IN_DONE_INT_ST (BIT(3))
-#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))
-#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))
-
-#define SPI_DMA_INT_CLR( i ) (REG_SPI_BASE( i ) + 0x11C)
-#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))
-#define SPI_OUT_EOF_INT_CLR (BIT(7))
-#define SPI_OUT_DONE_INT_CLR (BIT(6))
-#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))
-#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))
-#define SPI_IN_DONE_INT_CLR (BIT(3))
-#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))
-
-#define SPI_IN_ERR_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x120)
-#define SPI_IN_SUC_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x124)
-#define SPI_INLINK_DSCR( i ) (REG_SPI_BASE( i ) + 0x128)
-#define SPI_INLINK_DSCR_BF0( i ) (REG_SPI_BASE( i ) + 0x12C)
-#define SPI_INLINK_DSCR_BF1( i ) (REG_SPI_BASE( i ) + 0x130)
-#define SPI_OUT_EOF_BFR_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x134)
-#define SPI_OUT_EOF_DES_ADDR( i ) (REG_SPI_BASE( i ) + 0x138)
-#define SPI_OUTLINK_DSCR( i ) (REG_SPI_BASE( i ) + 0x13C)
-#define SPI_OUTLINK_DSCR_BF0( i ) (REG_SPI_BASE( i ) + 0x140)
-#define SPI_OUTLINK_DSCR_BF1( i ) (REG_SPI_BASE( i ) + 0x144)
-#define SPI_DMA_RSTATUS( i ) (REG_SPI_BASE( i ) + 0x148)
-#define SPI_DMA_TSTATUS( i ) (REG_SPI_BASE( i ) + 0x14C)
-#define SPI_REG_DATE( i ) (REG_SPI_BASE( i ) + 0x3FC)
-#define SPI_DATE 0x0FFFFFFF
-#define SPI_DATE_S 0
-#define SPI_DATE_VERSION 0x1604290
-
-#endif /* _SOC_SPI_REG_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __TIMG_REG_H__
+#define __TIMG_REG_H__
+#include "soc.h"
+
+#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
+#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
+/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: When set timer 0 time-base counter is enabled*/
+#define TIMG_T0_EN (BIT(31))
+#define TIMG_T0_EN_M (BIT(31))
+#define TIMG_T0_EN_V 0x1
+#define TIMG_T0_EN_S 31
+/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: When set timer 0 time-base counter increment. When cleared timer
+ 0 time-base counter decrement.*/
+#define TIMG_T0_INCREASE (BIT(30))
+#define TIMG_T0_INCREASE_M (BIT(30))
+#define TIMG_T0_INCREASE_V 0x1
+#define TIMG_T0_INCREASE_S 30
+/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
+/*description: When set timer 0 auto-reload at alarming is enabled*/
+#define TIMG_T0_AUTORELOAD (BIT(29))
+#define TIMG_T0_AUTORELOAD_M (BIT(29))
+#define TIMG_T0_AUTORELOAD_V 0x1
+#define TIMG_T0_AUTORELOAD_S 29
+/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
+/*description: Timer 0 clock (T0_clk) prescale value.*/
+#define TIMG_T0_DIVIDER 0x0000FFFF
+#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
+#define TIMG_T0_DIVIDER_V 0xFFFF
+#define TIMG_T0_DIVIDER_S 13
+/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: When set edge type interrupt will be generated during alarm*/
+#define TIMG_T0_EDGE_INT_EN (BIT(12))
+#define TIMG_T0_EDGE_INT_EN_M (BIT(12))
+#define TIMG_T0_EDGE_INT_EN_V 0x1
+#define TIMG_T0_EDGE_INT_EN_S 12
+/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: When set level type interrupt will be generated during alarm*/
+#define TIMG_T0_LEVEL_INT_EN (BIT(11))
+#define TIMG_T0_LEVEL_INT_EN_M (BIT(11))
+#define TIMG_T0_LEVEL_INT_EN_V 0x1
+#define TIMG_T0_LEVEL_INT_EN_S 11
+/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: When set alarm is enabled*/
+#define TIMG_T0_ALARM_EN (BIT(10))
+#define TIMG_T0_ALARM_EN_M (BIT(10))
+#define TIMG_T0_ALARM_EN_V 0x1
+#define TIMG_T0_ALARM_EN_S 10
+
+#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
+/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Register to store timer 0 time-base counter current value lower 32 bits.*/
+#define TIMG_T0_LO 0xFFFFFFFF
+#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
+#define TIMG_T0_LO_V 0xFFFFFFFF
+#define TIMG_T0_LO_S 0
+
+#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
+/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Register to store timer 0 time-base counter current value higher 32 bits.*/
+#define TIMG_T0_HI 0xFFFFFFFF
+#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
+#define TIMG_T0_HI_V 0xFFFFFFFF
+#define TIMG_T0_HI_S 0
+
+#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
+/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Write any value will trigger a timer 0 time-base counter value
+ update (timer 0 current value will be stored in registers above)*/
+#define TIMG_T0_UPDATE 0xFFFFFFFF
+#define TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S))
+#define TIMG_T0_UPDATE_V 0xFFFFFFFF
+#define TIMG_T0_UPDATE_S 0
+
+#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
+/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
+#define TIMG_T0_ALARM_LO 0xFFFFFFFF
+#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
+#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
+#define TIMG_T0_ALARM_LO_S 0
+
+#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
+/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
+#define TIMG_T0_ALARM_HI 0xFFFFFFFF
+#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
+#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF
+#define TIMG_T0_ALARM_HI_S 0
+
+#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
+/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Lower 32 bits of the value that will load into timer 0 time-base counter*/
+#define TIMG_T0_LOAD_LO 0xFFFFFFFF
+#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
+#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
+#define TIMG_T0_LOAD_LO_S 0
+
+#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
+/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: higher 32 bits of the value that will load into timer 0 time-base counter*/
+#define TIMG_T0_LOAD_HI 0xFFFFFFFF
+#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
+#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF
+#define TIMG_T0_LOAD_HI_S 0
+
+#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
+/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Write any value will trigger timer 0 time-base counter reload*/
+#define TIMG_T0_LOAD 0xFFFFFFFF
+#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
+#define TIMG_T0_LOAD_V 0xFFFFFFFF
+#define TIMG_T0_LOAD_S 0
+
+#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024)
+/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: When set timer 1 time-base counter is enabled*/
+#define TIMG_T1_EN (BIT(31))
+#define TIMG_T1_EN_M (BIT(31))
+#define TIMG_T1_EN_V 0x1
+#define TIMG_T1_EN_S 31
+/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: When set timer 1 time-base counter increment. When cleared timer
+ 1 time-base counter decrement.*/
+#define TIMG_T1_INCREASE (BIT(30))
+#define TIMG_T1_INCREASE_M (BIT(30))
+#define TIMG_T1_INCREASE_V 0x1
+#define TIMG_T1_INCREASE_S 30
+/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
+/*description: When set timer 1 auto-reload at alarming is enabled*/
+#define TIMG_T1_AUTORELOAD (BIT(29))
+#define TIMG_T1_AUTORELOAD_M (BIT(29))
+#define TIMG_T1_AUTORELOAD_V 0x1
+#define TIMG_T1_AUTORELOAD_S 29
+/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
+/*description: Timer 1 clock (T1_clk) prescale value.*/
+#define TIMG_T1_DIVIDER 0x0000FFFF
+#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S))
+#define TIMG_T1_DIVIDER_V 0xFFFF
+#define TIMG_T1_DIVIDER_S 13
+/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: When set edge type interrupt will be generated during alarm*/
+#define TIMG_T1_EDGE_INT_EN (BIT(12))
+#define TIMG_T1_EDGE_INT_EN_M (BIT(12))
+#define TIMG_T1_EDGE_INT_EN_V 0x1
+#define TIMG_T1_EDGE_INT_EN_S 12
+/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: When set level type interrupt will be generated during alarm*/
+#define TIMG_T1_LEVEL_INT_EN (BIT(11))
+#define TIMG_T1_LEVEL_INT_EN_M (BIT(11))
+#define TIMG_T1_LEVEL_INT_EN_V 0x1
+#define TIMG_T1_LEVEL_INT_EN_S 11
+/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: When set alarm is enabled*/
+#define TIMG_T1_ALARM_EN (BIT(10))
+#define TIMG_T1_ALARM_EN_M (BIT(10))
+#define TIMG_T1_ALARM_EN_V 0x1
+#define TIMG_T1_ALARM_EN_S 10
+
+#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028)
+/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Register to store timer 1 time-base counter current value lower 32 bits.*/
+#define TIMG_T1_LO 0xFFFFFFFF
+#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
+#define TIMG_T1_LO_V 0xFFFFFFFF
+#define TIMG_T1_LO_S 0
+
+#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c)
+/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Register to store timer 1 time-base counter current value higher 32 bits.*/
+#define TIMG_T1_HI 0xFFFFFFFF
+#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S))
+#define TIMG_T1_HI_V 0xFFFFFFFF
+#define TIMG_T1_HI_S 0
+
+#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030)
+/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Write any value will trigger a timer 1 time-base counter value
+ update (timer 1 current value will be stored in registers above)*/
+#define TIMG_T1_UPDATE 0xFFFFFFFF
+#define TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S))
+#define TIMG_T1_UPDATE_V 0xFFFFFFFF
+#define TIMG_T1_UPDATE_S 0
+
+#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034)
+/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm*/
+#define TIMG_T1_ALARM_LO 0xFFFFFFFF
+#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S))
+#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF
+#define TIMG_T1_ALARM_LO_S 0
+
+#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038)
+/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm*/
+#define TIMG_T1_ALARM_HI 0xFFFFFFFF
+#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S))
+#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF
+#define TIMG_T1_ALARM_HI_S 0
+
+#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c)
+/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Lower 32 bits of the value that will load into timer 1 time-base counter*/
+#define TIMG_T1_LOAD_LO 0xFFFFFFFF
+#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S))
+#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF
+#define TIMG_T1_LOAD_LO_S 0
+
+#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040)
+/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: higher 32 bits of the value that will load into timer 1 time-base counter*/
+#define TIMG_T1_LOAD_HI 0xFFFFFFFF
+#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S))
+#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF
+#define TIMG_T1_LOAD_HI_S 0
+
+#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044)
+/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Write any value will trigger timer 1 time-base counter reload*/
+#define TIMG_T1_LOAD 0xFFFFFFFF
+#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S))
+#define TIMG_T1_LOAD_V 0xFFFFFFFF
+#define TIMG_T1_LOAD_S 0
+
+#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048)
+/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: When set SWDT is enabled*/
+#define TIMG_WDT_EN (BIT(31))
+#define TIMG_WDT_EN_M (BIT(31))
+#define TIMG_WDT_EN_V 0x1
+#define TIMG_WDT_EN_S 31
+/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */
+/*description: Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
+#define TIMG_WDT_STG0 0x00000003
+#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
+#define TIMG_WDT_STG0_V 0x3
+#define TIMG_WDT_STG0_S 29
+/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */
+/*description: Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
+#define TIMG_WDT_STG1 0x00000003
+#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
+#define TIMG_WDT_STG1_V 0x3
+#define TIMG_WDT_STG1_S 27
+/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */
+/*description: Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
+#define TIMG_WDT_STG2 0x00000003
+#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
+#define TIMG_WDT_STG2_V 0x3
+#define TIMG_WDT_STG2_S 25
+/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */
+/*description: Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
+#define TIMG_WDT_STG3 0x00000003
+#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
+#define TIMG_WDT_STG3_V 0x3
+#define TIMG_WDT_STG3_S 23
+/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: When set edge type interrupt generation is enabled*/
+#define TIMG_WDT_EDGE_INT_EN (BIT(22))
+#define TIMG_WDT_EDGE_INT_EN_M (BIT(22))
+#define TIMG_WDT_EDGE_INT_EN_V 0x1
+#define TIMG_WDT_EDGE_INT_EN_S 22
+/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: When set level type interrupt generation is enabled*/
+#define TIMG_WDT_LEVEL_INT_EN (BIT(21))
+#define TIMG_WDT_LEVEL_INT_EN_M (BIT(21))
+#define TIMG_WDT_LEVEL_INT_EN_V 0x1
+#define TIMG_WDT_LEVEL_INT_EN_S 21
+/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
+/*description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns
+ 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
+#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
+#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
+#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
+#define TIMG_WDT_CPU_RESET_LENGTH_S 18
+/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
+/*description: length of system reset selection. 0: 100ns 1: 200ns 2: 300ns
+ 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
+#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007
+#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
+#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7
+#define TIMG_WDT_SYS_RESET_LENGTH_S 15
+/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: When set flash boot protection is enabled*/
+#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1
+#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
+
+#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c)
+/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
+/*description: SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
+#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
+#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
+#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
+#define TIMG_WDT_CLK_PRESCALE_S 16
+
+#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050)
+/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
+/*description: Stage 0 timeout value in SWDT clock cycles*/
+#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF
+#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
+#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF
+#define TIMG_WDT_STG0_HOLD_S 0
+
+#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054)
+/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
+/*description: Stage 1 timeout value in SWDT clock cycles*/
+#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF
+#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
+#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF
+#define TIMG_WDT_STG1_HOLD_S 0
+
+#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058)
+/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
+/*description: Stage 2 timeout value in SWDT clock cycles*/
+#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF
+#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
+#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF
+#define TIMG_WDT_STG2_HOLD_S 0
+
+#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c)
+/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
+/*description: Stage 3 timeout value in SWDT clock cycles*/
+#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF
+#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
+#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF
+#define TIMG_WDT_STG3_HOLD_S 0
+
+#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060)
+/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Write any value will feed SWDT*/
+#define TIMG_WDT_FEED 0xFFFFFFFF
+#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
+#define TIMG_WDT_FEED_V 0xFFFFFFFF
+#define TIMG_WDT_FEED_S 0
+
+#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064)
+/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: If change its value from default then write protection is on.*/
+#define TIMG_WDT_WKEY 0xFFFFFFFF
+#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
+#define TIMG_WDT_WKEY_V 0xFFFFFFFF
+#define TIMG_WDT_WKEY_S 0
+
+#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
+/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_START (BIT(31))
+#define TIMG_RTC_CALI_START_M (BIT(31))
+#define TIMG_RTC_CALI_START_V 0x1
+#define TIMG_RTC_CALI_START_S 31
+/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
+/*description: */
+#define TIMG_RTC_CALI_MAX 0x00007FFF
+#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
+#define TIMG_RTC_CALI_MAX_V 0x7FFF
+#define TIMG_RTC_CALI_MAX_S 16
+/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_RDY (BIT(15))
+#define TIMG_RTC_CALI_RDY_M (BIT(15))
+#define TIMG_RTC_CALI_RDY_V 0x1
+#define TIMG_RTC_CALI_RDY_S 15
+/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
+/*description: */
+#define TIMG_RTC_CALI_CLK_SEL 0x00000003
+#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
+#define TIMG_RTC_CALI_CLK_SEL_V 0x3
+#define TIMG_RTC_CALI_CLK_SEL_S 13
+/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: */
+#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_V 0x1
+#define TIMG_RTC_CALI_START_CYCLING_S 12
+
+#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
+/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_VALUE 0x01FFFFFF
+#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
+#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF
+#define TIMG_RTC_CALI_VALUE_S 7
+
+#define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070)
+/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_EN (BIT(31))
+#define TIMG_LACT_EN_M (BIT(31))
+#define TIMG_LACT_EN_V 0x1
+#define TIMG_LACT_EN_S 31
+/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_LACT_INCREASE (BIT(30))
+#define TIMG_LACT_INCREASE_M (BIT(30))
+#define TIMG_LACT_INCREASE_V 0x1
+#define TIMG_LACT_INCREASE_S 30
+/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_LACT_AUTORELOAD (BIT(29))
+#define TIMG_LACT_AUTORELOAD_M (BIT(29))
+#define TIMG_LACT_AUTORELOAD_V 0x1
+#define TIMG_LACT_AUTORELOAD_S 29
+/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
+/*description: */
+#define TIMG_LACT_DIVIDER 0x0000FFFF
+#define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S))
+#define TIMG_LACT_DIVIDER_V 0xFFFF
+#define TIMG_LACT_DIVIDER_S 13
+/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_EDGE_INT_EN (BIT(12))
+#define TIMG_LACT_EDGE_INT_EN_M (BIT(12))
+#define TIMG_LACT_EDGE_INT_EN_V 0x1
+#define TIMG_LACT_EDGE_INT_EN_S 12
+/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_LEVEL_INT_EN (BIT(11))
+#define TIMG_LACT_LEVEL_INT_EN_M (BIT(11))
+#define TIMG_LACT_LEVEL_INT_EN_V 0x1
+#define TIMG_LACT_LEVEL_INT_EN_S 11
+/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_ALARM_EN (BIT(10))
+#define TIMG_LACT_ALARM_EN_M (BIT(10))
+#define TIMG_LACT_ALARM_EN_V 0x1
+#define TIMG_LACT_ALARM_EN_S 10
+/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_LACT_LAC_EN (BIT(9))
+#define TIMG_LACT_LAC_EN_M (BIT(9))
+#define TIMG_LACT_LAC_EN_V 0x1
+#define TIMG_LACT_LAC_EN_S 9
+/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_LACT_CPST_EN (BIT(8))
+#define TIMG_LACT_CPST_EN_M (BIT(8))
+#define TIMG_LACT_CPST_EN_V 0x1
+#define TIMG_LACT_CPST_EN_S 8
+/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_RTC_ONLY (BIT(7))
+#define TIMG_LACT_RTC_ONLY_M (BIT(7))
+#define TIMG_LACT_RTC_ONLY_V 0x1
+#define TIMG_LACT_RTC_ONLY_S 7
+
+#define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074)
+/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */
+/*description: */
+#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF
+#define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S))
+#define TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF
+#define TIMG_LACT_RTC_STEP_LEN_S 6
+
+#define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078)
+/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_LO 0xFFFFFFFF
+#define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S))
+#define TIMG_LACT_LO_V 0xFFFFFFFF
+#define TIMG_LACT_LO_S 0
+
+#define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c)
+/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_HI 0xFFFFFFFF
+#define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S))
+#define TIMG_LACT_HI_V 0xFFFFFFFF
+#define TIMG_LACT_HI_S 0
+
+#define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080)
+/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_UPDATE 0xFFFFFFFF
+#define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S))
+#define TIMG_LACT_UPDATE_V 0xFFFFFFFF
+#define TIMG_LACT_UPDATE_S 0
+
+#define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084)
+/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_ALARM_LO 0xFFFFFFFF
+#define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S))
+#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF
+#define TIMG_LACT_ALARM_LO_S 0
+
+#define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088)
+/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_ALARM_HI 0xFFFFFFFF
+#define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S))
+#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF
+#define TIMG_LACT_ALARM_HI_S 0
+
+#define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c)
+/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_LOAD_LO 0xFFFFFFFF
+#define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S))
+#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF
+#define TIMG_LACT_LOAD_LO_S 0
+
+#define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090)
+/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_LOAD_HI 0xFFFFFFFF
+#define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S))
+#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF
+#define TIMG_LACT_LOAD_HI_S 0
+
+#define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094)
+/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_LOAD 0xFFFFFFFF
+#define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S))
+#define TIMG_LACT_LOAD_V 0xFFFFFFFF
+#define TIMG_LACT_LOAD_S 0
+
+#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098)
+/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_INT_ENA (BIT(3))
+#define TIMG_LACT_INT_ENA_M (BIT(3))
+#define TIMG_LACT_INT_ENA_V 0x1
+#define TIMG_LACT_INT_ENA_S 3
+/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Interrupt when an interrupt stage timeout*/
+#define TIMG_WDT_INT_ENA (BIT(2))
+#define TIMG_WDT_INT_ENA_M (BIT(2))
+#define TIMG_WDT_INT_ENA_V 0x1
+#define TIMG_WDT_INT_ENA_S 2
+/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: interrupt when timer1 alarm*/
+#define TIMG_T1_INT_ENA (BIT(1))
+#define TIMG_T1_INT_ENA_M (BIT(1))
+#define TIMG_T1_INT_ENA_V 0x1
+#define TIMG_T1_INT_ENA_S 1
+/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: interrupt when timer0 alarm*/
+#define TIMG_T0_INT_ENA (BIT(0))
+#define TIMG_T0_INT_ENA_M (BIT(0))
+#define TIMG_T0_INT_ENA_V 0x1
+#define TIMG_T0_INT_ENA_S 0
+
+#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c)
+/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_INT_RAW (BIT(3))
+#define TIMG_LACT_INT_RAW_M (BIT(3))
+#define TIMG_LACT_INT_RAW_V 0x1
+#define TIMG_LACT_INT_RAW_S 3
+/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Interrupt when an interrupt stage timeout*/
+#define TIMG_WDT_INT_RAW (BIT(2))
+#define TIMG_WDT_INT_RAW_M (BIT(2))
+#define TIMG_WDT_INT_RAW_V 0x1
+#define TIMG_WDT_INT_RAW_S 2
+/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: interrupt when timer1 alarm*/
+#define TIMG_T1_INT_RAW (BIT(1))
+#define TIMG_T1_INT_RAW_M (BIT(1))
+#define TIMG_T1_INT_RAW_V 0x1
+#define TIMG_T1_INT_RAW_S 1
+/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: interrupt when timer0 alarm*/
+#define TIMG_T0_INT_RAW (BIT(0))
+#define TIMG_T0_INT_RAW_M (BIT(0))
+#define TIMG_T0_INT_RAW_V 0x1
+#define TIMG_T0_INT_RAW_S 0
+
+#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0)
+/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_INT_ST (BIT(3))
+#define TIMG_LACT_INT_ST_M (BIT(3))
+#define TIMG_LACT_INT_ST_V 0x1
+#define TIMG_LACT_INT_ST_S 3
+/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Interrupt when an interrupt stage timeout*/
+#define TIMG_WDT_INT_ST (BIT(2))
+#define TIMG_WDT_INT_ST_M (BIT(2))
+#define TIMG_WDT_INT_ST_V 0x1
+#define TIMG_WDT_INT_ST_S 2
+/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: interrupt when timer1 alarm*/
+#define TIMG_T1_INT_ST (BIT(1))
+#define TIMG_T1_INT_ST_M (BIT(1))
+#define TIMG_T1_INT_ST_V 0x1
+#define TIMG_T1_INT_ST_S 1
+/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: interrupt when timer0 alarm*/
+#define TIMG_T0_INT_ST (BIT(0))
+#define TIMG_T0_INT_ST_M (BIT(0))
+#define TIMG_T0_INT_ST_V 0x1
+#define TIMG_T0_INT_ST_S 0
+
+#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4)
+/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_INT_CLR (BIT(3))
+#define TIMG_LACT_INT_CLR_M (BIT(3))
+#define TIMG_LACT_INT_CLR_V 0x1
+#define TIMG_LACT_INT_CLR_S 3
+/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Interrupt when an interrupt stage timeout*/
+#define TIMG_WDT_INT_CLR (BIT(2))
+#define TIMG_WDT_INT_CLR_M (BIT(2))
+#define TIMG_WDT_INT_CLR_V 0x1
+#define TIMG_WDT_INT_CLR_S 2
+/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: interrupt when timer1 alarm*/
+#define TIMG_T1_INT_CLR (BIT(1))
+#define TIMG_T1_INT_CLR_M (BIT(1))
+#define TIMG_T1_INT_CLR_V 0x1
+#define TIMG_T1_INT_CLR_S 1
+/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: interrupt when timer0 alarm*/
+#define TIMG_T0_INT_CLR (BIT(0))
+#define TIMG_T0_INT_CLR_M (BIT(0))
+#define TIMG_T0_INT_CLR_V 0x1
+#define TIMG_T0_INT_CLR_S 0
+
+#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8)
+/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; */
+/*description: Version of this regfile*/
+#define TIMG_NTIMERS_DATE 0x0FFFFFFF
+#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
+#define TIMG_NTIMERS_DATE_V 0xFFFFFFF
+#define TIMG_NTIMERS_DATE_S 0
+
+#define TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc)
+/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Force clock enable for this regfile*/
+#define TIMG_CLK_EN (BIT(31))
+#define TIMG_CLK_EN_M (BIT(31))
+#define TIMG_CLK_EN_V 0x1
+#define TIMG_CLK_EN_S 31
+
+
+
+
+#endif /*__TIMG_REG_H__ */
+
+
+++ /dev/null
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_TIMERS_REG_H_
-#define _SOC_TIMER_REG_H_
-
-#include "soc.h"
-
-#define T0CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0000)
-#define TIMERS_T0_EN (BIT(31))
-#define TIMERS_T0_EN_S 31
-#define TIMERS_T0_INCREASE (BIT(30))
-#define TIMERS_T0_INCREASE_S 30
-#define TIMERS_T0_AUTORELOAD (BIT(29))
-#define TIMERS_T0_AUTORELOAD_S 29
-#define TIMERS_T0_DIVIDER 0x0000FFFF
-#define TIMERS_T0_DIVIDER_S 13
-#define TIMERS_T0_EDGE_INT_EN (BIT(12))
-#define TIMERS_T0_EDGE_INT_EN_S 12
-#define TIMERS_T0_LEVEL_INT_EN (BIT(11))
-#define TIMERS_T0_LEVEL_INT_EN_S 11
-#define TIMERS_T0_ALARM_EN (BIT(10))
-#define TIMERS_T0_ALARM_EN_S 10
-
-#define T0LO(i) (DR_REG_TIMERS_BASE(i) + 0x0004)
-#define TIMERS_T0_LO 0xFFFFFFFF
-#define TIMERS_T0_LO_S 0
-
-#define T0HI(i) (DR_REG_TIMERS_BASE(i) + 0x0008)
-#define TIMERS_T0_HI 0xFFFFFFFF
-#define TIMERS_T0_HI_S 0
-
-#define T0UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x000c)
-#define TIMERS_T0_UPDATE 0xFFFFFFFF
-#define TIMERS_T0_UPDATE_S 0
-
-#define T0ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0010)
-#define TIMERS_T0_ALARM_LO 0xFFFFFFFF
-#define TIMERS_T0_ALARM_LO_S 0
-
-#define T0ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0014)
-#define TIMERS_T0_ALARM_HI 0xFFFFFFFF
-#define TIMERS_T0_ALARM_HI_S 0
-
-#define T0LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x0018)
-#define TIMERS_T0_LOAD_LO 0xFFFFFFFF
-#define TIMERS_T0_LOAD_LO_S 0
-
-#define T0LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x001c)
-#define TIMERS_T0_LOAD_HI 0xFFFFFFFF
-#define TIMERS_T0_LOAD_HI_S 0
-
-#define T0LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0020)
-#define TIMERS_T0_LOAD 0xFFFFFFFF
-#define TIMERS_T0_LOAD_S 0
-
-#define T1CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0024)
-#define TIMERS_T1_EN (BIT(31))
-#define TIMERS_T1_EN_S 31
-#define TIMERS_T1_INCREASE (BIT(30))
-#define TIMERS_T1_INCREASE_S 30
-#define TIMERS_T1_AUTORELOAD (BIT(29))
-#define TIMERS_T1_AUTORELOAD_S 29
-#define TIMERS_T1_DIVIDER 0x0000FFFF
-#define TIMERS_T1_DIVIDER_S 13
-#define TIMERS_T1_EDGE_INT_EN (BIT(12))
-#define TIMERS_T1_EDGE_INT_EN_S 12
-#define TIMERS_T1_LEVEL_INT_EN (BIT(11))
-#define TIMERS_T1_LEVEL_INT_EN_S 11
-#define TIMERS_T1_ALARM_EN (BIT(10))
-#define TIMERS_T1_ALARM_EN_S 10
-
-#define T1LO(i) (DR_REG_TIMERS_BASE(i) + 0x0028)
-#define TIMERS_T1_LO 0xFFFFFFFF
-#define TIMERS_T1_LO_S 0
-
-#define T1HI(i) (DR_REG_TIMERS_BASE(i) + 0x002c)
-#define TIMERS_T1_HI 0xFFFFFFFF
-#define TIMERS_T1_HI_S 0
-
-#define T1UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0030)
-#define TIMERS_T1_UPDATE 0xFFFFFFFF
-#define TIMERS_T1_UPDATE_S 0
-
-#define T1ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0034)
-#define TIMERS_T1_ALARM_LO 0xFFFFFFFF
-#define TIMERS_T1_ALARM_LO_S 0
-
-#define T1ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0038)
-#define TIMERS_T1_ALARM_HI 0xFFFFFFFF
-#define TIMERS_T1_ALARM_HI_S 0
-
-#define T1LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x003c)
-#define TIMERS_T1_LOAD_LO 0xFFFFFFFF
-#define TIMERS_T1_LOAD_LO_S 0
-
-#define T1LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0040)
-#define TIMERS_T1_LOAD_HI 0xFFFFFFFF
-#define TIMERS_T1_LOAD_HI_S 0
-
-#define T1LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0044)
-#define TIMERS_T1_LOAD 0xFFFFFFFF
-#define TIMERS_T1_LOAD_S 0
-
-#define WDTCONFIG0(i) (DR_REG_TIMERS_BASE(i) + 0x0048)
-#define TIMERS_WDT_EN (BIT(31))
-#define TIMERS_WDT_EN_S 31
-#define TIMERS_WDT_STG0 0x00000003
-#define TIMERS_WDT_STG0_S 29
-#define TIMERS_WDT_STG1 0x00000003
-#define TIMERS_WDT_STG1_S 27
-#define TIMERS_WDT_STG2 0x00000003
-#define TIMERS_WDT_STG2_S 25
-#define TIMERS_WDT_STG3 0x00000003
-#define TIMERS_WDT_STG3_S 23
-#define TIMERS_WDT_EDGE_INT_EN (BIT(22))
-#define TIMERS_WDT_EDGE_INT_EN_S 22
-#define TIMERS_WDT_LEVEL_INT_EN (BIT(21))
-#define TIMERS_WDT_LEVEL_INT_EN_S 21
-#define TIMERS_WDT_CPU_RESET_LENGTH 0x00000007
-#define TIMERS_WDT_CPU_RESET_LENGTH_S 18
-#define TIMERS_WDT_SYS_RESET_LENGTH 0x00000007
-#define TIMERS_WDT_SYS_RESET_LENGTH_S 15
-#define TIMERS_WDT_FLASHBOOT_MOD_EN (BIT(14))
-#define TIMERS_WDT_FLASHBOOT_MOD_EN_S 14
-
-#define WDTCONFIG1(i) (DR_REG_TIMERS_BASE(i) + 0x004c)
-#define TIMERS_WDT_CLK_PRESCALE 0x0000FFFF
-#define TIMERS_WDT_CLK_PRESCALE_S 16
-
-#define WDTCONFIG2(i) (DR_REG_TIMERS_BASE(i) + 0x0050)
-#define TIMERS_WDT_STG0_HOLD 0xFFFFFFFF
-#define TIMERS_WDT_STG0_HOLD_S 0
-
-#define WDTCONFIG3(i) (DR_REG_TIMERS_BASE(i) + 0x0054)
-#define TIMERS_WDT_STG1_HOLD 0xFFFFFFFF
-#define TIMERS_WDT_STG1_HOLD_S 0
-
-#define WDTCONFIG4(i) (DR_REG_TIMERS_BASE(i) + 0x0058)
-#define TIMERS_WDT_STG2_HOLD 0xFFFFFFFF
-#define TIMERS_WDT_STG2_HOLD_S 0
-
-#define WDTCONFIG5(i) (DR_REG_TIMERS_BASE(i) + 0x005c)
-#define TIMERS_WDT_STG3_HOLD 0xFFFFFFFF
-#define TIMERS_WDT_STG3_HOLD_S 0
-
-#define WDTFEED(i) (DR_REG_TIMERS_BASE(i) + 0x0060)
-#define TIMERS_WDT_FEED 0xFFFFFFFF
-#define TIMERS_WDT_FEED_S 0
-
-#define WDTWPROTECT(i) (DR_REG_TIMERS_BASE(i) + 0x0064)
-#define TIMERS_WDT_WKEY 0xFFFFFFFF
-#define TIMERS_WDT_WKEY_S 0
-
-#define RTCCALICFG(i) (DR_REG_TIMERS_BASE(i) + 0x0068)
-#define TIMERS_RTC_CALI_START (BIT(31))
-#define TIMERS_RTC_CALI_START_S 31
-#define TIMERS_RTC_CALI_MAX 0x00007FFF
-#define TIMERS_RTC_CALI_MAX_S 16
-#define TIMERS_RTC_CALI_RDY (BIT(15))
-#define TIMERS_RTC_CALI_RDY_S 15
-#define TIMERS_RTC_CALI_CLK_SEL 0x00000003
-#define TIMERS_RTC_CALI_CLK_SEL_S 13
-#define TIMERS_RTC_CALI_START_CYCLING (BIT(12))
-#define TIMERS_RTC_CALI_START_CYCLING_S 12
-
-#define RTCCALICFG1(i) (DR_REG_TIMERS_BASE(i) + 0x006c)
-#define TIMERS_RTC_CALI_VALUE 0x01FFFFFF
-#define TIMERS_RTC_CALI_VALUE_S 7
-
-#define LACTCONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0070)
-#define TIMERS_LACT_EN (BIT(31))
-#define TIMERS_LACT_EN_S 31
-#define TIMERS_LACT_INCREASE (BIT(30))
-#define TIMERS_LACT_INCREASE_S 30
-#define TIMERS_LACT_AUTORELOAD (BIT(29))
-#define TIMERS_LACT_AUTORELOAD_S 29
-#define TIMERS_LACT_DIVIDER 0x0000FFFF
-#define TIMERS_LACT_DIVIDER_S 13
-#define TIMERS_LACT_EDGE_INT_EN (BIT(12))
-#define TIMERS_LACT_EDGE_INT_EN_S 12
-#define TIMERS_LACT_LEVEL_INT_EN (BIT(11))
-#define TIMERS_LACT_LEVEL_INT_EN_S 11
-#define TIMERS_LACT_ALARM_EN (BIT(10))
-#define TIMERS_LACT_ALARM_EN_S 10
-#define TIMERS_LACT_LAC_EN (BIT(9))
-#define TIMERS_LACT_LAC_EN_S 9
-#define TIMERS_LACT_CPST_EN (BIT(8))
-#define TIMERS_LACT_CPST_EN_S 8
-#define TIMERS_LACT_RTC_ONLY (BIT(7))
-#define TIMERS_LACT_RTC_ONLY_S 7
-
-#define LACTRTC(i) (DR_REG_TIMERS_BASE(i) + 0x0074)
-#define TIMERS_LACT_RTC_STEP_LEN 0x03FFFFFF
-#define TIMERS_LACT_RTC_STEP_LEN_S 6
-
-#define LACTLO(i) (DR_REG_TIMERS_BASE(i) + 0x0078)
-#define TIMERS_LACT_LO 0xFFFFFFFF
-#define TIMERS_LACT_LO_S 0
-
-#define LACTHI(i) (DR_REG_TIMERS_BASE(i) + 0x007c)
-#define TIMERS_LACT_HI 0xFFFFFFFF
-#define TIMERS_LACT_HI_S 0
-
-#define LACTUPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0080)
-#define TIMERS_LACT_UPDATE 0xFFFFFFFF
-#define TIMERS_LACT_UPDATE_S 0
-
-#define LACTALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0084)
-#define TIMERS_LACT_ALARM_LO 0xFFFFFFFF
-#define TIMERS_LACT_ALARM_LO_S 0
-
-#define LACTALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0088)
-#define TIMERS_LACT_ALARM_HI 0xFFFFFFFF
-#define TIMERS_LACT_ALARM_HI_S 0
-
-#define LACTLOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x008c)
-#define TIMERS_LACT_LOAD_LO 0xFFFFFFFF
-#define TIMERS_LACT_LOAD_LO_S 0
-
-#define LACTLOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0090)
-#define TIMERS_LACT_LOAD_HI 0xFFFFFFFF
-#define TIMERS_LACT_LOAD_HI_S 0
-
-#define LACTLOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0094)
-#define TIMERS_LACT_LOAD 0xFFFFFFFF
-#define TIMERS_LACT_LOAD_S 0
-
-#define INT_ENA_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x0098)
-#define TIMERS_LACT_INT_ENA (BIT(3))
-#define TIMERS_LACT_INT_ENA_S 3
-#define TIMERS_WDT_INT_ENA (BIT(2))
-#define TIMERS_WDT_INT_ENA_S 2
-#define TIMERS_T1_INT_ENA (BIT(1))
-#define TIMERS_T1_INT_ENA_S 1
-#define TIMERS_T0_INT_ENA (BIT(0))
-#define TIMERS_T0_INT_ENA_S 0
-
-#define INT_RAW_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x009c)
-#define TIMERS_LACT_INT_RAW (BIT(3))
-#define TIMERS_LACT_INT_RAW_S 3
-#define TIMERS_WDT_INT_RAW (BIT(2))
-#define TIMERS_WDT_INT_RAW_S 2
-#define TIMERS_T1_INT_RAW (BIT(1))
-#define TIMERS_T1_INT_RAW_S 1
-#define TIMERS_T0_INT_RAW (BIT(0))
-#define TIMERS_T0_INT_RAW_S 0
-
-#define INT_ST_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a0)
-#define TIMERS_LACT_INT_ST (BIT(3))
-#define TIMERS_LACT_INT_ST_S 3
-#define TIMERS_WDT_INT_ST (BIT(2))
-#define TIMERS_WDT_INT_ST_S 2
-#define TIMERS_T1_INT_ST (BIT(1))
-#define TIMERS_T1_INT_ST_S 1
-#define TIMERS_T0_INT_ST (BIT(0))
-#define TIMERS_T0_INT_ST_S 0
-
-#define INT_CLR_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a4)
-#define TIMERS_LACT_INT_CLR (BIT(3))
-#define TIMERS_LACT_INT_CLR_S 3
-#define TIMERS_WDT_INT_CLR (BIT(2))
-#define TIMERS_WDT_INT_CLR_S 2
-#define TIMERS_T1_INT_CLR (BIT(1))
-#define TIMERS_T1_INT_CLR_S 1
-#define TIMERS_T0_INT_CLR (BIT(0))
-#define TIMERS_T0_INT_CLR_S 0
-
-#define NTIMERS_DATE(i) (DR_REG_TIMERS_BASE(i) + 0x00f8)
-#define TIMERS_NTIMERS_DATE 0x0FFFFFFF
-#define TIMERS_NTIMERS_DATE_S 0
-#define TIMERS_NTIMERS_DATE_VERSION 0x1604290
-
-#define REGCLK(i) (DR_REG_TIMERS_BASE(i) + 0x00fc)
-#define TIMERS_CLK_EN (BIT(31))
-#define TIMERS_CLK_EN_S 31
-
-#endif /* _SOC_TIMER_REG_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef __UART_REG_H__\r
+#define __UART_REG_H__\r
+\r
+\r
+#include "soc.h"\r
+\r
+#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( i > 1 ? 0xe000 : 0 ) )\r
+\r
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)\r
+/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */\r
+/*description: This register stores one byte data read by rx fifo.*/\r
+#define UART_RXFIFO_RD_BYTE 0x000000FF\r
+#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))\r
+#define UART_RXFIFO_RD_BYTE_V 0xFF\r
+#define UART_RXFIFO_RD_BYTE_S 0\r
+\r
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)\r
+/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver detects\r
+ the configured at_cmd chars.*/\r
+#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))\r
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))\r
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1\r
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18\r
+/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when rs485 detects\r
+ the clash between transmitter and receiver.*/\r
+#define UART_RS485_CLASH_INT_RAW (BIT(17))\r
+#define UART_RS485_CLASH_INT_RAW_M (BIT(17))\r
+#define UART_RS485_CLASH_INT_RAW_V 0x1\r
+#define UART_RS485_CLASH_INT_RAW_S 17\r
+/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when rs485 detects\r
+ the data frame error.*/\r
+#define UART_RS485_FRM_ERR_INT_RAW (BIT(16))\r
+#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))\r
+#define UART_RS485_FRM_ERR_INT_RAW_V 0x1\r
+#define UART_RS485_FRM_ERR_INT_RAW_S 16\r
+/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/\r
+#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))\r
+#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))\r
+#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1\r
+#define UART_RS485_PARITY_ERR_INT_RAW_S 15\r
+/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when transmitter has\r
+ send all the data in fifo.*/\r
+#define UART_TX_DONE_INT_RAW (BIT(14))\r
+#define UART_TX_DONE_INT_RAW_M (BIT(14))\r
+#define UART_TX_DONE_INT_RAW_V 0x1\r
+#define UART_TX_DONE_INT_RAW_S 14\r
+/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when transmitter has\r
+ kept the shortest duration after the last data has been send.*/\r
+#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13))\r
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13))\r
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1\r
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13\r
+/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when transmitter completes\r
+ sendding 0 after all the datas in transmitter's fifo are send.*/\r
+#define UART_TX_BRK_DONE_INT_RAW (BIT(12))\r
+#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12))\r
+#define UART_TX_BRK_DONE_INT_RAW_V 0x1\r
+#define UART_TX_BRK_DONE_INT_RAW_S 12\r
+/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/\r
+#define UART_GLITCH_DET_INT_RAW (BIT(11))\r
+#define UART_GLITCH_DET_INT_RAW_M (BIT(11))\r
+#define UART_GLITCH_DET_INT_RAW_V 0x1\r
+#define UART_GLITCH_DET_INT_RAW_S 11\r
+/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver receives\r
+ xon char with uart_sw_flow_con_en is set to 1.*/\r
+#define UART_SW_XOFF_INT_RAW (BIT(10))\r
+#define UART_SW_XOFF_INT_RAW_M (BIT(10))\r
+#define UART_SW_XOFF_INT_RAW_V 0x1\r
+#define UART_SW_XOFF_INT_RAW_S 10\r
+/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver recevies\r
+ xoff char with uart_sw_flow_con_en is set to 1.*/\r
+#define UART_SW_XON_INT_RAW (BIT(9))\r
+#define UART_SW_XON_INT_RAW_M (BIT(9))\r
+#define UART_SW_XON_INT_RAW_V 0x1\r
+#define UART_SW_XON_INT_RAW_S 9\r
+/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver takes\r
+ more time than rx_tout_thrhd to receive a byte.*/\r
+#define UART_RXFIFO_TOUT_INT_RAW (BIT(8))\r
+#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8))\r
+#define UART_RXFIFO_TOUT_INT_RAW_V 0x1\r
+#define UART_RXFIFO_TOUT_INT_RAW_S 8\r
+/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver detects\r
+ the 0 after the stop bit.*/\r
+#define UART_BRK_DET_INT_RAW (BIT(7))\r
+#define UART_BRK_DET_INT_RAW_M (BIT(7))\r
+#define UART_BRK_DET_INT_RAW_V 0x1\r
+#define UART_BRK_DET_INT_RAW_S 7\r
+/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver detects\r
+ the edge change of ctsn signal.*/\r
+#define UART_CTS_CHG_INT_RAW (BIT(6))\r
+#define UART_CTS_CHG_INT_RAW_M (BIT(6))\r
+#define UART_CTS_CHG_INT_RAW_V 0x1\r
+#define UART_CTS_CHG_INT_RAW_S 6\r
+/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver detects\r
+ the edge change of dsrn signal.*/\r
+#define UART_DSR_CHG_INT_RAW (BIT(5))\r
+#define UART_DSR_CHG_INT_RAW_M (BIT(5))\r
+#define UART_DSR_CHG_INT_RAW_V 0x1\r
+#define UART_DSR_CHG_INT_RAW_S 5\r
+/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver receives\r
+ more data than the fifo can store.*/\r
+#define UART_RXFIFO_OVF_INT_RAW (BIT(4))\r
+#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4))\r
+#define UART_RXFIFO_OVF_INT_RAW_V 0x1\r
+#define UART_RXFIFO_OVF_INT_RAW_S 4\r
+/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver detects\r
+ data's frame error .*/\r
+#define UART_FRM_ERR_INT_RAW (BIT(3))\r
+#define UART_FRM_ERR_INT_RAW_M (BIT(3))\r
+#define UART_FRM_ERR_INT_RAW_V 0x1\r
+#define UART_FRM_ERR_INT_RAW_S 3\r
+/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver detects\r
+ the parity error of data.*/\r
+#define UART_PARITY_ERR_INT_RAW (BIT(2))\r
+#define UART_PARITY_ERR_INT_RAW_M (BIT(2))\r
+#define UART_PARITY_ERR_INT_RAW_V 0x1\r
+#define UART_PARITY_ERR_INT_RAW_S 2\r
+/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when the amount of\r
+ data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/\r
+#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1))\r
+#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1))\r
+#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1\r
+#define UART_TXFIFO_EMPTY_INT_RAW_S 1\r
+/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This interrupt raw bit turns to high level when receiver receives\r
+ more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/\r
+#define UART_RXFIFO_FULL_INT_RAW (BIT(0))\r
+#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0))\r
+#define UART_RXFIFO_FULL_INT_RAW_V 0x1\r
+#define UART_RXFIFO_FULL_INT_RAW_S 0\r
+\r
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)\r
+/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena\r
+ is set to 1.*/\r
+#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18))\r
+#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18))\r
+#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1\r
+#define UART_AT_CMD_CHAR_DET_INT_ST_S 18\r
+/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena\r
+ is set to 1.*/\r
+#define UART_RS485_CLASH_INT_ST (BIT(17))\r
+#define UART_RS485_CLASH_INT_ST_M (BIT(17))\r
+#define UART_RS485_CLASH_INT_ST_V 0x1\r
+#define UART_RS485_CLASH_INT_ST_S 17\r
+/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena\r
+ is set to 1.*/\r
+#define UART_RS485_FRM_ERR_INT_ST (BIT(16))\r
+#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16))\r
+#define UART_RS485_FRM_ERR_INT_ST_V 0x1\r
+#define UART_RS485_FRM_ERR_INT_ST_S 16\r
+/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena\r
+ is set to 1.*/\r
+#define UART_RS485_PARITY_ERR_INT_ST (BIT(15))\r
+#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15))\r
+#define UART_RS485_PARITY_ERR_INT_ST_V 0x1\r
+#define UART_RS485_PARITY_ERR_INT_ST_S 15\r
+/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/\r
+#define UART_TX_DONE_INT_ST (BIT(14))\r
+#define UART_TX_DONE_INT_ST_M (BIT(14))\r
+#define UART_TX_DONE_INT_ST_V 0x1\r
+#define UART_TX_DONE_INT_ST_S 14\r
+/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena\r
+ is set to 1.*/\r
+#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13))\r
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13))\r
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1\r
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13\r
+/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena\r
+ is set to 1.*/\r
+#define UART_TX_BRK_DONE_INT_ST (BIT(12))\r
+#define UART_TX_BRK_DONE_INT_ST_M (BIT(12))\r
+#define UART_TX_BRK_DONE_INT_ST_V 0x1\r
+#define UART_TX_BRK_DONE_INT_ST_S 12\r
+/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena\r
+ is set to 1.*/\r
+#define UART_GLITCH_DET_INT_ST (BIT(11))\r
+#define UART_GLITCH_DET_INT_ST_M (BIT(11))\r
+#define UART_GLITCH_DET_INT_ST_V 0x1\r
+#define UART_GLITCH_DET_INT_ST_S 11\r
+/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/\r
+#define UART_SW_XOFF_INT_ST (BIT(10))\r
+#define UART_SW_XOFF_INT_ST_M (BIT(10))\r
+#define UART_SW_XOFF_INT_ST_V 0x1\r
+#define UART_SW_XOFF_INT_ST_S 10\r
+/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/\r
+#define UART_SW_XON_INT_ST (BIT(9))\r
+#define UART_SW_XON_INT_ST_M (BIT(9))\r
+#define UART_SW_XON_INT_ST_V 0x1\r
+#define UART_SW_XON_INT_ST_S 9\r
+/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena\r
+ is set to 1.*/\r
+#define UART_RXFIFO_TOUT_INT_ST (BIT(8))\r
+#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8))\r
+#define UART_RXFIFO_TOUT_INT_ST_V 0x1\r
+#define UART_RXFIFO_TOUT_INT_ST_S 8\r
+/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/\r
+#define UART_BRK_DET_INT_ST (BIT(7))\r
+#define UART_BRK_DET_INT_ST_M (BIT(7))\r
+#define UART_BRK_DET_INT_ST_V 0x1\r
+#define UART_BRK_DET_INT_ST_S 7\r
+/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/\r
+#define UART_CTS_CHG_INT_ST (BIT(6))\r
+#define UART_CTS_CHG_INT_ST_M (BIT(6))\r
+#define UART_CTS_CHG_INT_ST_V 0x1\r
+#define UART_CTS_CHG_INT_ST_S 6\r
+/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/\r
+#define UART_DSR_CHG_INT_ST (BIT(5))\r
+#define UART_DSR_CHG_INT_ST_M (BIT(5))\r
+#define UART_DSR_CHG_INT_ST_V 0x1\r
+#define UART_DSR_CHG_INT_ST_S 5\r
+/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena\r
+ is set to 1.*/\r
+#define UART_RXFIFO_OVF_INT_ST (BIT(4))\r
+#define UART_RXFIFO_OVF_INT_ST_M (BIT(4))\r
+#define UART_RXFIFO_OVF_INT_ST_V 0x1\r
+#define UART_RXFIFO_OVF_INT_ST_S 4\r
+/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/\r
+#define UART_FRM_ERR_INT_ST (BIT(3))\r
+#define UART_FRM_ERR_INT_ST_M (BIT(3))\r
+#define UART_FRM_ERR_INT_ST_V 0x1\r
+#define UART_FRM_ERR_INT_ST_S 3\r
+/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena\r
+ is set to 1.*/\r
+#define UART_PARITY_ERR_INT_ST (BIT(2))\r
+#define UART_PARITY_ERR_INT_ST_M (BIT(2))\r
+#define UART_PARITY_ERR_INT_ST_V 0x1\r
+#define UART_PARITY_ERR_INT_ST_S 2\r
+/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena\r
+ is set to 1.*/\r
+#define UART_TXFIFO_EMPTY_INT_ST (BIT(1))\r
+#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1))\r
+#define UART_TXFIFO_EMPTY_INT_ST_V 0x1\r
+#define UART_TXFIFO_EMPTY_INT_ST_S 1\r
+/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena\r
+ is set to 1.*/\r
+#define UART_RXFIFO_FULL_INT_ST (BIT(0))\r
+#define UART_RXFIFO_FULL_INT_ST_M (BIT(0))\r
+#define UART_RXFIFO_FULL_INT_ST_V 0x1\r
+#define UART_RXFIFO_FULL_INT_ST_S 0\r
+\r
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC)\r
+/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for at_cmd_char_det_int_st register.*/\r
+#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18))\r
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18))\r
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1\r
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18\r
+/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for rs485_clash_int_st register.*/\r
+#define UART_RS485_CLASH_INT_ENA (BIT(17))\r
+#define UART_RS485_CLASH_INT_ENA_M (BIT(17))\r
+#define UART_RS485_CLASH_INT_ENA_V 0x1\r
+#define UART_RS485_CLASH_INT_ENA_S 17\r
+/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for rs485_parity_err_int_st register.*/\r
+#define UART_RS485_FRM_ERR_INT_ENA (BIT(16))\r
+#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16))\r
+#define UART_RS485_FRM_ERR_INT_ENA_V 0x1\r
+#define UART_RS485_FRM_ERR_INT_ENA_S 16\r
+/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for rs485_parity_err_int_st register.*/\r
+#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15))\r
+#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15))\r
+#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1\r
+#define UART_RS485_PARITY_ERR_INT_ENA_S 15\r
+/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for tx_done_int_st register.*/\r
+#define UART_TX_DONE_INT_ENA (BIT(14))\r
+#define UART_TX_DONE_INT_ENA_M (BIT(14))\r
+#define UART_TX_DONE_INT_ENA_V 0x1\r
+#define UART_TX_DONE_INT_ENA_S 14\r
+/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/\r
+#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13))\r
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13))\r
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1\r
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13\r
+/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for tx_brk_done_int_st register.*/\r
+#define UART_TX_BRK_DONE_INT_ENA (BIT(12))\r
+#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12))\r
+#define UART_TX_BRK_DONE_INT_ENA_V 0x1\r
+#define UART_TX_BRK_DONE_INT_ENA_S 12\r
+/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for glitch_det_int_st register.*/\r
+#define UART_GLITCH_DET_INT_ENA (BIT(11))\r
+#define UART_GLITCH_DET_INT_ENA_M (BIT(11))\r
+#define UART_GLITCH_DET_INT_ENA_V 0x1\r
+#define UART_GLITCH_DET_INT_ENA_S 11\r
+/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for sw_xoff_int_st register.*/\r
+#define UART_SW_XOFF_INT_ENA (BIT(10))\r
+#define UART_SW_XOFF_INT_ENA_M (BIT(10))\r
+#define UART_SW_XOFF_INT_ENA_V 0x1\r
+#define UART_SW_XOFF_INT_ENA_S 10\r
+/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for sw_xon_int_st register.*/\r
+#define UART_SW_XON_INT_ENA (BIT(9))\r
+#define UART_SW_XON_INT_ENA_M (BIT(9))\r
+#define UART_SW_XON_INT_ENA_V 0x1\r
+#define UART_SW_XON_INT_ENA_S 9\r
+/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for rxfifo_tout_int_st register.*/\r
+#define UART_RXFIFO_TOUT_INT_ENA (BIT(8))\r
+#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8))\r
+#define UART_RXFIFO_TOUT_INT_ENA_V 0x1\r
+#define UART_RXFIFO_TOUT_INT_ENA_S 8\r
+/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for brk_det_int_st register.*/\r
+#define UART_BRK_DET_INT_ENA (BIT(7))\r
+#define UART_BRK_DET_INT_ENA_M (BIT(7))\r
+#define UART_BRK_DET_INT_ENA_V 0x1\r
+#define UART_BRK_DET_INT_ENA_S 7\r
+/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for cts_chg_int_st register.*/\r
+#define UART_CTS_CHG_INT_ENA (BIT(6))\r
+#define UART_CTS_CHG_INT_ENA_M (BIT(6))\r
+#define UART_CTS_CHG_INT_ENA_V 0x1\r
+#define UART_CTS_CHG_INT_ENA_S 6\r
+/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for dsr_chg_int_st register.*/\r
+#define UART_DSR_CHG_INT_ENA (BIT(5))\r
+#define UART_DSR_CHG_INT_ENA_M (BIT(5))\r
+#define UART_DSR_CHG_INT_ENA_V 0x1\r
+#define UART_DSR_CHG_INT_ENA_S 5\r
+/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for rxfifo_ovf_int_st register.*/\r
+#define UART_RXFIFO_OVF_INT_ENA (BIT(4))\r
+#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4))\r
+#define UART_RXFIFO_OVF_INT_ENA_V 0x1\r
+#define UART_RXFIFO_OVF_INT_ENA_S 4\r
+/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for frm_err_int_st register.*/\r
+#define UART_FRM_ERR_INT_ENA (BIT(3))\r
+#define UART_FRM_ERR_INT_ENA_M (BIT(3))\r
+#define UART_FRM_ERR_INT_ENA_V 0x1\r
+#define UART_FRM_ERR_INT_ENA_S 3\r
+/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for parity_err_int_st register.*/\r
+#define UART_PARITY_ERR_INT_ENA (BIT(2))\r
+#define UART_PARITY_ERR_INT_ENA_M (BIT(2))\r
+#define UART_PARITY_ERR_INT_ENA_V 0x1\r
+#define UART_PARITY_ERR_INT_ENA_S 2\r
+/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for rxfifo_full_int_st register.*/\r
+#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1))\r
+#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1))\r
+#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1\r
+#define UART_TXFIFO_EMPTY_INT_ENA_S 1\r
+/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for rxfifo_full_int_st register.*/\r
+#define UART_RXFIFO_FULL_INT_ENA (BIT(0))\r
+#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0))\r
+#define UART_RXFIFO_FULL_INT_ENA_V 0x1\r
+#define UART_RXFIFO_FULL_INT_ENA_S 0\r
+\r
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)\r
+/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/\r
+#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18))\r
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18))\r
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1\r
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18\r
+/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/\r
+#define UART_RS485_CLASH_INT_CLR (BIT(17))\r
+#define UART_RS485_CLASH_INT_CLR_M (BIT(17))\r
+#define UART_RS485_CLASH_INT_CLR_V 0x1\r
+#define UART_RS485_CLASH_INT_CLR_S 17\r
+/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/\r
+#define UART_RS485_FRM_ERR_INT_CLR (BIT(16))\r
+#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16))\r
+#define UART_RS485_FRM_ERR_INT_CLR_V 0x1\r
+#define UART_RS485_FRM_ERR_INT_CLR_S 16\r
+/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/\r
+#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15))\r
+#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15))\r
+#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1\r
+#define UART_RS485_PARITY_ERR_INT_CLR_S 15\r
+/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the tx_done_int_raw interrupt.*/\r
+#define UART_TX_DONE_INT_CLR (BIT(14))\r
+#define UART_TX_DONE_INT_CLR_M (BIT(14))\r
+#define UART_TX_DONE_INT_CLR_V 0x1\r
+#define UART_TX_DONE_INT_CLR_S 14\r
+/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/\r
+#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13))\r
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13))\r
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1\r
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13\r
+/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/\r
+#define UART_TX_BRK_DONE_INT_CLR (BIT(12))\r
+#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12))\r
+#define UART_TX_BRK_DONE_INT_CLR_V 0x1\r
+#define UART_TX_BRK_DONE_INT_CLR_S 12\r
+/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/\r
+#define UART_GLITCH_DET_INT_CLR (BIT(11))\r
+#define UART_GLITCH_DET_INT_CLR_M (BIT(11))\r
+#define UART_GLITCH_DET_INT_CLR_V 0x1\r
+#define UART_GLITCH_DET_INT_CLR_S 11\r
+/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/\r
+#define UART_SW_XOFF_INT_CLR (BIT(10))\r
+#define UART_SW_XOFF_INT_CLR_M (BIT(10))\r
+#define UART_SW_XOFF_INT_CLR_V 0x1\r
+#define UART_SW_XOFF_INT_CLR_S 10\r
+/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/\r
+#define UART_SW_XON_INT_CLR (BIT(9))\r
+#define UART_SW_XON_INT_CLR_M (BIT(9))\r
+#define UART_SW_XON_INT_CLR_V 0x1\r
+#define UART_SW_XON_INT_CLR_S 9\r
+/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/\r
+#define UART_RXFIFO_TOUT_INT_CLR (BIT(8))\r
+#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8))\r
+#define UART_RXFIFO_TOUT_INT_CLR_V 0x1\r
+#define UART_RXFIFO_TOUT_INT_CLR_S 8\r
+/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the brk_det_int_raw interrupt.*/\r
+#define UART_BRK_DET_INT_CLR (BIT(7))\r
+#define UART_BRK_DET_INT_CLR_M (BIT(7))\r
+#define UART_BRK_DET_INT_CLR_V 0x1\r
+#define UART_BRK_DET_INT_CLR_S 7\r
+/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/\r
+#define UART_CTS_CHG_INT_CLR (BIT(6))\r
+#define UART_CTS_CHG_INT_CLR_M (BIT(6))\r
+#define UART_CTS_CHG_INT_CLR_V 0x1\r
+#define UART_CTS_CHG_INT_CLR_S 6\r
+/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/\r
+#define UART_DSR_CHG_INT_CLR (BIT(5))\r
+#define UART_DSR_CHG_INT_CLR_M (BIT(5))\r
+#define UART_DSR_CHG_INT_CLR_V 0x1\r
+#define UART_DSR_CHG_INT_CLR_S 5\r
+/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/\r
+#define UART_RXFIFO_OVF_INT_CLR (BIT(4))\r
+#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4))\r
+#define UART_RXFIFO_OVF_INT_CLR_V 0x1\r
+#define UART_RXFIFO_OVF_INT_CLR_S 4\r
+/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear frm_err_int_raw interrupt.*/\r
+#define UART_FRM_ERR_INT_CLR (BIT(3))\r
+#define UART_FRM_ERR_INT_CLR_M (BIT(3))\r
+#define UART_FRM_ERR_INT_CLR_V 0x1\r
+#define UART_FRM_ERR_INT_CLR_S 3\r
+/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear parity_err_int_raw interrupt.*/\r
+#define UART_PARITY_ERR_INT_CLR (BIT(2))\r
+#define UART_PARITY_ERR_INT_CLR_M (BIT(2))\r
+#define UART_PARITY_ERR_INT_CLR_V 0x1\r
+#define UART_PARITY_ERR_INT_CLR_S 2\r
+/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/\r
+#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1))\r
+#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1))\r
+#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1\r
+#define UART_TXFIFO_EMPTY_INT_CLR_S 1\r
+/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/\r
+#define UART_RXFIFO_FULL_INT_CLR (BIT(0))\r
+#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0))\r
+#define UART_RXFIFO_FULL_INT_CLR_V 0x1\r
+#define UART_RXFIFO_FULL_INT_CLR_S 0\r
+\r
+#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)\r
+/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */\r
+/*description: The register value is the decimal part of the frequency divider's factor.*/\r
+#define UART_CLKDIV_FRAG 0x0000000F\r
+#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))\r
+#define UART_CLKDIV_FRAG_V 0xF\r
+#define UART_CLKDIV_FRAG_S 20\r
+/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */\r
+/*description: The register value is the integer part of the frequency divider's factor.*/\r
+#define UART_CLKDIV 0x000FFFFF\r
+#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S))\r
+#define UART_CLKDIV_V 0xFFFFF\r
+#define UART_CLKDIV_S 0\r
+\r
+#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18)\r
+/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */\r
+/*description: when input pulse width is lower then this value igore this pulse.this\r
+ register is used in autobaud detect process.*/\r
+#define UART_GLITCH_FILT 0x000000FF\r
+#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))\r
+#define UART_GLITCH_FILT_V 0xFF\r
+#define UART_GLITCH_FILT_S 8\r
+/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This is the enable bit for detecting baudrate.*/\r
+#define UART_AUTOBAUD_EN (BIT(0))\r
+#define UART_AUTOBAUD_EN_M (BIT(0))\r
+#define UART_AUTOBAUD_EN_V 0x1\r
+#define UART_AUTOBAUD_EN_S 0\r
+\r
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C)\r
+/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */\r
+/*description: This register represent the level value of the internal uart rxd signal.*/\r
+#define UART_TXD (BIT(31))\r
+#define UART_TXD_M (BIT(31))\r
+#define UART_TXD_V 0x1\r
+#define UART_TXD_S 31\r
+/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */\r
+/*description: This register represent the level value of the internal uart cts signal.*/\r
+#define UART_RTSN (BIT(30))\r
+#define UART_RTSN_M (BIT(30))\r
+#define UART_RTSN_V 0x1\r
+#define UART_RTSN_S 30\r
+/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */\r
+/*description: The register represent the level value of the internal uart dsr signal.*/\r
+#define UART_DTRN (BIT(29))\r
+#define UART_DTRN_M (BIT(29))\r
+#define UART_DTRN_V 0x1\r
+#define UART_DTRN_S 29\r
+/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */\r
+/*description: This register stores the value of transmitter's finite state\r
+ machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/\r
+#define UART_ST_UTX_OUT 0x0000000F\r
+#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))\r
+#define UART_ST_UTX_OUT_V 0xF\r
+#define UART_ST_UTX_OUT_S 24\r
+/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */\r
+/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in\r
+ transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/\r
+#define UART_TXFIFO_CNT 0x000000FF\r
+#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))\r
+#define UART_TXFIFO_CNT_V 0xFF\r
+#define UART_TXFIFO_CNT_S 16\r
+/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: This register stores the level value of the internal uart rxd signal.*/\r
+#define UART_RXD (BIT(15))\r
+#define UART_RXD_M (BIT(15))\r
+#define UART_RXD_V 0x1\r
+#define UART_RXD_S 15\r
+/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: This register stores the level value of the internal uart cts signal.*/\r
+#define UART_CTSN (BIT(14))\r
+#define UART_CTSN_M (BIT(14))\r
+#define UART_CTSN_V 0x1\r
+#define UART_CTSN_S 14\r
+/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: This register stores the level value of the internal uart dsr signal.*/\r
+#define UART_DSRN (BIT(13))\r
+#define UART_DSRN_M (BIT(13))\r
+#define UART_DSRN_V 0x1\r
+#define UART_DSRN_S 13\r
+/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */\r
+/*description: This register stores the value of receiver's finite state machine.\r
+ 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/\r
+#define UART_ST_URX_OUT 0x0000000F\r
+#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))\r
+#define UART_ST_URX_OUT_V 0xF\r
+#define UART_ST_URX_OUT_S 8\r
+/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */\r
+/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in\r
+ receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/\r
+#define UART_RXFIFO_CNT 0x000000FF\r
+#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))\r
+#define UART_RXFIFO_CNT_V 0xFF\r
+#define UART_RXFIFO_CNT_S 0\r
+\r
+#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)\r
+/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */\r
+/*description: This register is used to select the clock.1��apb clock��ref_tick*/\r
+#define UART_TICK_REF_ALWAYS_ON (BIT(27))\r
+#define UART_TICK_REF_ALWAYS_ON_M (BIT(27))\r
+#define UART_TICK_REF_ALWAYS_ON_V 0x1\r
+#define UART_TICK_REF_ALWAYS_ON_S 27\r
+/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
+/*description: 1��receiver stops storing data int fifo when data is wrong.\r
+ 0��receiver stores the data even if the received data is wrong.*/\r
+#define UART_ERR_WR_MASK (BIT(26))\r
+#define UART_ERR_WR_MASK_M (BIT(26))\r
+#define UART_ERR_WR_MASK_V 0x1\r
+#define UART_ERR_WR_MASK_S 26\r
+/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */\r
+/*description: 1��force clock on for registers��support clock only when write registers*/\r
+#define UART_CLK_EN (BIT(25))\r
+#define UART_CLK_EN_M (BIT(25))\r
+#define UART_CLK_EN_V 0x1\r
+#define UART_CLK_EN_S 25\r
+/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */\r
+/*description: Set this bit to inverse the level value of uart dtr signal.*/\r
+#define UART_DTR_INV (BIT(24))\r
+#define UART_DTR_INV_M (BIT(24))\r
+#define UART_DTR_INV_V 0x1\r
+#define UART_DTR_INV_S 24\r
+/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */\r
+/*description: Set this bit to inverse the level value of uart rts signal.*/\r
+#define UART_RTS_INV (BIT(23))\r
+#define UART_RTS_INV_M (BIT(23))\r
+#define UART_RTS_INV_V 0x1\r
+#define UART_RTS_INV_S 23\r
+/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */\r
+/*description: Set this bit to inverse the level value of uart txd signal.*/\r
+#define UART_TXD_INV (BIT(22))\r
+#define UART_TXD_INV_M (BIT(22))\r
+#define UART_TXD_INV_V 0x1\r
+#define UART_TXD_INV_S 22\r
+/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */\r
+/*description: Set this bit to inverse the level value of uart dsr signal.*/\r
+#define UART_DSR_INV (BIT(21))\r
+#define UART_DSR_INV_M (BIT(21))\r
+#define UART_DSR_INV_V 0x1\r
+#define UART_DSR_INV_S 21\r
+/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */\r
+/*description: Set this bit to inverse the level value of uart cts signal.*/\r
+#define UART_CTS_INV (BIT(20))\r
+#define UART_CTS_INV_M (BIT(20))\r
+#define UART_CTS_INV_V 0x1\r
+#define UART_CTS_INV_S 20\r
+/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */\r
+/*description: Set this bit to inverse the level value of uart rxd signal.*/\r
+#define UART_RXD_INV (BIT(19))\r
+#define UART_RXD_INV_M (BIT(19))\r
+#define UART_RXD_INV_V 0x1\r
+#define UART_RXD_INV_S 19\r
+/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset uart transmitter's fifo.*/\r
+#define UART_TXFIFO_RST (BIT(18))\r
+#define UART_TXFIFO_RST_M (BIT(18))\r
+#define UART_TXFIFO_RST_V 0x1\r
+#define UART_TXFIFO_RST_S 18\r
+/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */\r
+/*description: Set this bit to reset uart receiver's fifo.*/\r
+#define UART_RXFIFO_RST (BIT(17))\r
+#define UART_RXFIFO_RST_M (BIT(17))\r
+#define UART_RXFIFO_RST_V 0x1\r
+#define UART_RXFIFO_RST_S 17\r
+/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */\r
+/*description: Set this bit to enable irda protocol.*/\r
+#define UART_IRDA_EN (BIT(16))\r
+#define UART_IRDA_EN_M (BIT(16))\r
+#define UART_IRDA_EN_V 0x1\r
+#define UART_IRDA_EN_S 16\r
+/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable transmitter's flow control function.*/\r
+#define UART_TX_FLOW_EN (BIT(15))\r
+#define UART_TX_FLOW_EN_M (BIT(15))\r
+#define UART_TX_FLOW_EN_V 0x1\r
+#define UART_TX_FLOW_EN_S 15\r
+/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable uart loopback test mode.*/\r
+#define UART_LOOPBACK (BIT(14))\r
+#define UART_LOOPBACK_M (BIT(14))\r
+#define UART_LOOPBACK_V 0x1\r
+#define UART_LOOPBACK_S 14\r
+/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */\r
+/*description: Set this bit to inverse the level value of irda receiver's level.*/\r
+#define UART_IRDA_RX_INV (BIT(13))\r
+#define UART_IRDA_RX_INV_M (BIT(13))\r
+#define UART_IRDA_RX_INV_V 0x1\r
+#define UART_IRDA_RX_INV_S 13\r
+/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
+/*description: Set this bit to inverse the level value of irda transmitter's level.*/\r
+#define UART_IRDA_TX_INV (BIT(12))\r
+#define UART_IRDA_TX_INV_M (BIT(12))\r
+#define UART_IRDA_TX_INV_V 0x1\r
+#define UART_IRDA_TX_INV_S 12\r
+/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */\r
+/*description: 1��the irda transmitter's 11th bit is the same to the 10th bit.\r
+ 0��set irda transmitter's 11th bit to 0.*/\r
+#define UART_IRDA_WCTL (BIT(11))\r
+#define UART_IRDA_WCTL_M (BIT(11))\r
+#define UART_IRDA_WCTL_V 0x1\r
+#define UART_IRDA_WCTL_S 11\r
+/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
+/*description: This is the start enable bit for irda transmitter.*/\r
+#define UART_IRDA_TX_EN (BIT(10))\r
+#define UART_IRDA_TX_EN_M (BIT(10))\r
+#define UART_IRDA_TX_EN_V 0x1\r
+#define UART_IRDA_TX_EN_S 10\r
+/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable irda loopback mode.*/\r
+#define UART_IRDA_DPLX (BIT(9))\r
+#define UART_IRDA_DPLX_M (BIT(9))\r
+#define UART_IRDA_DPLX_V 0x1\r
+#define UART_IRDA_DPLX_S 9\r
+/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
+/*description: Set this bit to enbale transmitter to send 0 when the process\r
+ of sending data is done.*/\r
+#define UART_TXD_BRK (BIT(8))\r
+#define UART_TXD_BRK_M (BIT(8))\r
+#define UART_TXD_BRK_V 0x1\r
+#define UART_TXD_BRK_S 8\r
+/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
+/*description: This register is used to configure the software dtr signal which\r
+ is used in software flow control..*/\r
+#define UART_SW_DTR (BIT(7))\r
+#define UART_SW_DTR_M (BIT(7))\r
+#define UART_SW_DTR_V 0x1\r
+#define UART_SW_DTR_S 7\r
+/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
+/*description: This register is used to configure the software rts signal which\r
+ is used in software flow control.*/\r
+#define UART_SW_RTS (BIT(6))\r
+#define UART_SW_RTS_M (BIT(6))\r
+#define UART_SW_RTS_V 0x1\r
+#define UART_SW_RTS_S 6\r
+/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */\r
+/*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/\r
+#define UART_STOP_BIT_NUM 0x00000003\r
+#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))\r
+#define UART_STOP_BIT_NUM_V 0x3\r
+#define UART_STOP_BIT_NUM_S 4\r
+/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */\r
+/*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/\r
+#define UART_BIT_NUM 0x00000003\r
+#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))\r
+#define UART_BIT_NUM_V 0x3\r
+#define UART_BIT_NUM_S 2\r
+/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable uart parity check.*/\r
+#define UART_PARITY_EN (BIT(1))\r
+#define UART_PARITY_EN_M (BIT(1))\r
+#define UART_PARITY_EN_V 0x1\r
+#define UART_PARITY_EN_S 1\r
+/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: This register is used to configure the parity check mode. 0:even 1:odd*/\r
+#define UART_PARITY (BIT(0))\r
+#define UART_PARITY_M (BIT(0))\r
+#define UART_PARITY_V 0x1\r
+#define UART_PARITY_S 0\r
+\r
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)\r
+/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
+/*description: This is the enble bit for uart receiver's timeout function.*/\r
+#define UART_RX_TOUT_EN (BIT(31))\r
+#define UART_RX_TOUT_EN_M (BIT(31))\r
+#define UART_RX_TOUT_EN_V 0x1\r
+#define UART_RX_TOUT_EN_S 31\r
+/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */\r
+/*description: This register is used to configure the timeout value for uart\r
+ receiver receiving a byte.*/\r
+#define UART_RX_TOUT_THRHD 0x0000007F\r
+#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))\r
+#define UART_RX_TOUT_THRHD_V 0x7F\r
+#define UART_RX_TOUT_THRHD_S 24\r
+/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
+/*description: This is the flow enable bit for uart receiver. 1:choose software\r
+ flow control with configuring sw_rts signal*/\r
+#define UART_RX_FLOW_EN (BIT(23))\r
+#define UART_RX_FLOW_EN_M (BIT(23))\r
+#define UART_RX_FLOW_EN_V 0x1\r
+#define UART_RX_FLOW_EN_S 23\r
+/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */\r
+/*description: when receiver receives more data than its threshold value��\r
+ receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/\r
+#define UART_RX_FLOW_THRHD 0x0000007F\r
+#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))\r
+#define UART_RX_FLOW_THRHD_V 0x7F\r
+#define UART_RX_FLOW_THRHD_S 16\r
+/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */\r
+/*description: when the data amount in transmitter fifo is less than its threshold\r
+ value�� it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/\r
+#define UART_TXFIFO_EMPTY_THRHD 0x0000007F\r
+#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))\r
+#define UART_TXFIFO_EMPTY_THRHD_V 0x7F\r
+#define UART_TXFIFO_EMPTY_THRHD_S 8\r
+/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */\r
+/*description: When receiver receives more data than its threshold value��receiver\r
+ will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/\r
+#define UART_RXFIFO_FULL_THRHD 0x0000007F\r
+#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))\r
+#define UART_RXFIFO_FULL_THRHD_V 0x7F\r
+#define UART_RXFIFO_FULL_THRHD_S 0\r
+\r
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)\r
+/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
+/*description: This register stores the value of the minimum duration time for\r
+ the low level pulse�� it is used in baudrate-detect process.*/\r
+#define UART_LOWPULSE_MIN_CNT 0x000FFFFF\r
+#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))\r
+#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF\r
+#define UART_LOWPULSE_MIN_CNT_S 0\r
+\r
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)\r
+/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
+/*description: This register stores the value of the maxinum duration time\r
+ for the high level pulse�� it is used in baudrate-detect process.*/\r
+#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF\r
+#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))\r
+#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF\r
+#define UART_HIGHPULSE_MIN_CNT_S 0\r
+\r
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)\r
+/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */\r
+/*description: This register stores the count of rxd edge change�� it is used\r
+ in baudrate-detect process.*/\r
+#define UART_RXD_EDGE_CNT 0x000003FF\r
+#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))\r
+#define UART_RXD_EDGE_CNT_V 0x3FF\r
+#define UART_RXD_EDGE_CNT_S 0\r
+\r
+#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)\r
+/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: Set this bit to send xoff char�� it is cleared by hardware automatically.*/\r
+#define UART_SEND_XOFF (BIT(5))\r
+#define UART_SEND_XOFF_M (BIT(5))\r
+#define UART_SEND_XOFF_V 0x1\r
+#define UART_SEND_XOFF_S 5\r
+/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: Set this bit to send xon char�� it is cleared by hardware automatically.*/\r
+#define UART_SEND_XON (BIT(4))\r
+#define UART_SEND_XON_M (BIT(4))\r
+#define UART_SEND_XON_V 0x1\r
+#define UART_SEND_XON_S 4\r
+/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/\r
+#define UART_FORCE_XOFF (BIT(3))\r
+#define UART_FORCE_XOFF_M (BIT(3))\r
+#define UART_FORCE_XOFF_V 0x1\r
+#define UART_FORCE_XOFF_S 3\r
+/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/\r
+#define UART_FORCE_XON (BIT(2))\r
+#define UART_FORCE_XON_M (BIT(2))\r
+#define UART_FORCE_XON_V 0x1\r
+#define UART_FORCE_XON_S 2\r
+/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to remove flow control char from the received data.*/\r
+#define UART_XONOFF_DEL (BIT(1))\r
+#define UART_XONOFF_DEL_M (BIT(1))\r
+#define UART_XONOFF_DEL_V 0x1\r
+#define UART_XONOFF_DEL_S 1\r
+/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable software flow control. it is used with\r
+ register sw_xon or sw_xoff .*/\r
+#define UART_SW_FLOW_CON_EN (BIT(0))\r
+#define UART_SW_FLOW_CON_EN_M (BIT(0))\r
+#define UART_SW_FLOW_CON_EN_V 0x1\r
+#define UART_SW_FLOW_CON_EN_S 0\r
+\r
+#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)\r
+/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */\r
+/*description: When the input rxd edge changes more than this register value��\r
+ the uart is active from light sleeping mode.*/\r
+#define UART_ACTIVE_THRESHOLD 0x000003FF\r
+#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))\r
+#define UART_ACTIVE_THRESHOLD_V 0x3FF\r
+#define UART_ACTIVE_THRESHOLD_S 0\r
+\r
+#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C)\r
+/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */\r
+/*description: This register stores the xoff flow control char.*/\r
+#define UART_XOFF_CHAR 0x000000FF\r
+#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))\r
+#define UART_XOFF_CHAR_V 0xFF\r
+#define UART_XOFF_CHAR_S 24\r
+/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */\r
+/*description: This register stores the xon flow control char.*/\r
+#define UART_XON_CHAR 0x000000FF\r
+#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))\r
+#define UART_XON_CHAR_V 0xFF\r
+#define UART_XON_CHAR_S 16\r
+/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */\r
+/*description: When the data amount in receiver's fifo is less than this register\r
+ value�� it will send a xon char with uart_sw_flow_con_en set to 1.*/\r
+#define UART_XOFF_THRESHOLD 0x000000FF\r
+#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))\r
+#define UART_XOFF_THRESHOLD_V 0xFF\r
+#define UART_XOFF_THRESHOLD_S 8\r
+/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */\r
+/*description: when the data amount in receiver's fifo is more than this register\r
+ value�� it will send a xoff char with uart_sw_flow_con_en set to 1.*/\r
+#define UART_XON_THRESHOLD 0x000000FF\r
+#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))\r
+#define UART_XON_THRESHOLD_V 0xFF\r
+#define UART_XON_THRESHOLD_S 0\r
+\r
+#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40)\r
+/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */\r
+/*description: This register is used to configure the num of 0 send after the\r
+ process of sending data is done. it is active when txd_brk is set to 1.*/\r
+#define UART_TX_BRK_NUM 0x000000FF\r
+#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))\r
+#define UART_TX_BRK_NUM_V 0xFF\r
+#define UART_TX_BRK_NUM_S 20\r
+/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */\r
+/*description: This register is used to configure the duration time between transfers.*/\r
+#define UART_TX_IDLE_NUM 0x000003FF\r
+#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))\r
+#define UART_TX_IDLE_NUM_V 0x3FF\r
+#define UART_TX_IDLE_NUM_S 10\r
+/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */\r
+/*description: when receiver takes more time than this register value to receive\r
+ a byte data�� it will produce frame end signal for uhci to stop receiving data.*/\r
+#define UART_RX_IDLE_THRHD 0x000003FF\r
+#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))\r
+#define UART_RX_IDLE_THRHD_V 0x3FF\r
+#define UART_RX_IDLE_THRHD_S 0\r
+\r
+#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44)\r
+/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */\r
+/*description: This register is used to delay the transmitter's internal data signal.*/\r
+#define UART_RS485_TX_DLY_NUM 0x0000000F\r
+#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))\r
+#define UART_RS485_TX_DLY_NUM_V 0xF\r
+#define UART_RS485_TX_DLY_NUM_S 6\r
+/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
+/*description: This register is used to delay the receiver's internal data signal.*/\r
+#define UART_RS485_RX_DLY_NUM (BIT(5))\r
+#define UART_RS485_RX_DLY_NUM_M (BIT(5))\r
+#define UART_RS485_RX_DLY_NUM_V 0x1\r
+#define UART_RS485_RX_DLY_NUM_S 5\r
+/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
+/*description: 1: enable rs485's transmitter to send data when rs485's receiver\r
+ is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/\r
+#define UART_RS485RXBY_TX_EN (BIT(4))\r
+#define UART_RS485RXBY_TX_EN_M (BIT(4))\r
+#define UART_RS485RXBY_TX_EN_V 0x1\r
+#define UART_RS485RXBY_TX_EN_S 4\r
+/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */\r
+/*description: Set this bit to enable loopback transmitter's output data signal\r
+ to receiver's input data signal.*/\r
+#define UART_RS485TX_RX_EN (BIT(3))\r
+#define UART_RS485TX_RX_EN_M (BIT(3))\r
+#define UART_RS485TX_RX_EN_V 0x1\r
+#define UART_RS485TX_RX_EN_S 3\r
+/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */\r
+/*description: Set this bit to delay the stop bit by 1 bit.*/\r
+#define UART_DL1_EN (BIT(2))\r
+#define UART_DL1_EN_M (BIT(2))\r
+#define UART_DL1_EN_V 0x1\r
+#define UART_DL1_EN_S 2\r
+/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */\r
+/*description: Set this bit to delay the stop bit by 1 bit.*/\r
+#define UART_DL0_EN (BIT(1))\r
+#define UART_DL0_EN_M (BIT(1))\r
+#define UART_DL0_EN_V 0x1\r
+#define UART_DL0_EN_S 1\r
+/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to choose rs485 mode.*/\r
+#define UART_RS485_EN (BIT(0))\r
+#define UART_RS485_EN_M (BIT(0))\r
+#define UART_RS485_EN_V 0x1\r
+#define UART_RS485_EN_S 0\r
+\r
+#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48)\r
+/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */\r
+/*description: This register is used to configure the idle duration time before\r
+ the first at_cmd is received by receiver�� when the the duration is less than this register value it will not take the next data received as at_cmd char.*/\r
+#define UART_PRE_IDLE_NUM 0x00FFFFFF\r
+#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))\r
+#define UART_PRE_IDLE_NUM_V 0xFFFFFF\r
+#define UART_PRE_IDLE_NUM_S 0\r
+\r
+#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c)\r
+/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */\r
+/*description: This register is used to configure the duration time between\r
+ the last at_cmd and the next data�� when the duration is less than this register value it will not take the previous data as at_cmd char.*/\r
+#define UART_POST_IDLE_NUM 0x00FFFFFF\r
+#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))\r
+#define UART_POST_IDLE_NUM_V 0xFFFFFF\r
+#define UART_POST_IDLE_NUM_S 0\r
+\r
+#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50)\r
+/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */\r
+/*description: This register is used to configure the duration time between\r
+ the at_cmd chars�� when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/\r
+#define UART_RX_GAP_TOUT 0x00FFFFFF\r
+#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))\r
+#define UART_RX_GAP_TOUT_V 0xFFFFFF\r
+#define UART_RX_GAP_TOUT_S 0\r
+\r
+#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54)\r
+/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */\r
+/*description: This register is used to configure the num of continous at_cmd\r
+ chars received by receiver.*/\r
+#define UART_CHAR_NUM 0x000000FF\r
+#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))\r
+#define UART_CHAR_NUM_V 0xFF\r
+#define UART_CHAR_NUM_S 8\r
+/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */\r
+/*description: This register is used to configure the content of at_cmd char.*/\r
+#define UART_AT_CMD_CHAR 0x000000FF\r
+#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))\r
+#define UART_AT_CMD_CHAR_V 0xFF\r
+#define UART_AT_CMD_CHAR_S 0\r
+\r
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58)\r
+/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */\r
+/*description: refer to txfifo_empty_thrhd 's describtion.*/\r
+#define UART_TX_MEM_EMPTY_THRHD 0x00000007\r
+#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S))\r
+#define UART_TX_MEM_EMPTY_THRHD_V 0x7\r
+#define UART_TX_MEM_EMPTY_THRHD_S 28\r
+/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */\r
+/*description: refer to the rxfifo_full_thrhd's describtion.*/\r
+#define UART_RX_MEM_FULL_THRHD 0x00000007\r
+#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S))\r
+#define UART_RX_MEM_FULL_THRHD_V 0x7\r
+#define UART_RX_MEM_FULL_THRHD_S 25\r
+/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */\r
+/*description: refer to the uart_xoff_threshold's describtion.*/\r
+#define UART_XOFF_THRESHOLD_H2 0x00000003\r
+#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S))\r
+#define UART_XOFF_THRESHOLD_H2_V 0x3\r
+#define UART_XOFF_THRESHOLD_H2_S 23\r
+/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */\r
+/*description: refer to the uart_xon_threshold's describtion.*/\r
+#define UART_XON_THRESHOLD_H2 0x00000003\r
+#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S))\r
+#define UART_XON_THRESHOLD_H2_V 0x3\r
+#define UART_XON_THRESHOLD_H2_S 21\r
+/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */\r
+/*description: refer to the rx_tout_thrhd's describtion.*/\r
+#define UART_RX_TOUT_THRHD_H3 0x00000007\r
+#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S))\r
+#define UART_RX_TOUT_THRHD_H3_V 0x7\r
+#define UART_RX_TOUT_THRHD_H3_S 18\r
+/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */\r
+/*description: refer to the rx_flow_thrhd's describtion.*/\r
+#define UART_RX_FLOW_THRHD_H3 0x00000007\r
+#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S))\r
+#define UART_RX_FLOW_THRHD_H3_V 0x7\r
+#define UART_RX_FLOW_THRHD_H3_S 15\r
+/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the amount of mem allocated\r
+ to transmitter's fifo.the default byte num is 128.*/\r
+#define UART_TX_SIZE 0x0000000F\r
+#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))\r
+#define UART_TX_SIZE_V 0xF\r
+#define UART_TX_SIZE_S 7\r
+/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */\r
+/*description: This register is used to configure the amount of mem allocated\r
+ to receiver's fifo. the default byte num is 128.*/\r
+#define UART_RX_SIZE 0x0000000F\r
+#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))\r
+#define UART_RX_SIZE_V 0xF\r
+#define UART_RX_SIZE_S 3\r
+/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */\r
+/*description: Set this bit to power down mem��when reg_mem_pd registers in\r
+ the 3 uarts are all set to 1 mem will enter low power mode.*/\r
+#define UART_MEM_PD (BIT(0))\r
+#define UART_MEM_PD_M (BIT(0))\r
+#define UART_MEM_PD_V 0x1\r
+#define UART_MEM_PD_S 0\r
+\r
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c)\r
+/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */\r
+/*description: */\r
+#define UART_MEM_TX_STATUS 0x00FFFFFF\r
+#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S))\r
+#define UART_MEM_TX_STATUS_V 0xFFFFFF\r
+#define UART_MEM_TX_STATUS_S 0\r
+\r
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60)\r
+/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */\r
+/*description: */\r
+#define UART_MEM_RX_STATUS 0x00FFFFFF\r
+#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S))\r
+#define UART_MEM_RX_STATUS_V 0xFFFFFF\r
+#define UART_MEM_RX_STATUS_S 0\r
+\r
+#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)\r
+/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */\r
+/*description: refer to the txfifo_cnt's describtion.*/\r
+#define UART_TX_MEM_CNT 0x00000007\r
+#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S))\r
+#define UART_TX_MEM_CNT_V 0x7\r
+#define UART_TX_MEM_CNT_S 3\r
+/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */\r
+/*description: refer to the rxfifo_cnt's describtion.*/\r
+#define UART_RX_MEM_CNT 0x00000007\r
+#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S))\r
+#define UART_RX_MEM_CNT_V 0x7\r
+#define UART_RX_MEM_CNT_S 0\r
+\r
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68)\r
+/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
+/*description: This register stores the count of rxd posedge edge�� it is used\r
+ in boudrate-detect process.*/\r
+#define UART_POSEDGE_MIN_CNT 0x000FFFFF\r
+#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))\r
+#define UART_POSEDGE_MIN_CNT_V 0xFFFFF\r
+#define UART_POSEDGE_MIN_CNT_S 0\r
+\r
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c)\r
+/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */\r
+/*description: This register stores the count of rxd negedge edge�� it is used\r
+ in boudrate-detect process.*/\r
+#define UART_NEGEDGE_MIN_CNT 0x000FFFFF\r
+#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))\r
+#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF\r
+#define UART_NEGEDGE_MIN_CNT_S 0\r
+\r
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78)\r
+/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */\r
+/*description: */\r
+#define UART_DATE 0xFFFFFFFF\r
+#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S))\r
+#define UART_DATE_V 0xFFFFFFFF\r
+#define UART_DATE_S 0\r
+\r
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C)\r
+/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */\r
+/*description: */\r
+#define UART_ID 0xFFFFFFFF\r
+#define UART_ID_M ((UART_ID_V)<<(UART_ID_S))\r
+#define UART_ID_V 0xFFFFFFFF\r
+#define UART_ID_S 0\r
+\r
+\r
+\r
+\r
+#endif /*__UART_REG_H__ */\r
+\r
+\r
+++ /dev/null
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UART_REG_H_
-#define _SOC_UART_REG_H_
-
-#include "soc.h"
-
-//Slow bus
-//#define REG_UART_BASE( i ) (0x60000000+(i)*0x10000)
-//Fast bus
-#define REG_UART_BASE( i ) (0x3ff40000+(i)*0x10000)
-
-#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
- /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
- /*description: R/W share the same address*/
- #define UART_RXFIFO_RD_BYTE 0x000000FF
- #define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
- #define UART_RXFIFO_RD_BYTE_V 0xFF
- #define UART_RXFIFO_RD_BYTE_S 0
- #define UART_GET_RXFIFO_RD_BYTE(i) GET_PERI_REG_BITS2(UART_FIFO_REG(i) , UART_RXFIFO_RD_BYTE_V, UART_RXFIFO_RD_BYTE_S)
- #define UART_SET_TXFIFO_WR_BYTE(i,val) SET_PERI_REG_BITS(UART_FIFO_REG(i) , UART_RXFIFO_RD_BYTE_V, val, UART_RXFIFO_RD_BYTE_S)
-
-
-
-#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
- /* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for detecting AT_CMD char interrupt*/
- #define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18))
- #define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18))
- #define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1
- #define UART_AT_CMD_CHAR_DET_INT_RAW_S 18
- /* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for rs485 tx rx clash interrrupt*/
- #define UART_RS485_CLASH_INT_RAW (BIT(17))
- #define UART_RS485_CLASH_INT_RAW_M (BIT(17))
- #define UART_RS485_CLASH_INT_RAW_V 0x1
- #define UART_RS485_CLASH_INT_RAW_S 17
- /* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for rs485 other rx error*/
- #define UART_RS485_FRM_ERR_INT_RAW (BIT(16))
- #define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16))
- #define UART_RS485_FRM_ERR_INT_RAW_V 0x1
- #define UART_RS485_FRM_ERR_INT_RAW_S 16
- /* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for rs485 parity error*/
- #define UART_RS485_PARITY_ERR_INT_RAW (BIT(15))
- #define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15))
- #define UART_RS485_PARITY_ERR_INT_RAW_V 0x1
- #define UART_RS485_PARITY_ERR_INT_RAW_S 15
- /* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for tx done*/
- #define UART_TX_DONE_INT_RAW (BIT(14))
- #define UART_TX_DONE_INT_RAW_M (BIT(14))
- #define UART_TX_DONE_INT_RAW_V 0x1
- #define UART_TX_DONE_INT_RAW_S 14
- /* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for tx send idle done(depends on the uart_tx_idle_num)*/
- #define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13))
- #define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13))
- #define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1
- #define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13
- /* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for send 0 done(depends on uart_tx_brk_num)*/
- #define UART_TX_BRK_DONE_INT_RAW (BIT(12))
- #define UART_TX_BRK_DONE_INT_RAW_M (BIT(12))
- #define UART_TX_BRK_DONE_INT_RAW_V 0x1
- #define UART_TX_BRK_DONE_INT_RAW_S 12
- /* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for detecting rx glitch pulse*/
- #define UART_GLITCH_DET_INT_RAW (BIT(11))
- #define UART_GLITCH_DET_INT_RAW_M (BIT(11))
- #define UART_GLITCH_DET_INT_RAW_V 0x1
- #define UART_GLITCH_DET_INT_RAW_S 11
- /* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for rx receive xoff char(depends on the uart_xoff_char )*/
- #define UART_SW_XOFF_INT_RAW (BIT(10))
- #define UART_SW_XOFF_INT_RAW_M (BIT(10))
- #define UART_SW_XOFF_INT_RAW_V 0x1
- #define UART_SW_XOFF_INT_RAW_S 10
- /* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for rx receive xon char(depends on the uart_xon_char )*/
- #define UART_SW_XON_INT_RAW (BIT(9))
- #define UART_SW_XON_INT_RAW_M (BIT(9))
- #define UART_SW_XON_INT_RAW_V 0x1
- #define UART_SW_XON_INT_RAW_S 9
- /* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for Rx time-out interrupt(depands on the UART_RX_TOUT_THRHD)*/
- #define UART_RXFIFO_TOUT_INT_RAW (BIT(8))
- #define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8))
- #define UART_RXFIFO_TOUT_INT_RAW_V 0x1
- #define UART_RXFIFO_TOUT_INT_RAW_S 8
- /* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for Rx byte start error*/
- #define UART_BRK_DET_INT_RAW (BIT(7))
- #define UART_BRK_DET_INT_RAW_M (BIT(7))
- #define UART_BRK_DET_INT_RAW_V 0x1
- #define UART_BRK_DET_INT_RAW_S 7
- /* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for CTS changing level*/
- #define UART_CTS_CHG_INT_RAW (BIT(6))
- #define UART_CTS_CHG_INT_RAW_M (BIT(6))
- #define UART_CTS_CHG_INT_RAW_V 0x1
- #define UART_CTS_CHG_INT_RAW_S 6
- /* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for DSR changing level*/
- #define UART_DSR_CHG_INT_RAW (BIT(5))
- #define UART_DSR_CHG_INT_RAW_M (BIT(5))
- #define UART_DSR_CHG_INT_RAW_V 0x1
- #define UART_DSR_CHG_INT_RAW_S 5
- /* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for rx fifo overflow*/
- #define UART_RXFIFO_OVF_INT_RAW (BIT(4))
- #define UART_RXFIFO_OVF_INT_RAW_M (BIT(4))
- #define UART_RXFIFO_OVF_INT_RAW_V 0x1
- #define UART_RXFIFO_OVF_INT_RAW_S 4
- /* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for other rx error*/
- #define UART_FRM_ERR_INT_RAW (BIT(3))
- #define UART_FRM_ERR_INT_RAW_M (BIT(3))
- #define UART_FRM_ERR_INT_RAW_V 0x1
- #define UART_FRM_ERR_INT_RAW_S 3
- /* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for parity check error*/
- #define UART_PARITY_ERR_INT_RAW (BIT(2))
- #define UART_PARITY_ERR_INT_RAW_M (BIT(2))
- #define UART_PARITY_ERR_INT_RAW_V 0x1
- #define UART_PARITY_ERR_INT_RAW_S 2
- /* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for tx fifo empty interrupt(depands on UART_TXFIFO_EMPTY_THRHD bits)*/
- #define UART_TXFIFO_EMPTY_INT_RAW (BIT(1))
- #define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1))
- #define UART_TXFIFO_EMPTY_INT_RAW_V 0x1
- #define UART_TXFIFO_EMPTY_INT_RAW_S 1
- /* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
- /*description: The interrupt raw bit for rx fifo full interrupt(depands on UART_RXFIFO_FULL_THRHD bits)*/
- #define UART_RXFIFO_FULL_INT_RAW (BIT(0))
- #define UART_RXFIFO_FULL_INT_RAW_M (BIT(0))
- #define UART_RXFIFO_FULL_INT_RAW_V 0x1
- #define UART_RXFIFO_FULL_INT_RAW_S 0
- #define UART_GET_AT_CMD_CHAR_DET_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_AT_CMD_CHAR_DET_INT_RAW_V, UART_AT_CMD_CHAR_DET_INT_RAW_S)
- #define UART_GET_RS485_CLASH_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RS485_CLASH_INT_RAW_V, UART_RS485_CLASH_INT_RAW_S)
- #define UART_GET_RS485_FRM_ERR_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RS485_FRM_ERR_INT_RAW_V, UART_RS485_FRM_ERR_INT_RAW_S)
- #define UART_GET_RS485_PARITY_ERR_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RS485_PARITY_ERR_INT_RAW_V, UART_RS485_PARITY_ERR_INT_RAW_S)
- #define UART_GET_TX_DONE_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_TX_DONE_INT_RAW_V, UART_TX_DONE_INT_RAW_S)
- #define UART_GET_TX_BRK_IDLE_DONE_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_TX_BRK_IDLE_DONE_INT_RAW_V, UART_TX_BRK_IDLE_DONE_INT_RAW_S)
- #define UART_GET_TX_BRK_DONE_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_TX_BRK_DONE_INT_RAW_V, UART_TX_BRK_DONE_INT_RAW_S)
- #define UART_GET_GLITCH_DET_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_GLITCH_DET_INT_RAW_V, UART_GLITCH_DET_INT_RAW_S)
- #define UART_GET_SW_XOFF_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_SW_XOFF_INT_RAW_V, UART_SW_XOFF_INT_RAW_S)
- #define UART_GET_SW_XON_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_SW_XON_INT_RAW_V, UART_SW_XON_INT_RAW_S)
- #define UART_GET_RXFIFO_TOUT_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RXFIFO_TOUT_INT_RAW_V, UART_RXFIFO_TOUT_INT_RAW_S)
- #define UART_GET_BRK_DET_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_BRK_DET_INT_RAW_V, UART_BRK_DET_INT_RAW_S)
- #define UART_GET_CTS_CHG_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_CTS_CHG_INT_RAW_V, UART_CTS_CHG_INT_RAW_S)
- #define UART_GET_DSR_CHG_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_DSR_CHG_INT_RAW_V, UART_DSR_CHG_INT_RAW_S)
- #define UART_GET_RXFIFO_OVF_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RXFIFO_OVF_INT_RAW_V, UART_RXFIFO_OVF_INT_RAW_S)
- #define UART_GET_FRM_ERR_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_FRM_ERR_INT_RAW_V, UART_FRM_ERR_INT_RAW_S)
- #define UART_GET_PARITY_ERR_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_PARITY_ERR_INT_RAW_V, UART_PARITY_ERR_INT_RAW_S)
- #define UART_GET_TXFIFO_EMPTY_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_TXFIFO_EMPTY_INT_RAW_V, UART_TXFIFO_EMPTY_INT_RAW_S)
- #define UART_GET_RXFIFO_FULL_INT_RAW(i) GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RXFIFO_FULL_INT_RAW_V, UART_RXFIFO_FULL_INT_RAW_S)
-
-
-
-#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
- /* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
- /*description: The interrupt state bit for detecting AT_CMD char interrupt*/
- #define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18))
- #define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18))
- #define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1
- #define UART_AT_CMD_CHAR_DET_INT_ST_S 18
- /* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
- /*description: The interrupt state bit for rs485 tx rx clash interrrupt*/
- #define UART_RS485_CLASH_INT_ST (BIT(17))
- #define UART_RS485_CLASH_INT_ST_M (BIT(17))
- #define UART_RS485_CLASH_INT_ST_V 0x1
- #define UART_RS485_CLASH_INT_ST_S 17
- /* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
- /*description: The interrupt state bit for rs485 other rx error*/
- #define UART_RS485_FRM_ERR_INT_ST (BIT(16))
- #define UART_RS485_FRM_ERR_INT_ST_M (BIT(16))
- #define UART_RS485_FRM_ERR_INT_ST_V 0x1
- #define UART_RS485_FRM_ERR_INT_ST_S 16
- /* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
- /*description: The interrupt state bit for rs485 parity error*/
- #define UART_RS485_PARITY_ERR_INT_ST (BIT(15))
- #define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15))
- #define UART_RS485_PARITY_ERR_INT_ST_V 0x1
- #define UART_RS485_PARITY_ERR_INT_ST_S 15
- /* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
- /*description: The interrupt state bit for tx done event*/
- #define UART_TX_DONE_INT_ST (BIT(14))
- #define UART_TX_DONE_INT_ST_M (BIT(14))
- #define UART_TX_DONE_INT_ST_V 0x1
- #define UART_TX_DONE_INT_ST_S 14
- /* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
- /*description: The interrupt state bit for tx send idle done event*/
- #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13))
- #define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13))
- #define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1
- #define UART_TX_BRK_IDLE_DONE_INT_ST_S 13
- /* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
- /*description: The interrupt state bit for send 0 done event*/
- #define UART_TX_BRK_DONE_INT_ST (BIT(12))
- #define UART_TX_BRK_DONE_INT_ST_M (BIT(12))
- #define UART_TX_BRK_DONE_INT_ST_V 0x1
- #define UART_TX_BRK_DONE_INT_ST_S 12
- /* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
- /*description: The interrupt state bit for detecting rx glitch pulse event*/
- #define UART_GLITCH_DET_INT_ST (BIT(11))
- #define UART_GLITCH_DET_INT_ST_M (BIT(11))
- #define UART_GLITCH_DET_INT_ST_V 0x1
- #define UART_GLITCH_DET_INT_ST_S 11
- /* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
- /*description: The interrupt state bit for rx receive xoff char event*/
- #define UART_SW_XOFF_INT_ST (BIT(10))
- #define UART_SW_XOFF_INT_ST_M (BIT(10))
- #define UART_SW_XOFF_INT_ST_V 0x1
- #define UART_SW_XOFF_INT_ST_S 10
- /* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
- /*description: The interrupt state bit for rx receive xon char event*/
- #define UART_SW_XON_INT_ST (BIT(9))
- #define UART_SW_XON_INT_ST_M (BIT(9))
- #define UART_SW_XON_INT_ST_V 0x1
- #define UART_SW_XON_INT_ST_S 9
- /* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
- /*description: The interrupt state bit for Rx time-out event*/
- #define UART_RXFIFO_TOUT_INT_ST (BIT(8))
- #define UART_RXFIFO_TOUT_INT_ST_M (BIT(8))
- #define UART_RXFIFO_TOUT_INT_ST_V 0x1
- #define UART_RXFIFO_TOUT_INT_ST_S 8
- /* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
- /*description: The interrupt state bit for rx byte start error*/
- #define UART_BRK_DET_INT_ST (BIT(7))
- #define UART_BRK_DET_INT_ST_M (BIT(7))
- #define UART_BRK_DET_INT_ST_V 0x1
- #define UART_BRK_DET_INT_ST_S 7
- /* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
- /*description: The interrupt state bit for CTS changing level*/
- #define UART_CTS_CHG_INT_ST (BIT(6))
- #define UART_CTS_CHG_INT_ST_M (BIT(6))
- #define UART_CTS_CHG_INT_ST_V 0x1
- #define UART_CTS_CHG_INT_ST_S 6
- /* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
- /*description: The interrupt state bit for DSR changing level*/
- #define UART_DSR_CHG_INT_ST (BIT(5))
- #define UART_DSR_CHG_INT_ST_M (BIT(5))
- #define UART_DSR_CHG_INT_ST_V 0x1
- #define UART_DSR_CHG_INT_ST_S 5
- /* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
- /*description: The interrupt state bit for RX fifo overflow*/
- #define UART_RXFIFO_OVF_INT_ST (BIT(4))
- #define UART_RXFIFO_OVF_INT_ST_M (BIT(4))
- #define UART_RXFIFO_OVF_INT_ST_V 0x1
- #define UART_RXFIFO_OVF_INT_ST_S 4
- /* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
- /*description: The interrupt state for other rx error*/
- #define UART_FRM_ERR_INT_ST (BIT(3))
- #define UART_FRM_ERR_INT_ST_M (BIT(3))
- #define UART_FRM_ERR_INT_ST_V 0x1
- #define UART_FRM_ERR_INT_ST_S 3
- /* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
- /*description: The interrupt state bit for rx parity error*/
- #define UART_PARITY_ERR_INT_ST (BIT(2))
- #define UART_PARITY_ERR_INT_ST_M (BIT(2))
- #define UART_PARITY_ERR_INT_ST_V 0x1
- #define UART_PARITY_ERR_INT_ST_S 2
- /* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
- /*description: The interrupt state bit for TX fifo empty*/
- #define UART_TXFIFO_EMPTY_INT_ST (BIT(1))
- #define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1))
- #define UART_TXFIFO_EMPTY_INT_ST_V 0x1
- #define UART_TXFIFO_EMPTY_INT_ST_S 1
- /* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
- /*description: The interrupt state bit for RX fifo full event*/
- #define UART_RXFIFO_FULL_INT_ST (BIT(0))
- #define UART_RXFIFO_FULL_INT_ST_M (BIT(0))
- #define UART_RXFIFO_FULL_INT_ST_V 0x1
- #define UART_RXFIFO_FULL_INT_ST_S 0
- #define UART_GET_AT_CMD_CHAR_DET_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_AT_CMD_CHAR_DET_INT_ST_V, UART_AT_CMD_CHAR_DET_INT_ST_S)
- #define UART_GET_RS485_CLASH_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RS485_CLASH_INT_ST_V, UART_RS485_CLASH_INT_ST_S)
- #define UART_GET_RS485_FRM_ERR_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RS485_FRM_ERR_INT_ST_V, UART_RS485_FRM_ERR_INT_ST_S)
- #define UART_GET_RS485_PARITY_ERR_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RS485_PARITY_ERR_INT_ST_V, UART_RS485_PARITY_ERR_INT_ST_S)
- #define UART_GET_TX_DONE_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_TX_DONE_INT_ST_V, UART_TX_DONE_INT_ST_S)
- #define UART_GET_TX_BRK_IDLE_DONE_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_TX_BRK_IDLE_DONE_INT_ST_V, UART_TX_BRK_IDLE_DONE_INT_ST_S)
- #define UART_GET_TX_BRK_DONE_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_TX_BRK_DONE_INT_ST_V, UART_TX_BRK_DONE_INT_ST_S)
- #define UART_GET_GLITCH_DET_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_GLITCH_DET_INT_ST_V, UART_GLITCH_DET_INT_ST_S)
- #define UART_GET_SW_XOFF_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_SW_XOFF_INT_ST_V, UART_SW_XOFF_INT_ST_S)
- #define UART_GET_SW_XON_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_SW_XON_INT_ST_V, UART_SW_XON_INT_ST_S)
- #define UART_GET_RXFIFO_TOUT_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RXFIFO_TOUT_INT_ST_V, UART_RXFIFO_TOUT_INT_ST_S)
- #define UART_GET_BRK_DET_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_BRK_DET_INT_ST_V, UART_BRK_DET_INT_ST_S)
- #define UART_GET_CTS_CHG_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_CTS_CHG_INT_ST_V, UART_CTS_CHG_INT_ST_S)
- #define UART_GET_DSR_CHG_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_DSR_CHG_INT_ST_V, UART_DSR_CHG_INT_ST_S)
- #define UART_GET_RXFIFO_OVF_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RXFIFO_OVF_INT_ST_V, UART_RXFIFO_OVF_INT_ST_S)
- #define UART_GET_FRM_ERR_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_FRM_ERR_INT_ST_V, UART_FRM_ERR_INT_ST_S)
- #define UART_GET_PARITY_ERR_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_PARITY_ERR_INT_ST_V, UART_PARITY_ERR_INT_ST_S)
- #define UART_GET_TXFIFO_EMPTY_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_TXFIFO_EMPTY_INT_ST_V, UART_TXFIFO_EMPTY_INT_ST_S)
- #define UART_GET_RXFIFO_FULL_INT_ST(i) GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RXFIFO_FULL_INT_ST_V, UART_RXFIFO_FULL_INT_ST_S)
-
-
-
-#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC)
- /* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for detecting AT_CMD char interrupt*/
- #define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18))
- #define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18))
- #define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1
- #define UART_AT_CMD_CHAR_DET_INT_ENA_S 18
- /* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rs485 tx rx clash interrrupt*/
- #define UART_RS485_CLASH_INT_ENA (BIT(17))
- #define UART_RS485_CLASH_INT_ENA_M (BIT(17))
- #define UART_RS485_CLASH_INT_ENA_V 0x1
- #define UART_RS485_CLASH_INT_ENA_S 17
- /* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rs485 other rx error*/
- #define UART_RS485_FRM_ERR_INT_ENA (BIT(16))
- #define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16))
- #define UART_RS485_FRM_ERR_INT_ENA_V 0x1
- #define UART_RS485_FRM_ERR_INT_ENA_S 16
- /* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rs485 parity error*/
- #define UART_RS485_PARITY_ERR_INT_ENA (BIT(15))
- #define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15))
- #define UART_RS485_PARITY_ERR_INT_ENA_V 0x1
- #define UART_RS485_PARITY_ERR_INT_ENA_S 15
- /* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for tx done interrupt*/
- #define UART_TX_DONE_INT_ENA (BIT(14))
- #define UART_TX_DONE_INT_ENA_M (BIT(14))
- #define UART_TX_DONE_INT_ENA_V 0x1
- #define UART_TX_DONE_INT_ENA_S 14
- /* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for tx send idle done interrupt*/
- #define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13))
- #define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13))
- #define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1
- #define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13
- /* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for send 0 done interrupt*/
- #define UART_TX_BRK_DONE_INT_ENA (BIT(12))
- #define UART_TX_BRK_DONE_INT_ENA_M (BIT(12))
- #define UART_TX_BRK_DONE_INT_ENA_V 0x1
- #define UART_TX_BRK_DONE_INT_ENA_S 12
- /* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for detecting rx glitch pulse interrupt*/
- #define UART_GLITCH_DET_INT_ENA (BIT(11))
- #define UART_GLITCH_DET_INT_ENA_M (BIT(11))
- #define UART_GLITCH_DET_INT_ENA_V 0x1
- #define UART_GLITCH_DET_INT_ENA_S 11
- /* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rx receive xoff char interrupt*/
- #define UART_SW_XOFF_INT_ENA (BIT(10))
- #define UART_SW_XOFF_INT_ENA_M (BIT(10))
- #define UART_SW_XOFF_INT_ENA_V 0x1
- #define UART_SW_XOFF_INT_ENA_S 10
- /* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rx receive xon char interrupt*/
- #define UART_SW_XON_INT_ENA (BIT(9))
- #define UART_SW_XON_INT_ENA_M (BIT(9))
- #define UART_SW_XON_INT_ENA_V 0x1
- #define UART_SW_XON_INT_ENA_S 9
- /* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rx time-out interrupt*/
- #define UART_RXFIFO_TOUT_INT_ENA (BIT(8))
- #define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8))
- #define UART_RXFIFO_TOUT_INT_ENA_V 0x1
- #define UART_RXFIFO_TOUT_INT_ENA_S 8
- /* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rx byte start error*/
- #define UART_BRK_DET_INT_ENA (BIT(7))
- #define UART_BRK_DET_INT_ENA_M (BIT(7))
- #define UART_BRK_DET_INT_ENA_V 0x1
- #define UART_BRK_DET_INT_ENA_S 7
- /* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for CTS changing level*/
- #define UART_CTS_CHG_INT_ENA (BIT(6))
- #define UART_CTS_CHG_INT_ENA_M (BIT(6))
- #define UART_CTS_CHG_INT_ENA_V 0x1
- #define UART_CTS_CHG_INT_ENA_S 6
- /* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for DSR changing level*/
- #define UART_DSR_CHG_INT_ENA (BIT(5))
- #define UART_DSR_CHG_INT_ENA_M (BIT(5))
- #define UART_DSR_CHG_INT_ENA_V 0x1
- #define UART_DSR_CHG_INT_ENA_S 5
- /* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rx fifo overflow*/
- #define UART_RXFIFO_OVF_INT_ENA (BIT(4))
- #define UART_RXFIFO_OVF_INT_ENA_M (BIT(4))
- #define UART_RXFIFO_OVF_INT_ENA_V 0x1
- #define UART_RXFIFO_OVF_INT_ENA_S 4
- /* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for other rx error*/
- #define UART_FRM_ERR_INT_ENA (BIT(3))
- #define UART_FRM_ERR_INT_ENA_M (BIT(3))
- #define UART_FRM_ERR_INT_ENA_V 0x1
- #define UART_FRM_ERR_INT_ENA_S 3
- /* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for parity error*/
- #define UART_PARITY_ERR_INT_ENA (BIT(2))
- #define UART_PARITY_ERR_INT_ENA_M (BIT(2))
- #define UART_PARITY_ERR_INT_ENA_V 0x1
- #define UART_PARITY_ERR_INT_ENA_S 2
- /* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for tx fifo empty event*/
- #define UART_TXFIFO_EMPTY_INT_ENA (BIT(1))
- #define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1))
- #define UART_TXFIFO_EMPTY_INT_ENA_V 0x1
- #define UART_TXFIFO_EMPTY_INT_ENA_S 1
- /* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
- /*description: The interrupt enable bit for rx fifo full event*/
- #define UART_RXFIFO_FULL_INT_ENA (BIT(0))
- #define UART_RXFIFO_FULL_INT_ENA_M (BIT(0))
- #define UART_RXFIFO_FULL_INT_ENA_V 0x1
- #define UART_RXFIFO_FULL_INT_ENA_S 0
- #define UART_GET_AT_CMD_CHAR_DET_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_AT_CMD_CHAR_DET_INT_ENA_V, UART_AT_CMD_CHAR_DET_INT_ENA_S)
- #define UART_SET_AT_CMD_CHAR_DET_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_AT_CMD_CHAR_DET_INT_ENA_V,(val),UART_AT_CMD_CHAR_DET_INT_ENA_S)
- #define UART_GET_RS485_CLASH_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RS485_CLASH_INT_ENA_V, UART_RS485_CLASH_INT_ENA_S)
- #define UART_SET_RS485_CLASH_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RS485_CLASH_INT_ENA_V,(val),UART_RS485_CLASH_INT_ENA_S)
- #define UART_GET_RS485_FRM_ERR_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RS485_FRM_ERR_INT_ENA_V, UART_RS485_FRM_ERR_INT_ENA_S)
- #define UART_SET_RS485_FRM_ERR_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RS485_FRM_ERR_INT_ENA_V,(val),UART_RS485_FRM_ERR_INT_ENA_S)
- #define UART_GET_RS485_PARITY_ERR_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RS485_PARITY_ERR_INT_ENA_V, UART_RS485_PARITY_ERR_INT_ENA_S)
- #define UART_SET_RS485_PARITY_ERR_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RS485_PARITY_ERR_INT_ENA_V,(val),UART_RS485_PARITY_ERR_INT_ENA_S)
- #define UART_GET_TX_DONE_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_TX_DONE_INT_ENA_V, UART_TX_DONE_INT_ENA_S)
- #define UART_SET_TX_DONE_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_TX_DONE_INT_ENA_V,(val),UART_TX_DONE_INT_ENA_S)
- #define UART_GET_TX_BRK_IDLE_DONE_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_TX_BRK_IDLE_DONE_INT_ENA_V, UART_TX_BRK_IDLE_DONE_INT_ENA_S)
- #define UART_SET_TX_BRK_IDLE_DONE_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_TX_BRK_IDLE_DONE_INT_ENA_V,(val),UART_TX_BRK_IDLE_DONE_INT_ENA_S)
- #define UART_GET_TX_BRK_DONE_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_TX_BRK_DONE_INT_ENA_V, UART_TX_BRK_DONE_INT_ENA_S)
- #define UART_SET_TX_BRK_DONE_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_TX_BRK_DONE_INT_ENA_V,(val),UART_TX_BRK_DONE_INT_ENA_S)
- #define UART_GET_GLITCH_DET_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_GLITCH_DET_INT_ENA_V, UART_GLITCH_DET_INT_ENA_S)
- #define UART_SET_GLITCH_DET_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_GLITCH_DET_INT_ENA_V,(val),UART_GLITCH_DET_INT_ENA_S)
- #define UART_GET_SW_XOFF_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_SW_XOFF_INT_ENA_V, UART_SW_XOFF_INT_ENA_S)
- #define UART_SET_SW_XOFF_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_SW_XOFF_INT_ENA_V,(val),UART_SW_XOFF_INT_ENA_S)
- #define UART_GET_SW_XON_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_SW_XON_INT_ENA_V, UART_SW_XON_INT_ENA_S)
- #define UART_SET_SW_XON_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_SW_XON_INT_ENA_V,(val),UART_SW_XON_INT_ENA_S)
- #define UART_GET_RXFIFO_TOUT_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RXFIFO_TOUT_INT_ENA_V, UART_RXFIFO_TOUT_INT_ENA_S)
- #define UART_SET_RXFIFO_TOUT_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RXFIFO_TOUT_INT_ENA_V,(val),UART_RXFIFO_TOUT_INT_ENA_S)
- #define UART_GET_BRK_DET_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_BRK_DET_INT_ENA_V, UART_BRK_DET_INT_ENA_S)
- #define UART_SET_BRK_DET_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_BRK_DET_INT_ENA_V,(val),UART_BRK_DET_INT_ENA_S)
- #define UART_GET_CTS_CHG_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_CTS_CHG_INT_ENA_V, UART_CTS_CHG_INT_ENA_S)
- #define UART_SET_CTS_CHG_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_CTS_CHG_INT_ENA_V,(val),UART_CTS_CHG_INT_ENA_S)
- #define UART_GET_DSR_CHG_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_DSR_CHG_INT_ENA_V, UART_DSR_CHG_INT_ENA_S)
- #define UART_SET_DSR_CHG_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_DSR_CHG_INT_ENA_V,(val),UART_DSR_CHG_INT_ENA_S)
- #define UART_GET_RXFIFO_OVF_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RXFIFO_OVF_INT_ENA_V, UART_RXFIFO_OVF_INT_ENA_S)
- #define UART_SET_RXFIFO_OVF_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RXFIFO_OVF_INT_ENA_V,(val),UART_RXFIFO_OVF_INT_ENA_S)
- #define UART_GET_FRM_ERR_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_FRM_ERR_INT_ENA_V, UART_FRM_ERR_INT_ENA_S)
- #define UART_SET_FRM_ERR_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_FRM_ERR_INT_ENA_V,(val),UART_FRM_ERR_INT_ENA_S)
- #define UART_GET_PARITY_ERR_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_PARITY_ERR_INT_ENA_V, UART_PARITY_ERR_INT_ENA_S)
- #define UART_SET_PARITY_ERR_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_PARITY_ERR_INT_ENA_V,(val),UART_PARITY_ERR_INT_ENA_S)
- #define UART_GET_TXFIFO_EMPTY_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_TXFIFO_EMPTY_INT_ENA_V, UART_TXFIFO_EMPTY_INT_ENA_S)
- #define UART_SET_TXFIFO_EMPTY_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_TXFIFO_EMPTY_INT_ENA_V,(val),UART_TXFIFO_EMPTY_INT_ENA_S)
- #define UART_GET_RXFIFO_FULL_INT_ENA(i) GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RXFIFO_FULL_INT_ENA_V, UART_RXFIFO_FULL_INT_ENA_S)
- #define UART_SET_RXFIFO_FULL_INT_ENA(i,val) SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RXFIFO_FULL_INT_ENA_V,(val),UART_RXFIFO_FULL_INT_ENA_S)
-
-
-
-#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
- /* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
- /*description: Set this bit for detecting AT_CMD char interrupt*/
- #define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18))
- #define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18))
- #define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1
- #define UART_AT_CMD_CHAR_DET_INT_CLR_S 18
- /* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
- /*description: Set this bit for rs485 tx rx clash interrrupt*/
- #define UART_RS485_CLASH_INT_CLR (BIT(17))
- #define UART_RS485_CLASH_INT_CLR_M (BIT(17))
- #define UART_RS485_CLASH_INT_CLR_V 0x1
- #define UART_RS485_CLASH_INT_CLR_S 17
- /* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
- /*description: Set this bit for rs485 other rx error*/
- #define UART_RS485_FRM_ERR_INT_CLR (BIT(16))
- #define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16))
- #define UART_RS485_FRM_ERR_INT_CLR_V 0x1
- #define UART_RS485_FRM_ERR_INT_CLR_S 16
- /* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
- /*description: Set this bit for rs485 parity error interrupt*/
- #define UART_RS485_PARITY_ERR_INT_CLR (BIT(15))
- #define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15))
- #define UART_RS485_PARITY_ERR_INT_CLR_V 0x1
- #define UART_RS485_PARITY_ERR_INT_CLR_S 15
- /* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
- /*description: Set this bit to clear the tx done interrupt*/
- #define UART_TX_DONE_INT_CLR (BIT(14))
- #define UART_TX_DONE_INT_CLR_M (BIT(14))
- #define UART_TX_DONE_INT_CLR_V 0x1
- #define UART_TX_DONE_INT_CLR_S 14
- /* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
- /*description: Set this bit to clear the tx send idle done interrupt*/
- #define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13))
- #define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13))
- #define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1
- #define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13
- /* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
- /*description: Set this bit to clear the send 0 done interrupt*/
- #define UART_TX_BRK_DONE_INT_CLR (BIT(12))
- #define UART_TX_BRK_DONE_INT_CLR_M (BIT(12))
- #define UART_TX_BRK_DONE_INT_CLR_V 0x1
- #define UART_TX_BRK_DONE_INT_CLR_S 12
- /* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
- /*description: Set this bit to clear the detecting rx glitch pulse interrupt*/
- #define UART_GLITCH_DET_INT_CLR (BIT(11))
- #define UART_GLITCH_DET_INT_CLR_M (BIT(11))
- #define UART_GLITCH_DET_INT_CLR_V 0x1
- #define UART_GLITCH_DET_INT_CLR_S 11
- /* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
- /*description: Set this bit to clear the rx receive xoff char interrupt*/
- #define UART_SW_XOFF_INT_CLR (BIT(10))
- #define UART_SW_XOFF_INT_CLR_M (BIT(10))
- #define UART_SW_XOFF_INT_CLR_V 0x1
- #define UART_SW_XOFF_INT_CLR_S 10
- /* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
- /*description: Set this bit to clear the rx receive xon char interrupt*/
- #define UART_SW_XON_INT_CLR (BIT(9))
- #define UART_SW_XON_INT_CLR_M (BIT(9))
- #define UART_SW_XON_INT_CLR_V 0x1
- #define UART_SW_XON_INT_CLR_S 9
- /* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
- /*description: Set this bit to clear the rx time-out interrupt*/
- #define UART_RXFIFO_TOUT_INT_CLR (BIT(8))
- #define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8))
- #define UART_RXFIFO_TOUT_INT_CLR_V 0x1
- #define UART_RXFIFO_TOUT_INT_CLR_S 8
- /* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
- /*description: Set this bit to clear the rx byte start interrupt*/
- #define UART_BRK_DET_INT_CLR (BIT(7))
- #define UART_BRK_DET_INT_CLR_M (BIT(7))
- #define UART_BRK_DET_INT_CLR_V 0x1
- #define UART_BRK_DET_INT_CLR_S 7
- /* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
- /*description: Set this bit to clear the CTS changing interrupt*/
- #define UART_CTS_CHG_INT_CLR (BIT(6))
- #define UART_CTS_CHG_INT_CLR_M (BIT(6))
- #define UART_CTS_CHG_INT_CLR_V 0x1
- #define UART_CTS_CHG_INT_CLR_S 6
- /* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
- /*description: Set this bit to clear the DSR changing interrupt*/
- #define UART_DSR_CHG_INT_CLR (BIT(5))
- #define UART_DSR_CHG_INT_CLR_M (BIT(5))
- #define UART_DSR_CHG_INT_CLR_V 0x1
- #define UART_DSR_CHG_INT_CLR_S 5
- /* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
- /*description: Set this bit to clear the rx fifo over-flow interrupt*/
- #define UART_RXFIFO_OVF_INT_CLR (BIT(4))
- #define UART_RXFIFO_OVF_INT_CLR_M (BIT(4))
- #define UART_RXFIFO_OVF_INT_CLR_V 0x1
- #define UART_RXFIFO_OVF_INT_CLR_S 4
- /* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
- /*description: Set this bit to clear other rx error interrupt*/
- #define UART_FRM_ERR_INT_CLR (BIT(3))
- #define UART_FRM_ERR_INT_CLR_M (BIT(3))
- #define UART_FRM_ERR_INT_CLR_V 0x1
- #define UART_FRM_ERR_INT_CLR_S 3
- /* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
- /*description: Set this bit to clear the parity error interrupt*/
- #define UART_PARITY_ERR_INT_CLR (BIT(2))
- #define UART_PARITY_ERR_INT_CLR_M (BIT(2))
- #define UART_PARITY_ERR_INT_CLR_V 0x1
- #define UART_PARITY_ERR_INT_CLR_S 2
- /* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
- /*description: Set this bit to clear the tx fifo empty interrupt*/
- #define UART_TXFIFO_EMPTY_INT_CLR (BIT(1))
- #define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
- #define UART_TXFIFO_EMPTY_INT_CLR_V 0x1
- #define UART_TXFIFO_EMPTY_INT_CLR_S 1
- /* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
- /*description: Set this bit to clear the rx fifo full interrupt*/
- #define UART_RXFIFO_FULL_INT_CLR (BIT(0))
- #define UART_RXFIFO_FULL_INT_CLR_M (BIT(0))
- #define UART_RXFIFO_FULL_INT_CLR_V 0x1
- #define UART_RXFIFO_FULL_INT_CLR_S 0
- #define UART_SET_AT_CMD_CHAR_DET_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_AT_CMD_CHAR_DET_INT_CLR_V,(val),UART_AT_CMD_CHAR_DET_INT_CLR_S)
- #define UART_SET_RS485_CLASH_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RS485_CLASH_INT_CLR_V,(val),UART_RS485_CLASH_INT_CLR_S)
- #define UART_SET_RS485_FRM_ERR_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RS485_FRM_ERR_INT_CLR_V,(val),UART_RS485_FRM_ERR_INT_CLR_S)
- #define UART_SET_RS485_PARITY_ERR_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RS485_PARITY_ERR_INT_CLR_V,(val),UART_RS485_PARITY_ERR_INT_CLR_S)
- #define UART_SET_TX_DONE_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_TX_DONE_INT_CLR_V,(val),UART_TX_DONE_INT_CLR_S)
- #define UART_SET_TX_BRK_IDLE_DONE_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_TX_BRK_IDLE_DONE_INT_CLR_V,(val),UART_TX_BRK_IDLE_DONE_INT_CLR_S)
- #define UART_SET_TX_BRK_DONE_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_TX_BRK_DONE_INT_CLR_V,(val),UART_TX_BRK_DONE_INT_CLR_S)
- #define UART_SET_GLITCH_DET_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_GLITCH_DET_INT_CLR_V,(val),UART_GLITCH_DET_INT_CLR_S)
- #define UART_SET_SW_XOFF_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_SW_XOFF_INT_CLR_V,(val),UART_SW_XOFF_INT_CLR_S)
- #define UART_SET_SW_XON_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_SW_XON_INT_CLR_V,(val),UART_SW_XON_INT_CLR_S)
- #define UART_SET_RXFIFO_TOUT_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RXFIFO_TOUT_INT_CLR_V,(val),UART_RXFIFO_TOUT_INT_CLR_S)
- #define UART_SET_BRK_DET_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_BRK_DET_INT_CLR_V,(val),UART_BRK_DET_INT_CLR_S)
- #define UART_SET_CTS_CHG_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_CTS_CHG_INT_CLR_V,(val),UART_CTS_CHG_INT_CLR_S)
- #define UART_SET_DSR_CHG_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_DSR_CHG_INT_CLR_V,(val),UART_DSR_CHG_INT_CLR_S)
- #define UART_SET_RXFIFO_OVF_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RXFIFO_OVF_INT_CLR_V,(val),UART_RXFIFO_OVF_INT_CLR_S)
- #define UART_SET_FRM_ERR_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_FRM_ERR_INT_CLR_V,(val),UART_FRM_ERR_INT_CLR_S)
- #define UART_SET_PARITY_ERR_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_PARITY_ERR_INT_CLR_V,(val),UART_PARITY_ERR_INT_CLR_S)
- #define UART_SET_TXFIFO_EMPTY_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_TXFIFO_EMPTY_INT_CLR_V,(val),UART_TXFIFO_EMPTY_INT_CLR_S)
- #define UART_SET_RXFIFO_FULL_INT_CLR(i,val) SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RXFIFO_FULL_INT_CLR_V,(val),UART_RXFIFO_FULL_INT_CLR_S)
-
-
-
-#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)
- /* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'b0 ; */
- /*description: The decimal part of divider*/
- #define UART_CLKDIV_FRAG 0x0000000F
- #define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
- #define UART_CLKDIV_FRAG_V 0xF
- #define UART_CLKDIV_FRAG_S 20
- /* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */
- /*description: The interger part of divider BAUDRATE = UART_CLK_FREQ / UART_CLKDIV*/
- #define UART_CLKDIV 0x000FFFFF
- #define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
- #define UART_CLKDIV_V 0xFFFFF
- #define UART_CLKDIV_S 0
- #define UART_GET_CLKDIV_FRAG(i) GET_PERI_REG_BITS2(UART_CLKDIV_REG(i) , UART_CLKDIV_FRAG_V, UART_CLKDIV_FRAG_S)
- #define UART_SET_CLKDIV_FRAG(i,val) SET_PERI_REG_BITS(UART_CLKDIV_REG(i) ,UART_CLKDIV_FRAG_V,(val),UART_CLKDIV_FRAG_S)
- #define UART_GET_CLKDIV(i) GET_PERI_REG_BITS2(UART_CLKDIV_REG(i) , UART_CLKDIV_V, UART_CLKDIV_S)
- #define UART_SET_CLKDIV(i,val) SET_PERI_REG_BITS(UART_CLKDIV_REG(i) ,UART_CLKDIV_V,(val),UART_CLKDIV_S)
-
-
-
-#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18)
- /* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */
- /*description: ignore the glitch when pulse cnt is lower then this value*/
- #define UART_GLITCH_FILT 0x000000FF
- #define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
- #define UART_GLITCH_FILT_V 0xFF
- #define UART_GLITCH_FILT_S 8
- /* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
- /*description: Set this bit to enable baudrate detect*/
- #define UART_AUTOBAUD_EN (BIT(0))
- #define UART_AUTOBAUD_EN_M (BIT(0))
- #define UART_AUTOBAUD_EN_V 0x1
- #define UART_AUTOBAUD_EN_S 0
- #define UART_GET_GLITCH_FILT(i) GET_PERI_REG_BITS2(UART_AUTOBAUD_REG(i) , UART_GLITCH_FILT_V, UART_GLITCH_FILT_S)
- #define UART_SET_GLITCH_FILT(i,val) SET_PERI_REG_BITS(UART_AUTOBAUD_REG(i) ,UART_GLITCH_FILT_V,(val),UART_GLITCH_FILT_S)
- #define UART_GET_AUTOBAUD_EN(i) GET_PERI_REG_BITS2(UART_AUTOBAUD_REG(i) , UART_AUTOBAUD_EN_V, UART_AUTOBAUD_EN_S)
- #define UART_SET_AUTOBAUD_EN(i,val) SET_PERI_REG_BITS(UART_AUTOBAUD_REG(i) ,UART_AUTOBAUD_EN_V,(val),UART_AUTOBAUD_EN_S)
-
-
-
-#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C)
- /* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */
- /*description: The level of the internal uart txd value*/
- #define UART_TXD (BIT(31))
- #define UART_TXD_M (BIT(31))
- #define UART_TXD_V 0x1
- #define UART_TXD_S 31
- /* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */
- /*description: The level of the internal uart rts pin*/
- #define UART_RTSN (BIT(30))
- #define UART_RTSN_M (BIT(30))
- #define UART_RTSN_V 0x1
- #define UART_RTSN_S 30
- /* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */
- /*description: The level of the internaluart dtr pin*/
- #define UART_DTRN (BIT(29))
- #define UART_DTRN_M (BIT(29))
- #define UART_DTRN_V 0x1
- #define UART_DTRN_S 29
- /* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */
- /*description: The state for transmitting data. 4'd0:TX_IDLE*/
- #define UART_ST_UTX_OUT 0x0000000F
- #define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
- #define UART_ST_UTX_OUT_V 0xF
- #define UART_ST_UTX_OUT_S 24
- /* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
- /*description: Number of data in UART TX fifo*/
- #define UART_TXFIFO_CNT 0x000000FF
- #define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
- #define UART_TXFIFO_CNT_V 0xFF
- #define UART_TXFIFO_CNT_S 16
- /* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */
- /*description: The level of the internal uart rxd value*/
- #define UART_RXD (BIT(15))
- #define UART_RXD_M (BIT(15))
- #define UART_RXD_V 0x1
- #define UART_RXD_S 15
- /* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */
- /*description: The level of the internal uart cts value*/
- #define UART_CTSN (BIT(14))
- #define UART_CTSN_M (BIT(14))
- #define UART_CTSN_V 0x1
- #define UART_CTSN_S 14
- /* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
- /*description: The level of the internal uart dsr value*/
- #define UART_DSRN (BIT(13))
- #define UART_DSRN_M (BIT(13))
- #define UART_DSRN_V 0x1
- #define UART_DSRN_S 13
- /* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */
- /*description: The state for receiving data. 4‘d0: RX_IDLE*/
- #define UART_ST_URX_OUT 0x0000000F
- #define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
- #define UART_ST_URX_OUT_V 0xF
- #define UART_ST_URX_OUT_S 8
- /* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */
- /*description: Number of data in UART RX fifo*/
- #define UART_RXFIFO_CNT 0x000000FF
- #define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
- #define UART_RXFIFO_CNT_V 0xFF
- #define UART_RXFIFO_CNT_S 0
- #define UART_GET_TXD(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_TXD_V, UART_TXD_S)
- #define UART_GET_RTSN(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_RTSN_V, UART_RTSN_S)
- #define UART_GET_DTRN(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_DTRN_V, UART_DTRN_S)
- #define UART_GET_ST_UTX_OUT(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_ST_UTX_OUT_V, UART_ST_UTX_OUT_S)
- #define UART_GET_TXFIFO_CNT(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_TXFIFO_CNT_V, UART_TXFIFO_CNT_S)
- #define UART_GET_RXD(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_RXD_V, UART_RXD_S)
- #define UART_GET_CTSN(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_CTSN_V, UART_CTSN_S)
- #define UART_GET_DSRN(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_DSRN_V, UART_DSRN_S)
- #define UART_GET_ST_URX_OUT(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_ST_URX_OUT_V, UART_ST_URX_OUT_S)
- #define UART_GET_RXFIFO_CNT(i) GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_RXFIFO_CNT_V, UART_RXFIFO_CNT_S)
-
-
-
-#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)
- /* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */
- /*description: 1：use apb clock：use referrence clock*/
- #define UART_TICK_REF_ALWAYS_ON (BIT(27))
- #define UART_TICK_REF_ALWAYS_ON_M (BIT(27))
- #define UART_TICK_REF_ALWAYS_ON_V 0x1
- #define UART_TICK_REF_ALWAYS_ON_S 27
- /* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
- /*description: 1：rx stop storing data int rxfifo when data is error 0：if received data is wrong*/
- #define UART_ERR_WR_MASK (BIT(26))
- #define UART_ERR_WR_MASK_M (BIT(26))
- #define UART_ERR_WR_MASK_V 0x1
- #define UART_ERR_WR_MASK_S 26
- /* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
- /*description: 1：force clock on for registers：support clock only when write registers*/
- #define UART_CLK_EN (BIT(25))
- #define UART_CLK_EN_M (BIT(25))
- #define UART_CLK_EN_V 0x1
- #define UART_CLK_EN_S 25
- /* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
- /*description: Set this bit to inverse uart dtr level*/
- #define UART_DTR_INV (BIT(24))
- #define UART_DTR_INV_M (BIT(24))
- #define UART_DTR_INV_V 0x1
- #define UART_DTR_INV_S 24
- /* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
- /*description: Set this bit to inverse uart rts level*/
- #define UART_RTS_INV (BIT(23))
- #define UART_RTS_INV_M (BIT(23))
- #define UART_RTS_INV_V 0x1
- #define UART_RTS_INV_S 23
- /* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
- /*description: Set this bit to inverse uart txd level*/
- #define UART_TXD_INV (BIT(22))
- #define UART_TXD_INV_M (BIT(22))
- #define UART_TXD_INV_V 0x1
- #define UART_TXD_INV_S 22
- /* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
- /*description: Set this bit to inverse uart dsr level*/
- #define UART_DSR_INV (BIT(21))
- #define UART_DSR_INV_M (BIT(21))
- #define UART_DSR_INV_V 0x1
- #define UART_DSR_INV_S 21
- /* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
- /*description: Set this bit to inverse uart cts level*/
- #define UART_CTS_INV (BIT(20))
- #define UART_CTS_INV_M (BIT(20))
- #define UART_CTS_INV_V 0x1
- #define UART_CTS_INV_S 20
- /* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
- /*description: Set this bit to inverse uart rxd level*/
- #define UART_RXD_INV (BIT(19))
- #define UART_RXD_INV_M (BIT(19))
- #define UART_RXD_INV_V 0x1
- #define UART_RXD_INV_S 19
- /* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
- /*description: Set this bit to reset uart tx fifo*/
- #define UART_TXFIFO_RST (BIT(18))
- #define UART_TXFIFO_RST_M (BIT(18))
- #define UART_TXFIFO_RST_V 0x1
- #define UART_TXFIFO_RST_S 18
- /* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
- /*description: Set this bit to reset uart rx fifo*/
- #define UART_RXFIFO_RST (BIT(17))
- #define UART_RXFIFO_RST_M (BIT(17))
- #define UART_RXFIFO_RST_V 0x1
- #define UART_RXFIFO_RST_S 17
- /* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
- /*description: Set this bit to enable irda protocol*/
- #define UART_IRDA_EN (BIT(16))
- #define UART_IRDA_EN_M (BIT(16))
- #define UART_IRDA_EN_V 0x1
- #define UART_IRDA_EN_S 16
- /* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
- /*description: Set this bit to enable tx flow control*/
- #define UART_TX_FLOW_EN (BIT(15))
- #define UART_TX_FLOW_EN_M (BIT(15))
- #define UART_TX_FLOW_EN_V 0x1
- #define UART_TX_FLOW_EN_S 15
- /* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
- /*description: Set this bit to enable uart loopback test mode*/
- #define UART_LOOPBACK (BIT(14))
- #define UART_LOOPBACK_M (BIT(14))
- #define UART_LOOPBACK_V 0x1
- #define UART_LOOPBACK_S 14
- /* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
- /*description: Set this bit to inverse irda rx level*/
- #define UART_IRDA_RX_INV (BIT(13))
- #define UART_IRDA_RX_INV_M (BIT(13))
- #define UART_IRDA_RX_INV_V 0x1
- #define UART_IRDA_RX_INV_S 13
- /* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
- /*description: Set this bit to inverse irda tx level*/
- #define UART_IRDA_TX_INV (BIT(12))
- #define UART_IRDA_TX_INV_M (BIT(12))
- #define UART_IRDA_TX_INV_V 0x1
- #define UART_IRDA_TX_INV_S 12
- /* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
- /*description: 1：the tx 11th bit is the same to the 10th bit 0：set tx 11th bit to 0*/
- #define UART_IRDA_WCTL (BIT(11))
- #define UART_IRDA_WCTL_M (BIT(11))
- #define UART_IRDA_WCTL_V 0x1
- #define UART_IRDA_WCTL_S 11
- /* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
- /*description: Set this bit to enable irda to send data*/
- #define UART_IRDA_TX_EN (BIT(10))
- #define UART_IRDA_TX_EN_M (BIT(10))
- #define UART_IRDA_TX_EN_V 0x1
- #define UART_IRDA_TX_EN_S 10
- /* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
- /*description: Set this bit to enable irda duplex mode*/
- #define UART_IRDA_DPLX (BIT(9))
- #define UART_IRDA_DPLX_M (BIT(9))
- #define UART_IRDA_DPLX_V 0x1
- #define UART_IRDA_DPLX_S 9
- /* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
- /*description: Set this bit to enbale tx send 0*/
- #define UART_TXD_BRK (BIT(8))
- #define UART_TXD_BRK_M (BIT(8))
- #define UART_TXD_BRK_V 0x1
- #define UART_TXD_BRK_S 8
- /* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
- /*description: sw dtr*/
- #define UART_SW_DTR (BIT(7))
- #define UART_SW_DTR_M (BIT(7))
- #define UART_SW_DTR_V 0x1
- #define UART_SW_DTR_S 7
- /* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
- /*description: sw rts*/
- #define UART_SW_RTS (BIT(6))
- #define UART_SW_RTS_M (BIT(6))
- #define UART_SW_RTS_V 0x1
- #define UART_SW_RTS_S 6
- /* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
- /*description: Set stop bit: 1:1bit 2:1.5bits 3:2bits*/
- #define UART_STOP_BIT_NUM 0x00000003
- #define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
- #define UART_STOP_BIT_NUM_V 0x3
- #define UART_STOP_BIT_NUM_S 4
- /* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
- /*description: Set bit num: 0:5bits 1:6bits 2:7bits 3:8bits*/
- #define UART_BIT_NUM 0x00000003
- #define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
- #define UART_BIT_NUM_V 0x3
- #define UART_BIT_NUM_S 2
- /* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
- /*description: Set this bit to enable uart parity check*/
- #define UART_PARITY_EN (BIT(1))
- #define UART_PARITY_EN_M (BIT(1))
- #define UART_PARITY_EN_V 0x1
- #define UART_PARITY_EN_S 1
- /* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
- /*description: Set parity check: 0:even 1:odd*/
- #define UART_PARITY (BIT(0))
- #define UART_PARITY_M (BIT(0))
- #define UART_PARITY_V 0x1
- #define UART_PARITY_S 0
- #define UART_GET_TICK_REF_ALWAYS_ON(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TICK_REF_ALWAYS_ON_V, UART_TICK_REF_ALWAYS_ON_S)
- #define UART_SET_TICK_REF_ALWAYS_ON(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TICK_REF_ALWAYS_ON_V,(val),UART_TICK_REF_ALWAYS_ON_S)
- #define UART_GET_ERR_WR_MASK(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_ERR_WR_MASK_V, UART_ERR_WR_MASK_S)
- #define UART_SET_ERR_WR_MASK(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_ERR_WR_MASK_V,(val),UART_ERR_WR_MASK_S)
- #define UART_GET_REG_CLK_EN(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_CLK_EN_V, UART_CLK_EN_S)
- #define UART_SET_REG_CLK_EN(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_CLK_EN_V,(val),UART_CLK_EN_S)
- #define UART_GET_DTR_INV(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_DTR_INV_V, UART_DTR_INV_S)
- #define UART_SET_DTR_INV(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_DTR_INV_V,(val),UART_DTR_INV_S)
- #define UART_GET_RTS_INV(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_RTS_INV_V, UART_RTS_INV_S)
- #define UART_SET_RTS_INV(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_RTS_INV_V,(val),UART_RTS_INV_S)
- #define UART_GET_TXD_INV(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TXD_INV_V, UART_TXD_INV_S)
- #define UART_SET_TXD_INV(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TXD_INV_V,(val),UART_TXD_INV_S)
- #define UART_GET_DSR_INV(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_DSR_INV_V, UART_DSR_INV_S)
- #define UART_SET_DSR_INV(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_DSR_INV_V,(val),UART_DSR_INV_S)
- #define UART_GET_CTS_INV(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_CTS_INV_V, UART_CTS_INV_S)
- #define UART_SET_CTS_INV(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_CTS_INV_V,(val),UART_CTS_INV_S)
- #define UART_GET_RXD_INV(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_RXD_INV_V, UART_RXD_INV_S)
- #define UART_SET_RXD_INV(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_RXD_INV_V,(val),UART_RXD_INV_S)
- #define UART_GET_TXFIFO_RST(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TXFIFO_RST_V, UART_TXFIFO_RST_S)
- #define UART_SET_TXFIFO_RST(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TXFIFO_RST_V,(val),UART_TXFIFO_RST_S)
- #define UART_GET_RXFIFO_RST(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_RXFIFO_RST_V, UART_RXFIFO_RST_S)
- #define UART_SET_RXFIFO_RST(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_RXFIFO_RST_V,(val),UART_RXFIFO_RST_S)
- #define UART_GET_IRDA_EN(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_EN_V, UART_IRDA_EN_S)
- #define UART_SET_IRDA_EN(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_EN_V,(val),UART_IRDA_EN_S)
- #define UART_GET_TX_FLOW_EN(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TX_FLOW_EN_V, UART_TX_FLOW_EN_S)
- #define UART_SET_TX_FLOW_EN(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TX_FLOW_EN_V,(val),UART_TX_FLOW_EN_S)
- #define UART_GET_LOOPBACK(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_LOOPBACK_V, UART_LOOPBACK_S)
- #define UART_SET_LOOPBACK(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_LOOPBACK_V,(val),UART_LOOPBACK_S)
- #define UART_GET_IRDA_RX_INV(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_RX_INV_V, UART_IRDA_RX_INV_S)
- #define UART_SET_IRDA_RX_INV(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_RX_INV_V,(val),UART_IRDA_RX_INV_S)
- #define UART_GET_IRDA_TX_INV(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_TX_INV_V, UART_IRDA_TX_INV_S)
- #define UART_SET_IRDA_TX_INV(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_TX_INV_V,(val),UART_IRDA_TX_INV_S)
- #define UART_GET_IRDA_WCTL(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_WCTL_V, UART_IRDA_WCTL_S)
- #define UART_SET_IRDA_WCTL(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_WCTL_V,(val),UART_IRDA_WCTL_S)
- #define UART_GET_IRDA_TX_EN(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_TX_EN_V, UART_IRDA_TX_EN_S)
- #define UART_SET_IRDA_TX_EN(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_TX_EN_V,(val),UART_IRDA_TX_EN_S)
- #define UART_GET_IRDA_DPLX(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_DPLX_V, UART_IRDA_DPLX_S)
- #define UART_SET_IRDA_DPLX(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_DPLX_V,(val),UART_IRDA_DPLX_S)
- #define UART_GET_TXD_BRK(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TXD_BRK_V, UART_TXD_BRK_S)
- #define UART_SET_TXD_BRK(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TXD_BRK_V,(val),UART_TXD_BRK_S)
- #define UART_GET_SW_DTR(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_SW_DTR_V, UART_SW_DTR_S)
- #define UART_SET_SW_DTR(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_SW_DTR_V,(val),UART_SW_DTR_S)
- #define UART_GET_SW_RTS(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_SW_RTS_V, UART_SW_RTS_S)
- #define UART_SET_SW_RTS(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_SW_RTS_V,(val),UART_SW_RTS_S)
- #define UART_GET_STOP_BIT_NUM(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_STOP_BIT_NUM_V, UART_STOP_BIT_NUM_S)
- #define UART_SET_STOP_BIT_NUM(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_STOP_BIT_NUM_V,(val),UART_STOP_BIT_NUM_S)
- #define UART_GET_BIT_NUM(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_BIT_NUM_V, UART_BIT_NUM_S)
- #define UART_SET_BIT_NUM(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_BIT_NUM_V,(val),UART_BIT_NUM_S)
- #define UART_GET_PARITY_EN(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_PARITY_EN_V, UART_PARITY_EN_S)
- #define UART_SET_PARITY_EN(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_PARITY_EN_V,(val),UART_PARITY_EN_S)
- #define UART_GET_PARITY(i) GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_PARITY_V, UART_PARITY_S)
- #define UART_SET_PARITY(i,val) SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_PARITY_V,(val),UART_PARITY_S)
-
-
-
-#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
- /* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
- /*description: Set this bit to enable rx time-out function*/
- #define UART_RX_TOUT_EN (BIT(31))
- #define UART_RX_TOUT_EN_M (BIT(31))
- #define UART_RX_TOUT_EN_V 0x1
- #define UART_RX_TOUT_EN_S 31
- /* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */
- /*description: Config bits for rx time-out threshold*/
- #define UART_RX_TOUT_THRHD 0x0000007F
- #define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
- #define UART_RX_TOUT_THRHD_V 0x7F
- #define UART_RX_TOUT_THRHD_S 24
- /* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
- /*description: Set this bit to enable rx hardware flow control*/
- #define UART_RX_FLOW_EN (BIT(23))
- #define UART_RX_FLOW_EN_M (BIT(23))
- #define UART_RX_FLOW_EN_V 0x1
- #define UART_RX_FLOW_EN_S 23
- /* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */
- /*description: The config bits for rx flow control threshold*/
- #define UART_RX_FLOW_THRHD 0x0000007F
- #define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
- #define UART_RX_FLOW_THRHD_V 0x7F
- #define UART_RX_FLOW_THRHD_S 16
- /* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */
- /*description: The config bits for tx fifo empty threshold*/
- #define UART_TXFIFO_EMPTY_THRHD 0x0000007F
- #define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
- #define UART_TXFIFO_EMPTY_THRHD_V 0x7F
- #define UART_TXFIFO_EMPTY_THRHD_S 8
- /* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */
- /*description: The config bits for rx fifo full threshold*/
- #define UART_RXFIFO_FULL_THRHD 0x0000007F
- #define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
- #define UART_RXFIFO_FULL_THRHD_V 0x7F
- #define UART_RXFIFO_FULL_THRHD_S 0
- #define UART_GET_RX_TOUT_EN(i) GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RX_TOUT_EN_V, UART_RX_TOUT_EN_S)
- #define UART_SET_RX_TOUT_EN(i,val) SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RX_TOUT_EN_V,(val),UART_RX_TOUT_EN_S)
- #define UART_GET_RX_TOUT_THRHD(i) GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RX_TOUT_THRHD_V, UART_RX_TOUT_THRHD_S)
- #define UART_SET_RX_TOUT_THRHD(i,val) SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RX_TOUT_THRHD_V,(val),UART_RX_TOUT_THRHD_S)
- #define UART_GET_RX_FLOW_EN(i) GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RX_FLOW_EN_V, UART_RX_FLOW_EN_S)
- #define UART_SET_RX_FLOW_EN(i,val) SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RX_FLOW_EN_V,(val),UART_RX_FLOW_EN_S)
- #define UART_GET_RX_FLOW_THRHD(i) GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RX_FLOW_THRHD_V, UART_RX_FLOW_THRHD_S)
- #define UART_SET_RX_FLOW_THRHD(i,val) SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RX_FLOW_THRHD_V,(val),UART_RX_FLOW_THRHD_S)
- #define UART_GET_TXFIFO_EMPTY_THRHD(i) GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_TXFIFO_EMPTY_THRHD_V, UART_TXFIFO_EMPTY_THRHD_S)
- #define UART_SET_TXFIFO_EMPTY_THRHD(i,val) SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_TXFIFO_EMPTY_THRHD_V,(val),UART_TXFIFO_EMPTY_THRHD_S)
- #define UART_GET_RXFIFO_FULL_THRHD(i) GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RXFIFO_FULL_THRHD_V, UART_RXFIFO_FULL_THRHD_S)
- #define UART_SET_RXFIFO_FULL_THRHD(i,val) SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RXFIFO_FULL_THRHD_V,(val),UART_RXFIFO_FULL_THRHD_S)
-
-
-
-#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)
- /* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
- /*description: used in baudrate detect*/
- #define UART_LOWPULSE_MIN_CNT 0x000FFFFF
- #define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
- #define UART_LOWPULSE_MIN_CNT_V 0xFFFFF
- #define UART_LOWPULSE_MIN_CNT_S 0
- #define UART_GET_LOWPULSE_MIN_CNT(i) GET_PERI_REG_BITS2(UART_LOWPULSE_REG(i) , UART_LOWPULSE_MIN_CNT_V, UART_LOWPULSE_MIN_CNT_S)
-
-
-
-#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)
- /* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
- /*description: used in baudrate detect*/
- #define UART_HIGHPULSE_MIN_CNT 0x000FFFFF
- #define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
- #define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF
- #define UART_HIGHPULSE_MIN_CNT_S 0
- #define UART_GET_HIGHPULSE_MIN_CNT(i) GET_PERI_REG_BITS2(UART_HIGHPULSE_REG(i) , UART_HIGHPULSE_MIN_CNT_V, UART_HIGHPULSE_MIN_CNT_S)
-
-
-
-#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
- /* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
- /*description: used in baudrate detect*/
- #define UART_RXD_EDGE_CNT 0x000003FF
- #define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
- #define UART_RXD_EDGE_CNT_V 0x3FF
- #define UART_RXD_EDGE_CNT_S 0
- #define UART_GET_RXD_EDGE_CNT(i) GET_PERI_REG_BITS2(UART_RXD_CNT_REG(i) , UART_RXD_EDGE_CNT_V, UART_RXD_EDGE_CNT_S)
-
-
-
-#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)
- /* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */
- /*description: */
- #define UART_SEND_XOFF (BIT(5))
- #define UART_SEND_XOFF_M (BIT(5))
- #define UART_SEND_XOFF_V 0x1
- #define UART_SEND_XOFF_S 5
- /* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */
- /*description: */
- #define UART_SEND_XON (BIT(4))
- #define UART_SEND_XON_M (BIT(4))
- #define UART_SEND_XON_V 0x1
- #define UART_SEND_XON_S 4
- /* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
- /*description: Set this bit to set ctsn*/
- #define UART_FORCE_XOFF (BIT(3))
- #define UART_FORCE_XOFF_M (BIT(3))
- #define UART_FORCE_XOFF_V 0x1
- #define UART_FORCE_XOFF_S 3
- /* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
- /*description: Set this bit to clear ctsn*/
- #define UART_FORCE_XON (BIT(2))
- #define UART_FORCE_XON_M (BIT(2))
- #define UART_FORCE_XON_V 0x1
- #define UART_FORCE_XON_S 2
- /* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
- /*description: Set this bit to remove flow control char from rx data*/
- #define UART_XONOFF_DEL (BIT(1))
- #define UART_XONOFF_DEL_M (BIT(1))
- #define UART_XONOFF_DEL_V 0x1
- #define UART_XONOFF_DEL_S 1
- /* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
- /*description: Set this bit to enable sw flow control*/
- #define UART_SW_FLOW_CON_EN (BIT(0))
- #define UART_SW_FLOW_CON_EN_M (BIT(0))
- #define UART_SW_FLOW_CON_EN_V 0x1
- #define UART_SW_FLOW_CON_EN_S 0
- #define UART_GET_SEND_XOFF(i) GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_SEND_XOFF_V, UART_SEND_XOFF_S)
- #define UART_SET_SEND_XOFF(i,val) SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_SEND_XOFF_V,(val),UART_SEND_XOFF_S)
- #define UART_GET_SEND_XON(i) GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_SEND_XON_V, UART_SEND_XON_S)
- #define UART_SET_SEND_XON(i,val) SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_SEND_XON_V,(val),UART_SEND_XON_S)
- #define UART_GET_FORCE_XOFF(i) GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_FORCE_XOFF_V, UART_FORCE_XOFF_S)
- #define UART_SET_FORCE_XOFF(i,val) SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_FORCE_XOFF_V,(val),UART_FORCE_XOFF_S)
- #define UART_GET_FORCE_XON(i) GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_FORCE_XON_V, UART_FORCE_XON_S)
- #define UART_SET_FORCE_XON(i,val) SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_FORCE_XON_V,(val),UART_FORCE_XON_S)
- #define UART_GET_XONOFF_DEL(i) GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_XONOFF_DEL_V, UART_XONOFF_DEL_S)
- #define UART_SET_XONOFF_DEL(i,val) SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_XONOFF_DEL_V,(val),UART_XONOFF_DEL_S)
- #define UART_GET_SW_FLOW_CON_EN(i) GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_SW_FLOW_CON_EN_V, UART_SW_FLOW_CON_EN_S)
- #define UART_SET_SW_FLOW_CON_EN(i,val) SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_SW_FLOW_CON_EN_V,(val),UART_SW_FLOW_CON_EN_S)
-
-
-
-#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
- /* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
- /*description: when the num of rx level change is more than this value*/
- #define UART_ACTIVE_THRESHOLD 0x000003FF
- #define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
- #define UART_ACTIVE_THRESHOLD_V 0x3FF
- #define UART_ACTIVE_THRESHOLD_S 0
- #define UART_GET_ACTIVE_THRESHOLD(i) GET_PERI_REG_BITS2(UART_SLEEP_CONF_REG(i) , UART_ACTIVE_THRESHOLD_V, UART_ACTIVE_THRESHOLD_S)
- #define UART_SET_ACTIVE_THRESHOLD(i,val) SET_PERI_REG_BITS(UART_SLEEP_CONF_REG(i) ,UART_ACTIVE_THRESHOLD_V,(val),UART_ACTIVE_THRESHOLD_S)
-
-
-
-#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C)
- /* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */
- /*description: xoff char*/
- #define UART_XOFF_CHAR 0x000000FF
- #define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
- #define UART_XOFF_CHAR_V 0xFF
- #define UART_XOFF_CHAR_S 24
- /* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */
- /*description: xon char*/
- #define UART_XON_CHAR 0x000000FF
- #define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
- #define UART_XON_CHAR_V 0xFF
- #define UART_XON_CHAR_S 16
- /* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */
- /*description: rx stop receiving data when rxfifo_cnt is more than this value*/
- #define UART_XOFF_THRESHOLD 0x000000FF
- #define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
- #define UART_XOFF_THRESHOLD_V 0xFF
- #define UART_XOFF_THRESHOLD_S 8
- /* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
- /*description: rx continue receiving data when rxfifo cnt is less then this value*/
- #define UART_XON_THRESHOLD 0x000000FF
- #define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
- #define UART_XON_THRESHOLD_V 0xFF
- #define UART_XON_THRESHOLD_S 0
- #define UART_GET_XOFF_CH(i) GET_PERI_REG_BITS2(UART_SWFC_CONF_REG(i) , UART_XOFF_CHAR_V, UART_XOFF_CHAR_S)
- #define UART_SET_XOFF_CH(i,val) SET_PERI_REG_BITS(UART_SWFC_CONF_REG(i) ,UART_XOFF_CHAR_V,(val),UART_XOFF_CHAR_S)
- #define UART_GET_XON_CH(i) GET_PERI_REG_BITS2(UART_SWFC_CONF_REG(i) , UART_XON_CHAR_V, UART_XON_CHAR_S)
- #define UART_SET_XON_CH(i,val) SET_PERI_REG_BITS(UART_SWFC_CONF_REG(i) ,UART_XON_CHAR_V,(val),UART_XON_CHAR_S)
- #define UART_GET_XOFF_THRESHOLD(i) GET_PERI_REG_BITS2(UART_SWFC_CONF_REG(i) , UART_XOFF_THRESHOLD_V, UART_XOFF_THRESHOLD_S)
- #define UART_SET_XOFF_THRESHOLD(i,val) SET_PERI_REG_BITS(UART_SWFC_CONF_REG(i) ,UART_XOFF_THRESHOLD_V,(val),UART_XOFF_THRESHOLD_S)
- #define UART_GET_XON_THRESHOLD(i) GET_PERI_REG_BITS2(UART_SWFC_CONF_REG(i) , UART_XON_THRESHOLD_V, UART_XON_THRESHOLD_S)
- #define UART_SET_XON_THRESHOLD(i,val) SET_PERI_REG_BITS(UART_SWFC_CONF_REG(i) ,UART_XON_THRESHOLD_V,(val),UART_XON_THRESHOLD_S)
-
-
-
-#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40)
- /* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */
- /*description: brk number config*/
- #define UART_TX_BRK_NUM 0x000000FF
- #define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
- #define UART_TX_BRK_NUM_V 0xFF
- #define UART_TX_BRK_NUM_S 20
- /* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
- /*description: idle number config*/
- #define UART_TX_IDLE_NUM 0x000003FF
- #define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
- #define UART_TX_IDLE_NUM_V 0x3FF
- #define UART_TX_IDLE_NUM_S 10
- /* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
- /*description: rx idle number config*/
- #define UART_RX_IDLE_THRHD 0x000003FF
- #define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
- #define UART_RX_IDLE_THRHD_V 0x3FF
- #define UART_RX_IDLE_THRHD_S 0
- #define UART_GET_TX_BRK_NUM(i) GET_PERI_REG_BITS2(UART_IDLE_CONF_REG(i) , UART_TX_BRK_NUM_V, UART_TX_BRK_NUM_S)
- #define UART_SET_TX_BRK_NUM(i,val) SET_PERI_REG_BITS(UART_IDLE_CONF_REG(i) ,UART_TX_BRK_NUM_V,(val),UART_TX_BRK_NUM_S)
- #define UART_GET_TX_IDLE_NUM(i) GET_PERI_REG_BITS2(UART_IDLE_CONF_REG(i) , UART_TX_IDLE_NUM_V, UART_TX_IDLE_NUM_S)
- #define UART_SET_TX_IDLE_NUM(i,val) SET_PERI_REG_BITS(UART_IDLE_CONF_REG(i) ,UART_TX_IDLE_NUM_V,(val),UART_TX_IDLE_NUM_S)
- #define UART_GET_RX_IDLE_THRHD(i) GET_PERI_REG_BITS2(UART_IDLE_CONF_REG(i) , UART_RX_IDLE_THRHD_V, UART_RX_IDLE_THRHD_S)
- #define UART_SET_RX_IDLE_THRHD(i,val) SET_PERI_REG_BITS(UART_IDLE_CONF_REG(i) ,UART_RX_IDLE_THRHD_V,(val),UART_RX_IDLE_THRHD_S)
-
-
-
-#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44)
- /* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
- /*description: config this reg to delay tx signal*/
- #define UART_RS485_TX_DLY_NUM 0x0000000F
- #define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
- #define UART_RS485_TX_DLY_NUM_V 0xF
- #define UART_RS485_TX_DLY_NUM_S 6
- /* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
- /*description: config this reg to delay rx signal*/
- #define UART_RS485_RX_DLY_NUM (BIT(5))
- #define UART_RS485_RX_DLY_NUM_M (BIT(5))
- #define UART_RS485_RX_DLY_NUM_V 0x1
- #define UART_RS485_RX_DLY_NUM_S 5
- /* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
- /*description: set this bit to enable tx when rx is busy*/
- #define UART_RS485RXBY_TX_EN (BIT(4))
- #define UART_RS485RXBY_TX_EN_M (BIT(4))
- #define UART_RS485RXBY_TX_EN_V 0x1
- #define UART_RS485RXBY_TX_EN_S 4
- /* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
- /*description: set this bit to enable rx receiving when tx is sending*/
- #define UART_RS485TX_RX_EN (BIT(3))
- #define UART_RS485TX_RX_EN_M (BIT(3))
- #define UART_RS485TX_RX_EN_V 0x1
- #define UART_RS485TX_RX_EN_S 3
- /* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
- /*description: set this bit to add 1 bit stop bit(after data)*/
- #define UART_DL1_EN (BIT(2))
- #define UART_DL1_EN_M (BIT(2))
- #define UART_DL1_EN_V 0x1
- #define UART_DL1_EN_S 2
- /* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
- /*description: set this bit to add 1 bit stop bit(before data)*/
- #define UART_DL0_EN (BIT(1))
- #define UART_DL0_EN_M (BIT(1))
- #define UART_DL0_EN_V 0x1
- #define UART_DL0_EN_S 1
- /* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
- /*description: set this bit to enable rs485 protocol*/
- #define UART_RS485_EN (BIT(0))
- #define UART_RS485_EN_M (BIT(0))
- #define UART_RS485_EN_V 0x1
- #define UART_RS485_EN_S 0
- #define UART_GET_RS485_TX_DLY_NUM(i) GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485_TX_DLY_NUM_V, UART_RS485_TX_DLY_NUM_S)
- #define UART_SET_RS485_TX_DLY_NUM(i,val) SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485_TX_DLY_NUM_V,(val),UART_RS485_TX_DLY_NUM_S)
- #define UART_GET_RS485_RX_DLY_NUM(i) GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485_RX_DLY_NUM_V, UART_RS485_RX_DLY_NUM_S)
- #define UART_SET_RS485_RX_DLY_NUM(i,val) SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485_RX_DLY_NUM_V,(val),UART_RS485_RX_DLY_NUM_S)
- #define UART_GET_RS485RXBY_TX_EN(i) GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485RXBY_TX_EN_V, UART_RS485RXBY_TX_EN_S)
- #define UART_SET_RS485RXBY_TX_EN(i,val) SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485RXBY_TX_EN_V,(val),UART_RS485RXBY_TX_EN_S)
- #define UART_GET_RS485TX_RX_EN(i) GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485TX_RX_EN_V, UART_RS485TX_RX_EN_S)
- #define UART_SET_RS485TX_RX_EN(i,val) SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485TX_RX_EN_V,(val),UART_RS485TX_RX_EN_S)
- #define UART_GET_DL1_EN(i) GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_DL1_EN_V, UART_DL1_EN_S)
- #define UART_SET_DL1_EN(i,val) SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_DL1_EN_V,(val),UART_DL1_EN_S)
- #define UART_GET_DL0_EN(i) GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_DL0_EN_V, UART_DL0_EN_S)
- #define UART_SET_DL0_EN(i,val) SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_DL0_EN_V,(val),UART_DL0_EN_S)
- #define UART_GET_RS485_EN(i) GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485_EN_V, UART_RS485_EN_S)
- #define UART_SET_RS485_EN(i,val) SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485_EN_V,(val),UART_RS485_EN_S)
-
-
-
-#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48)
- /* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
- /*description: config the idle time before receiving AT_CMD*/
- #define UART_PRE_IDLE_NUM 0x00FFFFFF
- #define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
- #define UART_PRE_IDLE_NUM_V 0xFFFFFF
- #define UART_PRE_IDLE_NUM_S 0
- #define UART_GET_PRE_IDLE_NUM(i) GET_PERI_REG_BITS2(UART_AT_CMD_PRECNT_REG(i) , UART_PRE_IDLE_NUM_V, UART_PRE_IDLE_NUM_S)
- #define UART_SET_PRE_IDLE_NUM(i,val) SET_PERI_REG_BITS(UART_AT_CMD_PRECNT_REG(i) ,UART_PRE_IDLE_NUM_V,(val),UART_PRE_IDLE_NUM_S)
-
-
-
-#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c)
- /* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
- /*description: config the idle time after receiving AT_CMD*/
- #define UART_POST_IDLE_NUM 0x00FFFFFF
- #define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
- #define UART_POST_IDLE_NUM_V 0xFFFFFF
- #define UART_POST_IDLE_NUM_S 0
- #define UART_GET_POST_IDLE_NUM(i) GET_PERI_REG_BITS2(UART_AT_CMD_POSTCNT_REG(i) , UART_POST_IDLE_NUM_V, UART_POST_IDLE_NUM_S)
- #define UART_SET_POST_IDLE_NUM(i,val) SET_PERI_REG_BITS(UART_AT_CMD_POSTCNT_REG(i) ,UART_POST_IDLE_NUM_V,(val),UART_POST_IDLE_NUM_S)
-
-
-
-#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50)
- /* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */
- /*description: config the time between receiving two AT_CMD*/
- #define UART_RX_GAP_TOUT 0x00FFFFFF
- #define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
- #define UART_RX_GAP_TOUT_V 0xFFFFFF
- #define UART_RX_GAP_TOUT_S 0
- #define UART_GET_RX_GAP_TOUT(i) GET_PERI_REG_BITS2(UART_AT_CMD_GAPTOUT_REG(i) , UART_RX_GAP_TOUT_V, UART_RX_GAP_TOUT_S)
- #define UART_SET_RX_GAP_TOUT(i,val) SET_PERI_REG_BITS(UART_AT_CMD_GAPTOUT_REG(i) ,UART_RX_GAP_TOUT_V,(val),UART_RX_GAP_TOUT_S)
-
-
-
-#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54)
- /* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'd3 ; */
- /*description: config the continous num of AT_CMD*/
- #define UART_CHAR_NUM 0x000000FF
- #define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
- #define UART_CHAR_NUM_V 0xFF
- #define UART_CHAR_NUM_S 8
- /* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
- /*description: config AT_CMD*/
- #define UART_AT_CMD_CHAR 0x000000FF
- #define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
- #define UART_AT_CMD_CHAR_V 0xFF
- #define UART_AT_CMD_CHAR_S 0
- #define UART_GET_CHAR_NUM(i) GET_PERI_REG_BITS2(UART_AT_CMD_CHAR_REG(i) , UART_CHAR_NUM_V, UART_CHAR_NUM_S)
- #define UART_SET_CHAR_NUM(i,val) SET_PERI_REG_BITS(UART_AT_CMD_CHAR_REG(i) ,UART_CHAR_NUM_V,(val),UART_CHAR_NUM_S)
- #define UART_GET_AT_CMD_CHAR(i) GET_PERI_REG_BITS2(UART_AT_CMD_CHAR_REG(i) , UART_AT_CMD_CHAR_V, UART_AT_CMD_CHAR_S)
- #define UART_SET_AT_CMD_CHAR(i,val) SET_PERI_REG_BITS(UART_AT_CMD_CHAR_REG(i) ,UART_AT_CMD_CHAR_V,(val),UART_AT_CMD_CHAR_S)
-
-
-
-#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58)
- /* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
- /*description: the most significant bits of tx fifo empty threashold*/
- #define UART_TX_MEM_EMPTY_THRHD 0x00000007
- #define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S))
- #define UART_TX_MEM_EMPTY_THRHD_V 0x7
- #define UART_TX_MEM_EMPTY_THRHD_S 28
- /* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
- /*description: the most significant bits of rx fifo full threashold*/
- #define UART_RX_MEM_FULL_THRHD 0x00000007
- #define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S))
- #define UART_RX_MEM_FULL_THRHD_V 0x7
- #define UART_RX_MEM_FULL_THRHD_S 25
- /* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */
- /*description: the most significant bits of uart xoff flow threashold*/
- #define UART_XOFF_THRESHOLD_H2 0x00000003
- #define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S))
- #define UART_XOFF_THRESHOLD_H2_V 0x3
- #define UART_XOFF_THRESHOLD_H2_S 23
- /* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
- /*description: the most significant bits of uart xon flow threshold*/
- #define UART_XON_THRESHOLD_H2 0x00000003
- #define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S))
- #define UART_XON_THRESHOLD_H2_V 0x3
- #define UART_XON_THRESHOLD_H2_S 21
- /* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3h0 ; */
- /*description: the most significant bits of rx timeout threshold*/
- #define UART_RX_TOUT_THRHD_H3 0x00000007
- #define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S))
- #define UART_RX_TOUT_THRHD_H3_V 0x7
- #define UART_RX_TOUT_THRHD_H3_S 18
- /* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
- /*description: the most significant bits of rx flow control threshold*/
- #define UART_RX_FLOW_THRHD_H3 0x00000007
- #define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S))
- #define UART_RX_FLOW_THRHD_H3_V 0x7
- #define UART_RX_FLOW_THRHD_H3_S 15
- /* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 3'h0 ; */
- /*description: config tx_mem's size(128*reg_rx_size)*/
- #define UART_TX_SIZE 0x0000000F
- #define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
- #define UART_TX_SIZE_V 0xF
- #define UART_TX_SIZE_S 7
- /* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 3'h0 ; */
- /*description: config rx mem's size(128*reg_rx_size)*/
- #define UART_RX_SIZE 0x0000000F
- #define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
- #define UART_RX_SIZE_V 0xF
- #define UART_RX_SIZE_S 3
- /* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
- /*description: set this bit to pull_down mem's pd signal*/
- #define UART_MEM_PD (BIT(0))
- #define UART_MEM_PD_M (BIT(0))
- #define UART_MEM_PD_V 0x1
- #define UART_MEM_PD_S 0
- #define UART_GET_TX_MEM_EMPTY_THRHD(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_TX_MEM_EMPTY_THRHD_V, UART_TX_MEM_EMPTY_THRHD_S)
- #define UART_SET_TX_MEM_EMPTY_THRHD(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_TX_MEM_EMPTY_THRHD_V,(val),UART_TX_MEM_EMPTY_THRHD_S)
- #define UART_GET_RX_MEM_FULL_THRHD(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_RX_MEM_FULL_THRHD_V, UART_RX_MEM_FULL_THRHD_S)
- #define UART_SET_RX_MEM_FULL_THRHD(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_RX_MEM_FULL_THRHD_V,(val),UART_RX_MEM_FULL_THRHD_S)
- #define UART_GET_XOFF_THRESHOLD_H2(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_XOFF_THRESHOLD_H2_V, UART_XOFF_THRESHOLD_H2_S)
- #define UART_SET_XOFF_THRESHOLD_H2(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_XOFF_THRESHOLD_H2_V,(val),UART_XOFF_THRESHOLD_H2_S)
- #define UART_GET_XON_THRESHOLD_H2(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_XON_THRESHOLD_H2_V, UART_XON_THRESHOLD_H2_S)
- #define UART_SET_XON_THRESHOLD_H2(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_XON_THRESHOLD_H2_V,(val),UART_XON_THRESHOLD_H2_S)
- #define UART_GET_RX_TOUT_THRHD_H3(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_RX_TOUT_THRHD_H3_V, UART_RX_TOUT_THRHD_H3_S)
- #define UART_SET_RX_TOUT_THRHD_H3(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_RX_TOUT_THRHD_H3_V,(val),UART_RX_TOUT_THRHD_H3_S)
- #define UART_GET_RX_FLOW_THRHD_H3(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_RX_FLOW_THRHD_H3_V, UART_RX_FLOW_THRHD_H3_S)
- #define UART_SET_RX_FLOW_THRHD_H3(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_RX_FLOW_THRHD_H3_V,(val),UART_RX_FLOW_THRHD_H3_S)
- #define UART_GET_REG_TX_SIZE(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_TX_SIZE_V, UART_TX_SIZE_S)
- #define UART_SET_REG_TX_SIZE(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_TX_SIZE_V,(val),UART_TX_SIZE_S)
- #define UART_GET_REG_RX_SIZE(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_RX_SIZE_V, UART_RX_SIZE_S)
- #define UART_SET_REG_RX_SIZE(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_RX_SIZE_V,(val),UART_RX_SIZE_S)
- #define UART_GET_REG_MEM_PD(i) GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_MEM_PD_V, UART_MEM_PD_S)
- #define UART_SET_REG_MEM_PD(i,val) SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_MEM_PD_V,(val),UART_MEM_PD_S)
-
-
-
-#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c)
- /* UART_TX_RADDR_CHX : RO ;bitpos:[23:13] ;default: 11'b0 ; */
- /*description: uartx tx mem's read address*/
- #define UART_TX_RADDR_CHX 0x000007FF
- #define UART_TX_RADDR_CHX_M ((UART_TX_RADDR_CHX_V)<<(UART_TX_RADDR_CHX_S))
- #define UART_TX_RADDR_CHX_V 0x7FF
- #define UART_TX_RADDR_CHX_S 13
- /* UART_APB_TX_WADDR_CHX : RO ;bitpos:[12:2] ;default: 11'b0 ; */
- /*description: uartx tx mem's write address*/
- #define UART_APB_TX_WADDR_CHX 0x000007FF
- #define UART_APB_TX_WADDR_CHX_M ((UART_APB_TX_WADDR_CHX_V)<<(UART_APB_TX_WADDR_CHX_S))
- #define UART_APB_TX_WADDR_CHX_V 0x7FF
- #define UART_APB_TX_WADDR_CHX_S 2
- #define UART_GET_TX_RADDR_CHX(i) GET_PERI_REG_BITS2(UART_MEM_TX_STATUS_REG(i) , UART_TX_RADDR_CHX_V, UART_TX_RADDR_CHX_S)
- #define UART_GET_APB_TX_WADDR_CHX(i) GET_PERI_REG_BITS2(UART_MEM_TX_STATUS_REG(i) , UART_APB_TX_WADDR_CHX_V, UART_APB_TX_WADDR_CHX_S)
-
-
-
-#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60)
- /* UART_RX_WADDR_CHX : RO ;bitpos:[23:13] ;default: 11'b0 ; */
- /*description: uartx rx mem's write address*/
- #define UART_RX_WADDR_CHX 0x000007FF
- #define UART_RX_WADDR_CHX_M ((UART_RX_WADDR_CHX_V)<<(UART_RX_WADDR_CHX_S))
- #define UART_RX_WADDR_CHX_V 0x7FF
- #define UART_RX_WADDR_CHX_S 13
- /* UART_APB_RX_RADDR_CHX : RO ;bitpos:[12:2] ;default: 11'b0 ; */
- /*description: uartx rx mem's read address*/
- #define UART_APB_RX_RADDR_CHX 0x000007FF
- #define UART_APB_RX_RADDR_CHX_M ((UART_APB_RX_RADDR_CHX_V)<<(UART_APB_RX_RADDR_CHX_S))
- #define UART_APB_RX_RADDR_CHX_V 0x7FF
- #define UART_APB_RX_RADDR_CHX_S 2
- #define UART_GET_RX_WADDR_CHX(i) GET_PERI_REG_BITS2(UART_MEM_RX_STATUS_REG(i) , UART_RX_WADDR_CHX_V, UART_RX_WADDR_CHX_S)
- #define UART_GET_APB_RX_RADDR_CHX(i) GET_PERI_REG_BITS2(UART_MEM_RX_STATUS_REG(i) , UART_APB_RX_RADDR_CHX_V, UART_APB_RX_RADDR_CHX_S)
-
-
-
-#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78)
- /* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */
- /*description: */
- #define UART_DATE 0xFFFFFFFF
- #define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S))
- #define UART_DATE_V 0xFFFFFFFF
- #define UART_DATE_S 0
- #define UART_GET_DATE(i) GET_PERI_REG_BITS2(UART_DATE_REG(i) , UART_DATE_V, UART_DATE_S)
- #define UART_SET_DATE(i,val) SET_PERI_REG_BITS(UART_DATE_REG(i) ,UART_DATE_V,(val),UART_DATE_S)
-
-
-
-#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C)
- /* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */
- /*description: */
- #define UART_ID 0xFFFFFFFF
- #define UART_ID_M ((UART_ID_V)<<(UART_ID_S))
- #define UART_ID_V 0xFFFFFFFF
- #define UART_ID_S 0
- #define UART_GET_ID(i) GET_PERI_REG_BITS2(UART_ID_REG(i) , UART_ID_V, UART_ID_S)
- #define UART_SET_ID(i,val) SET_PERI_REG_BITS(UART_ID_REG(i) ,UART_ID_V,(val),UART_ID_S)
-
-
-
-
-
-
-#endif /* _SOC_UART_REG_H_ */
-
-
+++ /dev/null
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UHCI0_REG_H_
-#define _SOC_UHCI0_REG_H_
-
-#include "soc.h"
-
-#define UHCI0_CONF0 ( DR_REG_UHCI0_BASE + 0x0)
-#define UHCI0_UART_RX_BRK_EOF_EN (BIT(22))
-#define UHCI0_CLK_EN (BIT(21))
-#define UHCI0_ENCODE_CRC_EN (BIT(20))
-#define UHCI0_LEN_EOF_EN (BIT(19))
-#define UHCI0_UART_IDLE_EOF_EN (BIT(18))
-#define UHCI0_CRC_REC_EN (BIT(17))
-#define UHCI0_HEAD_EN (BIT(16))
-#define UHCI0_SEPER_EN (BIT(15))
-#define UHCI0_MEM_TRANS_EN (BIT(14))
-#define UHCI0_RX_DATA_BURST_EN (BIT(13))
-#define UHCI0_TXDSCR_BURST_EN (BIT(12))
-#define UHCI0_RXDSCR_BURST_EN (BIT(11))
-#define UHCI0_UART1_CE (BIT(10))
-#define UHCI0_UART0_CE (BIT(9))
-#define UHCI0_TO_EOF_MODE (BIT(8))
-#define UHCI0_RX_NO_RESTART_CLR (BIT(7))
-#define UHCI0_RX_AUTO_WRBACK (BIT(6))
-#define UHCI0_RX_LOOP_TEST (BIT(5))
-#define UHCI0_TX_LOOP_TEST (BIT(4))
-#define UHCI0_AHBM_RST (BIT(3))
-#define UHCI0_AHBM_FIFO_RST (BIT(2))
-#define UHCI0_RX_RST (BIT(1))
-#define UHCI0_TX_RST (BIT(0))
-
-#define UHCI0_INT_RAW ( DR_REG_UHCI0_BASE + 0x4)
-#define UHCI0_UHCI_SEND_A_Q_INT_RAW (BIT(15))
-#define UHCI0_UHCI_SEND_S_Q_INT_RAW (BIT(14))
-#define UHCI0_UHCI_TO_TOTAL_EOF_INT_RAW (BIT(13))
-#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_RAW (BIT(12))
-#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_RAW (BIT(11))
-#define UHCI0_UHCI_RX_DSCR_ERR_INT_RAW (BIT(10))
-#define UHCI0_UHCI_TX_DSCR_ERR_INT_RAW (BIT(9))
-#define UHCI0_UHCI_TO_EOF_INT_RAW (BIT(8))
-#define UHCI0_UHCI_RX_DONE_INT_RAW (BIT(7))
-#define UHCI0_UHCI_FROM_ERR_EOF_INT_RAW (BIT(6))
-#define UHCI0_UHCI_FROM_SUC_EOF_INT_RAW (BIT(5))
-#define UHCI0_UHCI_TX_DONE_INT_RAW (BIT(4))
-#define UHCI0_UHCI_TX_HUNG_INT_RAW (BIT(3))
-#define UHCI0_UHCI_RX_HUNG_INT_RAW (BIT(2))
-#define UHCI0_UHCI_TX_START_INT_RAW (BIT(1))
-#define UHCI0_UHCI_RX_START_INT_RAW (BIT(0))
-
-#define UHCI0_INT_ST ( DR_REG_UHCI0_BASE + 0x8)
-#define UHCI0_UHCI_SEND_A_Q_INT_ST (BIT(15))
-#define UHCI0_UHCI_SEND_S_Q_INT_ST (BIT(14))
-#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ST (BIT(13))
-#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ST (BIT(12))
-#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ST (BIT(11))
-#define UHCI0_UHCI_RX_DSCR_ERR_INT_ST (BIT(10))
-#define UHCI0_UHCI_TX_DSCR_ERR_INT_ST (BIT(9))
-#define UHCI0_UHCI_TO_EOF_INT_ST (BIT(8))
-#define UHCI0_UHCI_RX_DONE_INT_ST (BIT(7))
-#define UHCI0_UHCI_FROM_ERR_EOF_INT_ST (BIT(6))
-#define UHCI0_UHCI_FROM_SUC_EOF_INT_ST (BIT(5))
-#define UHCI0_UHCI_TX_DONE_INT_ST (BIT(4))
-#define UHCI0_UHCI_TX_HUNG_INT_ST (BIT(3))
-#define UHCI0_UHCI_RX_HUNG_INT_ST (BIT(2))
-#define UHCI0_UHCI_TX_START_INT_ST (BIT(1))
-#define UHCI0_UHCI_RX_START_INT_ST (BIT(0))
-
-#define UHCI0_INT_ENA ( DR_REG_UHCI0_BASE + 0xC)
-#define UHCI0_UHCI_SEND_A_Q_INT_ENA (BIT(15))
-#define UHCI0_UHCI_SEND_S_Q_INT_ENA (BIT(14))
-#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ENA (BIT(13))
-#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ENA (BIT(12))
-#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ENA (BIT(11))
-#define UHCI0_UHCI_RX_DSCR_ERR_INT_ENA (BIT(10))
-#define UHCI0_UHCI_TX_DSCR_ERR_INT_ENA (BIT(9))
-#define UHCI0_UHCI_TO_EOF_INT_ENA (BIT(8))
-#define UHCI0_UHCI_RX_DONE_INT_ENA (BIT(7))
-#define UHCI0_UHCI_FROM_ERR_EOF_INT_ENA (BIT(6))
-#define UHCI0_UHCI_FROM_SUC_EOF_INT_ENA (BIT(5))
-#define UHCI0_UHCI_TX_DONE_INT_ENA (BIT(4))
-#define UHCI0_UHCI_TX_HUNG_INT_ENA (BIT(3))
-#define UHCI0_UHCI_RX_HUNG_INT_ENA (BIT(2))
-#define UHCI0_UHCI_TX_START_INT_ENA (BIT(1))
-#define UHCI0_UHCI_RX_START_INT_ENA (BIT(0))
-
-#define UHCI0_INT_CLR ( DR_REG_UHCI0_BASE + 0x10)
-#define UHCI0_SEND_A_REG_Q_INT_CLR (BIT(15))
-#define UHCI0_SEND_S_REG_Q_INT_CLR (BIT(14))
-#define UHCI0_TO_TOTAL_EOF_INT_CLR (BIT(13))
-#define UHCI0_RXLINK_EOF_ERR_INT_CLR (BIT(12))
-#define UHCI0_TX_DSCR_EMPTY_INT_CLR (BIT(11))
-#define UHCI0_RX_DSCR_ERR_INT_CLR (BIT(10))
-#define UHCI0_TX_DSCR_ERR_INT_CLR (BIT(9))
-#define UHCI0_TO_EOF_INT_CLR (BIT(8))
-#define UHCI0_RX_DONE_INT_CLR (BIT(7))
-#define UHCI0_FROM_ERR_EOF_INT_CLR (BIT(6))
-#define UHCI0_FROM_SUC_EOF_INT_CLR (BIT(5))
-#define UHCI0_TX_DONE_INT_CLR (BIT(4))
-#define UHCI0_TX_HUNG_INT_CLR (BIT(3))
-#define UHCI0_RX_HUNG_INT_CLR (BIT(2))
-#define UHCI0_TX_START_INT_CLR (BIT(1))
-#define UHCI0_RX_START_INT_CLR (BIT(0))
-
-#define UHCI0_RX_STATUS ( DR_REG_UHCI0_BASE + 0x14)
-#define UHCI0_RX_EMPTY (BIT(1))
-#define UHCI0_RX_FULL (BIT(0))
-
-#define UHCI0_RXFIFO_PUSH ( DR_REG_UHCI0_BASE + 0x18)
-#define UHCI0_RXFIFO_PUSH_EN (BIT(16))
-#define UHCI0_RXFIFO_WDATA 0x000001FF
-#define UHCI0_RXFIFO_WDATA_S 0
-
-#define UHCI0_TX_STATUS ( DR_REG_UHCI0_BASE + 0x1C)
-#define UHCI0_UHCI_RX_ERR_CAUSE 0x00000007
-#define UHCI0_UHCI_RX_ERR_CAUSE_S 4
-#define UHCI0_TX_EMPTY (BIT(1))
-#define UHCI0_TX_FULL (BIT(0))
-
-#define UHCI0_TX_POP ( DR_REG_UHCI0_BASE + 0x20)
-#define UHCI0_TXFIFO_POP (BIT(16))
-#define UHCI0_TXFIFO_RDATA 0x00000FFF
-#define UHCI0_TXFIFO_RDATA_S 0
-
-#define UHCI0_RX_LINK ( DR_REG_UHCI0_BASE + 0x24)
-#define UHCI0_UHCI_RXLINK_PARK (BIT(31))
-#define UHCI0_RXLINK_RESTART (BIT(30))
-#define UHCI0_RXLINK_START (BIT(29))
-#define UHCI0_RXLINK_STOP (BIT(28))
-#define UHCI0_RXLINK_ADDR 0x000FFFFF
-#define UHCI0_RXLINK_ADDR_S 0
-
-#define UHCI0_TX_LINK ( DR_REG_UHCI0_BASE + 0x28)
-#define UHCI0_UHCI_TXLINK_PARK (BIT(31))
-#define UHCI0_TXLINK_RESTART (BIT(30))
-#define UHCI0_TXLINK_START (BIT(29))
-#define UHCI0_TXLINK_STOP (BIT(28))
-#define UHCI0_TXLINK_AUTO_RET (BIT(20))
-#define UHCI0_TXLINK_ADDR 0x000FFFFF
-#define UHCI0_TXLINK_ADDR_S 0
-
-#define UHCI0_CONF1 ( DR_REG_UHCI0_BASE + 0x2C)
-#define UHCI0_SW_START (BIT(8))
-#define UHCI0_WAIT_SW_START (BIT(7))
-#define UHCI0_CHECK_OWNER (BIT(6))
-#define UHCI0_TX_ACK_NUM_RE (BIT(5))
-#define UHCI0_TX_CHECK_SUM_RE (BIT(4))
-#define UHCI0_SAVE_HEAD (BIT(3))
-#define UHCI0_CRC_DISABLE (BIT(2))
-#define UHCI0_CHECK_SEQ_EN (BIT(1))
-#define UHCI0_CHECK_SUM_EN (BIT(0))
-
-#define UHCI0_STATE0 ( DR_REG_UHCI0_BASE + 0x30)
-#define UHCI0_UHCI_STATE0 0xFFFFFFFF
-#define UHCI0_UHCI_STATE0_S 0
-
-#define UHCI0_STATE1 ( DR_REG_UHCI0_BASE + 0x34)
-#define UHCI0_UHCI_STATE1 0xFFFFFFFF
-#define UHCI0_UHCI_STATE1_S 0
-
-#define UHCI0_RX_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x38)
-#define UHCI0_TO_EOF_DES_ADDR 0xFFFFFFFF
-#define UHCI0_TO_EOF_DES_ADDR_S 0
-
-#define UHCI0_TX_SUC_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x3C)
-#define UHCI0_FROM_SUC_EOF_DES_ADDR 0xFFFFFFFF
-#define UHCI0_FROM_SUC_EOF_DES_ADDR_S 0
-
-#define UHCI0_TX_ERR_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x40)
-#define UHCI0_FROM_ERR_EOF_DES_ADDR 0xFFFFFFFF
-#define UHCI0_FROM_ERR_EOF_DES_ADDR_S 0
-
-#define UHCI0_RX_EOF_BFR_DES_ADDR ( DR_REG_UHCI0_BASE + 0x44)
-#define UHCI0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF
-#define UHCI0_TO_EOF_BFR_DES_ADDR_S 0
-
-#define UHCI0_AHB_TEST ( DR_REG_UHCI0_BASE + 0x48)
-#define UHCI0_AHB_TESTADDR 0x00000003
-#define UHCI0_AHB_TESTADDR_S 4
-#define UHCI0_AHB_TESTMODE 0x00000007
-#define UHCI0_AHB_TESTMODE_S 0
-
-#define UHCI0_TX_DSCR ( DR_REG_UHCI0_BASE + 0x4C)
-#define UHCI0_TXLINK_DSCR 0xFFFFFFFF
-#define UHCI0_TXLINK_DSCR_S 0
-
-#define UHCI0_TX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x50)
-#define UHCI0_TXLINK_DSCR_BF0 0xFFFFFFFF
-#define UHCI0_TXLINK_DSCR_BF0_S 0
-
-#define UHCI0_TX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x54)
-#define UHCI0_TXLINK_DSCR_BF1 0xFFFFFFFF
-#define UHCI0_TXLINK_DSCR_BF1_S 0
-
-#define UHCI0_RX_DSCR ( DR_REG_UHCI0_BASE + 0x58)
-#define UHCI0_RXLINK_DSCR 0xFFFFFFFF
-#define UHCI0_RXLINK_DSCR_S 0
-
-#define UHCI0_RX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x5C)
-#define UHCI0_RXLINK_DSCR_BF0 0xFFFFFFFF
-#define UHCI0_RXLINK_DSCR_BF0_S 0
-
-#define UHCI0_RX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x60)
-#define UHCI0_RXLINK_DSCR_BF1 0xFFFFFFFF
-#define UHCI0_RXLINK_DSCR_BF1_S 0
-
-#define UHCI0_ESCAPE_CONF ( DR_REG_UHCI0_BASE + 0x64)
-#define UHCI0_RX_13_ESC_EN (BIT(7))
-#define UHCI0_RX_11_ESC_EN (BIT(6))
-#define UHCI0_RX_DB_ESC_EN (BIT(5))
-#define UHCI0_RX_C0_ESC_EN (BIT(4))
-#define UHCI0_TX_13_ESC_EN (BIT(3))
-#define UHCI0_TX_11_ESC_EN (BIT(2))
-#define UHCI0_TX_DB_ESC_EN (BIT(1))
-#define UHCI0_TX_C0_ESC_EN (BIT(0))
-
-#define UHCI0_HUNG_CONF ( DR_REG_UHCI0_BASE + 0x68)
-#define UHCI0_RXFIFO_TIMEOUT_ENA (BIT(23))
-#define UHCI0_RXFIFO_TIMEOUT_SHIFT 0x00000007
-#define UHCI0_RXFIFO_TIMEOUT_SHIFT_S 20
-#define UHCI0_RXFIFO_TIMEOUT 0x000000FF
-#define UHCI0_RXFIFO_TIMEOUT_S 12
-#define UHCI0_TXFIFO_TIMEOUT_ENA (BIT(11))
-#define UHCI0_TXFIFO_TIMEOUT_SHIFT 0x00000007
-#define UHCI0_TXFIFO_TIMEOUT_SHIFT_S 8
-#define UHCI0_TXFIFO_TIMEOUT 0x000000FF
-#define UHCI0_TXFIFO_TIMEOUT_S 0
-
-#define UHCI0_ACK_NUM ( DR_REG_UHCI0_BASE + 0x6C)
-
-#define UHCI0_RX_HEAD ( DR_REG_UHCI0_BASE + 0x70)
-#define UHCI0_UHCI_RX_HEAD 0xFFFFFFFF
-#define UHCI0_UHCI_RX_HEAD_S 0
-
-#define UHCI0_QUICK_SENT ( DR_REG_UHCI0_BASE + 0x74)
-#define UHCI0_ALWAYS_SEND_EN (BIT(7))
-#define UHCI0_ALWAYS_SEND_NUM 0x00000007
-#define UHCI0_ALWAYS_SEND_NUM_S 4
-#define UHCI0_SINGLE_SEND_EN (BIT(3))
-#define UHCI0_SINGLE_SEND_NUM 0x00000007
-#define UHCI0_SINGLE_SEND_NUM_S 0
-
-#define UHCI0_REG_Q0_WORD0 ( DR_REG_UHCI0_BASE + 0x78)
-#define UHCI0_SEND_Q0_WORD0 0xFFFFFFFF
-#define UHCI0_SEND_Q0_WORD0_S 0
-
-#define UHCI0_REG_Q0_WORD1 ( DR_REG_UHCI0_BASE + 0x7C)
-#define UHCI0_SEND_Q0_WORD1 0xFFFFFFFF
-#define UHCI0_SEND_Q0_WORD1_S 0
-
-#define UHCI0_REG_Q1_WORD0 ( DR_REG_UHCI0_BASE + 0x80)
-#define UHCI0_SEND_Q1_WORD0 0xFFFFFFFF
-#define UHCI0_SEND_Q1_WORD0_S 0
-
-#define UHCI0_REG_Q1_WORD1 ( DR_REG_UHCI0_BASE + 0x84)
-#define UHCI0_SEND_Q1_WORD1 0xFFFFFFFF
-#define UHCI0_SEND_Q1_WORD1_S 0
-
-#define UHCI0_REG_Q2_WORD0 ( DR_REG_UHCI0_BASE + 0x88)
-#define UHCI0_SEND_Q2_WORD0 0xFFFFFFFF
-#define UHCI0_SEND_Q2_WORD0_S 0
-
-#define UHCI0_REG_Q2_WORD1 ( DR_REG_UHCI0_BASE + 0x8C)
-#define UHCI0_SEND_Q2_WORD1 0xFFFFFFFF
-#define UHCI0_SEND_Q2_WORD1_S 0
-
-#define UHCI0_REG_Q3_WORD0 ( DR_REG_UHCI0_BASE + 0x90)
-#define UHCI0_SEND_Q3_WORD0 0xFFFFFFFF
-#define UHCI0_SEND_Q3_WORD0_S 0
-
-#define UHCI0_REG_Q3_WORD1 ( DR_REG_UHCI0_BASE + 0x94)
-#define UHCI0_SEND_Q3_WORD1 0xFFFFFFFF
-#define UHCI0_SEND_Q3_WORD1_S 0
-
-#define UHCI0_REG_Q4_WORD0 ( DR_REG_UHCI0_BASE + 0x98)
-#define UHCI0_SEND_Q4_WORD0 0xFFFFFFFF
-#define UHCI0_SEND_Q4_WORD0_S 0
-
-#define UHCI0_REG_Q4_WORD1 ( DR_REG_UHCI0_BASE + 0x9C)
-#define UHCI0_SEND_Q4_WORD1 0xFFFFFFFF
-#define UHCI0_SEND_Q4_WORD1_S 0
-
-#define UHCI0_REG_Q5_WORD0 ( DR_REG_UHCI0_BASE + 0xA0)
-#define UHCI0_SEND_Q5_WORD0 0xFFFFFFFF
-#define UHCI0_SEND_Q5_WORD0_S 0
-
-#define UHCI0_REG_Q5_WORD1 ( DR_REG_UHCI0_BASE + 0xA4)
-#define UHCI0_SEND_Q5_WORD1 0xFFFFFFFF
-#define UHCI0_SEND_Q5_WORD1_S 0
-
-#define UHCI0_REG_Q6_WORD0 ( DR_REG_UHCI0_BASE + 0xA8)
-#define UHCI0_SEND_Q6_WORD0 0xFFFFFFFF
-#define UHCI0_SEND_Q6_WORD0_S 0
-
-#define UHCI0_REG_Q6_WORD1 ( DR_REG_UHCI0_BASE + 0xAC)
-#define UHCI0_SEND_Q6_WORD1 0xFFFFFFFF
-#define UHCI0_SEND_Q6_WORD1_S 0
-
-#define UHCI0_ESC_CONF0 ( DR_REG_UHCI0_BASE + 0xB0)
-#define UHCI0_SEPER_ESC_CHAR1 0x000000FF
-#define UHCI0_SEPER_ESC_CHAR1_S 16
-#define UHCI0_SEPER_ESC_CHAR0 0x000000FF
-#define UHCI0_SEPER_ESC_CHAR0_S 8
-#define UHCI0_SEPER_CHAR 0x000000FF
-#define UHCI0_SEPER_CHAR_S 0
-
-#define UHCI0_ESC_CONF1 ( DR_REG_UHCI0_BASE + 0xB4)
-#define UHCI0_ESC_SEQ0_CHAR1 0x000000FF
-#define UHCI0_ESC_SEQ0_CHAR1_S 16
-#define UHCI0_ESC_SEQ0_CHAR0 0x000000FF
-#define UHCI0_ESC_SEQ0_CHAR0_S 8
-#define UHCI0_ESC_SEQ0 0x000000FF
-#define UHCI0_ESC_SEQ0_S 0
-
-#define UHCI0_ESC_CONF2 ( DR_REG_UHCI0_BASE + 0xB8)
-#define UHCI0_ESC_SEQ1_CHAR1 0x000000FF
-#define UHCI0_ESC_SEQ1_CHAR1_S 16
-#define UHCI0_ESC_SEQ1_CHAR0 0x000000FF
-#define UHCI0_ESC_SEQ1_CHAR0_S 8
-#define UHCI0_ESC_SEQ1 0x000000FF
-#define UHCI0_ESC_SEQ1_S 0
-
-#define UHCI0_ESC_CONF3 ( DR_REG_UHCI0_BASE + 0xBC)
-#define UHCI0_ESC_SEQ2_CHAR1 0x000000FF
-#define UHCI0_ESC_SEQ2_CHAR1_S 16
-#define UHCI0_ESC_SEQ2_CHAR0 0x000000FF
-#define UHCI0_ESC_SEQ2_CHAR0_S 8
-#define UHCI0_ESC_SEQ2 0x000000FF
-#define UHCI0_ESC_SEQ2_S 0
-
-#define UHCI0_PKT_THRES ( DR_REG_UHCI0_BASE + 0xC0)
-#define UHCI0_PKT_THRS 0x00001FFF
-#define UHCI0_PKT_THRS_S 0
-
-#define UHCI0_DATA ( DR_REG_UHCI0_BASE + 0xFC)
-#define UHCI0_UHCI_DATA 0xFFFFFFFF
-#define UHCI0_UHCI_DATA_S 0
-
-#endif /* _SOC_UHCI0_REG_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UHCI_REG_H_
+#define _SOC_UHCI_REG_H_
+
+
+#include "soc.h"
+#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
+#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0)
+/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to enable to use brk char as the end of a data frame.*/
+#define UHCI_UART_RX_BRK_EOF_EN (BIT(23))
+#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(23))
+#define UHCI_UART_RX_BRK_EOF_EN_V 0x1
+#define UHCI_UART_RX_BRK_EOF_EN_S 23
+/* UHCI_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to enable clock-gating for read or write registers.*/
+#define UHCI_CLK_EN (BIT(22))
+#define UHCI_CLK_EN_M (BIT(22))
+#define UHCI_CLK_EN_V 0x1
+#define UHCI_CLK_EN_S 22
+/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Set this bit to enable crc calculation for data frame when bit6
+ in the head packet is 1.*/
+#define UHCI_ENCODE_CRC_EN (BIT(21))
+#define UHCI_ENCODE_CRC_EN_M (BIT(21))
+#define UHCI_ENCODE_CRC_EN_V 0x1
+#define UHCI_ENCODE_CRC_EN_S 21
+/* UHCI_LEN_EOF_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: Set this bit to enable to use packet_len in packet head when
+ the received data is equal to packet_len this means the end of a data frame.*/
+#define UHCI_LEN_EOF_EN (BIT(20))
+#define UHCI_LEN_EOF_EN_M (BIT(20))
+#define UHCI_LEN_EOF_EN_V 0x1
+#define UHCI_LEN_EOF_EN_S 20
+/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to enable to use idle time when the idle time after
+ data frame is satisfied this means the end of a data frame.*/
+#define UHCI_UART_IDLE_EOF_EN (BIT(19))
+#define UHCI_UART_IDLE_EOF_EN_M (BIT(19))
+#define UHCI_UART_IDLE_EOF_EN_V 0x1
+#define UHCI_UART_IDLE_EOF_EN_S 19
+/* UHCI_CRC_REC_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: Set this bit to enable receiver''s ability of crc calculation
+ when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/
+#define UHCI_CRC_REC_EN (BIT(18))
+#define UHCI_CRC_REC_EN_M (BIT(18))
+#define UHCI_CRC_REC_EN_V 0x1
+#define UHCI_CRC_REC_EN_S 18
+/* UHCI_HEAD_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: Set this bit to enable to use head packet before the data frame.*/
+#define UHCI_HEAD_EN (BIT(17))
+#define UHCI_HEAD_EN_M (BIT(17))
+#define UHCI_HEAD_EN_V 0x1
+#define UHCI_HEAD_EN_S 17
+/* UHCI_SEPER_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: Set this bit to use special char to separate the data frame.*/
+#define UHCI_SEPER_EN (BIT(16))
+#define UHCI_SEPER_EN_M (BIT(16))
+#define UHCI_SEPER_EN_V 0x1
+#define UHCI_SEPER_EN_S 16
+/* UHCI_MEM_TRANS_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_MEM_TRANS_EN (BIT(15))
+#define UHCI_MEM_TRANS_EN_M (BIT(15))
+#define UHCI_MEM_TRANS_EN_V 0x1
+#define UHCI_MEM_TRANS_EN_S 15
+/* UHCI_OUT_DATA_BURST_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable DMA burst MODE*/
+#define UHCI_OUT_DATA_BURST_EN (BIT(14))
+#define UHCI_OUT_DATA_BURST_EN_M (BIT(14))
+#define UHCI_OUT_DATA_BURST_EN_V 0x1
+#define UHCI_OUT_DATA_BURST_EN_S 14
+/* UHCI_INDSCR_BURST_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to enable DMA out links to use burst mode.*/
+#define UHCI_INDSCR_BURST_EN (BIT(13))
+#define UHCI_INDSCR_BURST_EN_M (BIT(13))
+#define UHCI_INDSCR_BURST_EN_V 0x1
+#define UHCI_INDSCR_BURST_EN_S 13
+/* UHCI_OUTDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable DMA in links to use burst mode.*/
+#define UHCI_OUTDSCR_BURST_EN (BIT(12))
+#define UHCI_OUTDSCR_BURST_EN_M (BIT(12))
+#define UHCI_OUTDSCR_BURST_EN_V 0x1
+#define UHCI_OUTDSCR_BURST_EN_S 12
+/* UHCI_UART2_CE : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to use UART2 to transmit or receive data.*/
+#define UHCI_UART2_CE (BIT(11))
+#define UHCI_UART2_CE_M (BIT(11))
+#define UHCI_UART2_CE_V 0x1
+#define UHCI_UART2_CE_S 11
+/* UHCI_UART1_CE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to use UART1 to transmit or receive data.*/
+#define UHCI_UART1_CE (BIT(10))
+#define UHCI_UART1_CE_M (BIT(10))
+#define UHCI_UART1_CE_V 0x1
+#define UHCI_UART1_CE_S 10
+/* UHCI_UART0_CE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to use UART to transmit or receive data.*/
+#define UHCI_UART0_CE (BIT(9))
+#define UHCI_UART0_CE_M (BIT(9))
+#define UHCI_UART0_CE_V 0x1
+#define UHCI_UART0_CE_S 9
+/* UHCI_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: Set this bit to produce eof after DMA pops all data clear this
+ bit to produce eof after DMA pushes all data*/
+#define UHCI_OUT_EOF_MODE (BIT(8))
+#define UHCI_OUT_EOF_MODE_M (BIT(8))
+#define UHCI_OUT_EOF_MODE_V 0x1
+#define UHCI_OUT_EOF_MODE_S 8
+/* UHCI_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: don't use*/
+#define UHCI_OUT_NO_RESTART_CLR (BIT(7))
+#define UHCI_OUT_NO_RESTART_CLR_M (BIT(7))
+#define UHCI_OUT_NO_RESTART_CLR_V 0x1
+#define UHCI_OUT_NO_RESTART_CLR_S 7
+/* UHCI_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: when in link's length is 0 go on to use the next in link automatically.*/
+#define UHCI_OUT_AUTO_WRBACK (BIT(6))
+#define UHCI_OUT_AUTO_WRBACK_M (BIT(6))
+#define UHCI_OUT_AUTO_WRBACK_V 0x1
+#define UHCI_OUT_AUTO_WRBACK_S 6
+/* UHCI_OUT_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable loop test for out links.*/
+#define UHCI_OUT_LOOP_TEST (BIT(5))
+#define UHCI_OUT_LOOP_TEST_M (BIT(5))
+#define UHCI_OUT_LOOP_TEST_V 0x1
+#define UHCI_OUT_LOOP_TEST_S 5
+/* UHCI_IN_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable loop test for in links.*/
+#define UHCI_IN_LOOP_TEST (BIT(4))
+#define UHCI_IN_LOOP_TEST_M (BIT(4))
+#define UHCI_IN_LOOP_TEST_V 0x1
+#define UHCI_IN_LOOP_TEST_S 4
+/* UHCI_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset dma ahb interface.*/
+#define UHCI_AHBM_RST (BIT(3))
+#define UHCI_AHBM_RST_M (BIT(3))
+#define UHCI_AHBM_RST_V 0x1
+#define UHCI_AHBM_RST_S 3
+/* UHCI_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to reset dma ahb fifo.*/
+#define UHCI_AHBM_FIFO_RST (BIT(2))
+#define UHCI_AHBM_FIFO_RST_M (BIT(2))
+#define UHCI_AHBM_FIFO_RST_V 0x1
+#define UHCI_AHBM_FIFO_RST_S 2
+/* UHCI_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset out link operations.*/
+#define UHCI_OUT_RST (BIT(1))
+#define UHCI_OUT_RST_M (BIT(1))
+#define UHCI_OUT_RST_V 0x1
+#define UHCI_OUT_RST_S 1
+/* UHCI_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to reset in link operations.*/
+#define UHCI_IN_RST (BIT(0))
+#define UHCI_IN_RST_M (BIT(0))
+#define UHCI_IN_RST_V 0x1
+#define UHCI_IN_RST_S 0
+
+#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4)
+/* UHCI_DMA_INFIFO_FULL_WM_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_M (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_V 0x1
+#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_S 16
+/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: When use always_send registers to send a series of short packets
+ it will produce this interrupt when dma has send the short packet.*/
+#define UHCI_SEND_A_Q_INT_RAW (BIT(15))
+#define UHCI_SEND_A_Q_INT_RAW_M (BIT(15))
+#define UHCI_SEND_A_Q_INT_RAW_V 0x1
+#define UHCI_SEND_A_Q_INT_RAW_S 15
+/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: When use single send registers to send a short packets it will
+ produce this interrupt when dma has send the short packet.*/
+#define UHCI_SEND_S_Q_INT_RAW (BIT(14))
+#define UHCI_SEND_S_Q_INT_RAW_M (BIT(14))
+#define UHCI_SEND_S_Q_INT_RAW_V 0x1
+#define UHCI_SEND_S_Q_INT_RAW_S 14
+/* UHCI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: When all data have been send it will produce uhci_out_total_eof_int interrupt.*/
+#define UHCI_OUT_TOTAL_EOF_INT_RAW (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_RAW_M (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_RAW_V 0x1
+#define UHCI_OUT_TOTAL_EOF_INT_RAW_S 13
+/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: when there are some errors about eof in outlink descriptor it
+ will produce uhci_outlink_eof_err_int interrupt.*/
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 12
+/* UHCI_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: when there are not enough in links for DMA it will produce uhci_in_dscr_err_int
+ interrupt.*/
+#define UHCI_IN_DSCR_EMPTY_INT_RAW (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_RAW_M (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_RAW_V 0x1
+#define UHCI_IN_DSCR_EMPTY_INT_RAW_S 11
+/* UHCI_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: when there are some errors about the in link descriptor it will
+ produce uhci_out_dscr_err_int interrupt.*/
+#define UHCI_OUT_DSCR_ERR_INT_RAW (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_RAW_M (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_RAW_V 0x1
+#define UHCI_OUT_DSCR_ERR_INT_RAW_S 10
+/* UHCI_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: when there are some errors about the out link descriptor it
+ will produce uhci_in_dscr_err_int interrupt.*/
+#define UHCI_IN_DSCR_ERR_INT_RAW (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_RAW_M (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_RAW_V 0x1
+#define UHCI_IN_DSCR_ERR_INT_RAW_S 9
+/* UHCI_OUT_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int
+ interrupt.*/
+#define UHCI_OUT_EOF_INT_RAW (BIT(8))
+#define UHCI_OUT_EOF_INT_RAW_M (BIT(8))
+#define UHCI_OUT_EOF_INT_RAW_V 0x1
+#define UHCI_OUT_EOF_INT_RAW_S 8
+/* UHCI_OUT_DONE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: when a out link descriptor is completed it will produce uhci_out_done_int
+ interrupt.*/
+#define UHCI_OUT_DONE_INT_RAW (BIT(7))
+#define UHCI_OUT_DONE_INT_RAW_M (BIT(7))
+#define UHCI_OUT_DONE_INT_RAW_V 0x1
+#define UHCI_OUT_DONE_INT_RAW_S 7
+/* UHCI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: when there are some errors about eof in in link descriptor it
+ will produce uhci_in_err_eof_int interrupt.*/
+#define UHCI_IN_ERR_EOF_INT_RAW (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_RAW_M (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_RAW_V 0x1
+#define UHCI_IN_ERR_EOF_INT_RAW_S 6
+/* UHCI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: when a data packet has been received it will produce uhci_in_suc_eof_int
+ interrupt.*/
+#define UHCI_IN_SUC_EOF_INT_RAW (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_RAW_M (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_RAW_V 0x1
+#define UHCI_IN_SUC_EOF_INT_RAW_S 5
+/* UHCI_IN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: when a in link descriptor has been completed it will produce
+ uhci_in_done_int interrupt.*/
+#define UHCI_IN_DONE_INT_RAW (BIT(4))
+#define UHCI_IN_DONE_INT_RAW_M (BIT(4))
+#define UHCI_IN_DONE_INT_RAW_V 0x1
+#define UHCI_IN_DONE_INT_RAW_S 4
+/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: when DMA takes a lot of time to read a data from RAM it will
+ produce uhci_tx_hung_int interrupt.*/
+#define UHCI_TX_HUNG_INT_RAW (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_M (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_V 0x1
+#define UHCI_TX_HUNG_INT_RAW_S 3
+/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: when DMA takes a lot of time to receive a data it will produce
+ uhci_rx_hung_int interrupt.*/
+#define UHCI_RX_HUNG_INT_RAW (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_M (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_V 0x1
+#define UHCI_RX_HUNG_INT_RAW_S 2
+/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
+#define UHCI_TX_START_INT_RAW (BIT(1))
+#define UHCI_TX_START_INT_RAW_M (BIT(1))
+#define UHCI_TX_START_INT_RAW_V 0x1
+#define UHCI_TX_START_INT_RAW_S 1
+/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: when a separator char has been send it will produce uhci_rx_start_int
+ interrupt.*/
+#define UHCI_RX_START_INT_RAW (BIT(0))
+#define UHCI_RX_START_INT_RAW_M (BIT(0))
+#define UHCI_RX_START_INT_RAW_V 0x1
+#define UHCI_RX_START_INT_RAW_S 0
+
+#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8)
+/* UHCI_DMA_INFIFO_FULL_WM_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ST (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_M (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_V 0x1
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_S 16
+/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_A_Q_INT_ST (BIT(15))
+#define UHCI_SEND_A_Q_INT_ST_M (BIT(15))
+#define UHCI_SEND_A_Q_INT_ST_V 0x1
+#define UHCI_SEND_A_Q_INT_ST_S 15
+/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_S_Q_INT_ST (BIT(14))
+#define UHCI_SEND_S_Q_INT_ST_M (BIT(14))
+#define UHCI_SEND_S_Q_INT_ST_V 0x1
+#define UHCI_SEND_S_Q_INT_ST_S 14
+/* UHCI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_TOTAL_EOF_INT_ST (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_ST_M (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_ST_V 0x1
+#define UHCI_OUT_TOTAL_EOF_INT_ST_S 13
+/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 12
+/* UHCI_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_EMPTY_INT_ST (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_ST_M (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_ST_V 0x1
+#define UHCI_IN_DSCR_EMPTY_INT_ST_S 11
+/* UHCI_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DSCR_ERR_INT_ST (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_ST_M (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_ST_V 0x1
+#define UHCI_OUT_DSCR_ERR_INT_ST_S 10
+/* UHCI_IN_DSCR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_ERR_INT_ST (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_ST_M (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_ST_V 0x1
+#define UHCI_IN_DSCR_ERR_INT_ST_S 9
+/* UHCI_OUT_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_EOF_INT_ST (BIT(8))
+#define UHCI_OUT_EOF_INT_ST_M (BIT(8))
+#define UHCI_OUT_EOF_INT_ST_V 0x1
+#define UHCI_OUT_EOF_INT_ST_S 8
+/* UHCI_OUT_DONE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DONE_INT_ST (BIT(7))
+#define UHCI_OUT_DONE_INT_ST_M (BIT(7))
+#define UHCI_OUT_DONE_INT_ST_V 0x1
+#define UHCI_OUT_DONE_INT_ST_S 7
+/* UHCI_IN_ERR_EOF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_ERR_EOF_INT_ST (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_ST_M (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_ST_V 0x1
+#define UHCI_IN_ERR_EOF_INT_ST_S 6
+/* UHCI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_SUC_EOF_INT_ST (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_ST_M (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_ST_V 0x1
+#define UHCI_IN_SUC_EOF_INT_ST_S 5
+/* UHCI_IN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DONE_INT_ST (BIT(4))
+#define UHCI_IN_DONE_INT_ST_M (BIT(4))
+#define UHCI_IN_DONE_INT_ST_V 0x1
+#define UHCI_IN_DONE_INT_ST_S 4
+/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_HUNG_INT_ST (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_M (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_V 0x1
+#define UHCI_TX_HUNG_INT_ST_S 3
+/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_HUNG_INT_ST (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_M (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_V 0x1
+#define UHCI_RX_HUNG_INT_ST_S 2
+/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_START_INT_ST (BIT(1))
+#define UHCI_TX_START_INT_ST_M (BIT(1))
+#define UHCI_TX_START_INT_ST_V 0x1
+#define UHCI_TX_START_INT_ST_S 1
+/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_START_INT_ST (BIT(0))
+#define UHCI_RX_START_INT_ST_M (BIT(0))
+#define UHCI_RX_START_INT_ST_V 0x1
+#define UHCI_RX_START_INT_ST_S 0
+
+#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC)
+/* UHCI_DMA_INFIFO_FULL_WM_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_M (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_V 0x1
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_S 16
+/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_A_Q_INT_ENA (BIT(15))
+#define UHCI_SEND_A_Q_INT_ENA_M (BIT(15))
+#define UHCI_SEND_A_Q_INT_ENA_V 0x1
+#define UHCI_SEND_A_Q_INT_ENA_S 15
+/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_S_Q_INT_ENA (BIT(14))
+#define UHCI_SEND_S_Q_INT_ENA_M (BIT(14))
+#define UHCI_SEND_S_Q_INT_ENA_V 0x1
+#define UHCI_SEND_S_Q_INT_ENA_S 14
+/* UHCI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_TOTAL_EOF_INT_ENA (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_ENA_M (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_ENA_V 0x1
+#define UHCI_OUT_TOTAL_EOF_INT_ENA_S 13
+/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 12
+/* UHCI_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_EMPTY_INT_ENA (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_ENA_M (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_ENA_V 0x1
+#define UHCI_IN_DSCR_EMPTY_INT_ENA_S 11
+/* UHCI_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DSCR_ERR_INT_ENA (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_ENA_M (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_ENA_V 0x1
+#define UHCI_OUT_DSCR_ERR_INT_ENA_S 10
+/* UHCI_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_ERR_INT_ENA (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_ENA_M (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_ENA_V 0x1
+#define UHCI_IN_DSCR_ERR_INT_ENA_S 9
+/* UHCI_OUT_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_EOF_INT_ENA (BIT(8))
+#define UHCI_OUT_EOF_INT_ENA_M (BIT(8))
+#define UHCI_OUT_EOF_INT_ENA_V 0x1
+#define UHCI_OUT_EOF_INT_ENA_S 8
+/* UHCI_OUT_DONE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DONE_INT_ENA (BIT(7))
+#define UHCI_OUT_DONE_INT_ENA_M (BIT(7))
+#define UHCI_OUT_DONE_INT_ENA_V 0x1
+#define UHCI_OUT_DONE_INT_ENA_S 7
+/* UHCI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_ERR_EOF_INT_ENA (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_ENA_M (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_ENA_V 0x1
+#define UHCI_IN_ERR_EOF_INT_ENA_S 6
+/* UHCI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_SUC_EOF_INT_ENA (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_ENA_M (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_ENA_V 0x1
+#define UHCI_IN_SUC_EOF_INT_ENA_S 5
+/* UHCI_IN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DONE_INT_ENA (BIT(4))
+#define UHCI_IN_DONE_INT_ENA_M (BIT(4))
+#define UHCI_IN_DONE_INT_ENA_V 0x1
+#define UHCI_IN_DONE_INT_ENA_S 4
+/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_HUNG_INT_ENA (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_M (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_V 0x1
+#define UHCI_TX_HUNG_INT_ENA_S 3
+/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_HUNG_INT_ENA (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_M (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_V 0x1
+#define UHCI_RX_HUNG_INT_ENA_S 2
+/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_START_INT_ENA (BIT(1))
+#define UHCI_TX_START_INT_ENA_M (BIT(1))
+#define UHCI_TX_START_INT_ENA_V 0x1
+#define UHCI_TX_START_INT_ENA_S 1
+/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_START_INT_ENA (BIT(0))
+#define UHCI_RX_START_INT_ENA_M (BIT(0))
+#define UHCI_RX_START_INT_ENA_V 0x1
+#define UHCI_RX_START_INT_ENA_S 0
+
+#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10)
+/* UHCI_DMA_INFIFO_FULL_WM_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_M (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_V 0x1
+#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_S 16
+/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_A_Q_INT_CLR (BIT(15))
+#define UHCI_SEND_A_Q_INT_CLR_M (BIT(15))
+#define UHCI_SEND_A_Q_INT_CLR_V 0x1
+#define UHCI_SEND_A_Q_INT_CLR_S 15
+/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_S_Q_INT_CLR (BIT(14))
+#define UHCI_SEND_S_Q_INT_CLR_M (BIT(14))
+#define UHCI_SEND_S_Q_INT_CLR_V 0x1
+#define UHCI_SEND_S_Q_INT_CLR_S 14
+/* UHCI_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_TOTAL_EOF_INT_CLR (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_CLR_M (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_CLR_V 0x1
+#define UHCI_OUT_TOTAL_EOF_INT_CLR_S 13
+/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 12
+/* UHCI_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_EMPTY_INT_CLR (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_CLR_M (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_CLR_V 0x1
+#define UHCI_IN_DSCR_EMPTY_INT_CLR_S 11
+/* UHCI_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DSCR_ERR_INT_CLR (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_CLR_M (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_CLR_V 0x1
+#define UHCI_OUT_DSCR_ERR_INT_CLR_S 10
+/* UHCI_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_ERR_INT_CLR (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_CLR_M (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_CLR_V 0x1
+#define UHCI_IN_DSCR_ERR_INT_CLR_S 9
+/* UHCI_OUT_EOF_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_EOF_INT_CLR (BIT(8))
+#define UHCI_OUT_EOF_INT_CLR_M (BIT(8))
+#define UHCI_OUT_EOF_INT_CLR_V 0x1
+#define UHCI_OUT_EOF_INT_CLR_S 8
+/* UHCI_OUT_DONE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DONE_INT_CLR (BIT(7))
+#define UHCI_OUT_DONE_INT_CLR_M (BIT(7))
+#define UHCI_OUT_DONE_INT_CLR_V 0x1
+#define UHCI_OUT_DONE_INT_CLR_S 7
+/* UHCI_IN_ERR_EOF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_ERR_EOF_INT_CLR (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_CLR_M (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_CLR_V 0x1
+#define UHCI_IN_ERR_EOF_INT_CLR_S 6
+/* UHCI_IN_SUC_EOF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_SUC_EOF_INT_CLR (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_CLR_M (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_CLR_V 0x1
+#define UHCI_IN_SUC_EOF_INT_CLR_S 5
+/* UHCI_IN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DONE_INT_CLR (BIT(4))
+#define UHCI_IN_DONE_INT_CLR_M (BIT(4))
+#define UHCI_IN_DONE_INT_CLR_V 0x1
+#define UHCI_IN_DONE_INT_CLR_S 4
+/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_HUNG_INT_CLR (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_M (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_V 0x1
+#define UHCI_TX_HUNG_INT_CLR_S 3
+/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_HUNG_INT_CLR (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_M (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_V 0x1
+#define UHCI_RX_HUNG_INT_CLR_S 2
+/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_START_INT_CLR (BIT(1))
+#define UHCI_TX_START_INT_CLR_M (BIT(1))
+#define UHCI_TX_START_INT_CLR_V 0x1
+#define UHCI_TX_START_INT_CLR_S 1
+/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_START_INT_CLR (BIT(0))
+#define UHCI_RX_START_INT_CLR_M (BIT(0))
+#define UHCI_RX_START_INT_CLR_V 0x1
+#define UHCI_RX_START_INT_CLR_S 0
+
+#define UHCI_DMA_OUT_STATUS_REG(i) (REG_UHCI_BASE(i) + 0x14)
+/* UHCI_OUT_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: 1:DMA in link descriptor's fifo is empty.*/
+#define UHCI_OUT_EMPTY (BIT(1))
+#define UHCI_OUT_EMPTY_M (BIT(1))
+#define UHCI_OUT_EMPTY_V 0x1
+#define UHCI_OUT_EMPTY_S 1
+/* UHCI_OUT_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1:DMA out link descriptor's fifo is full.*/
+#define UHCI_OUT_FULL (BIT(0))
+#define UHCI_OUT_FULL_M (BIT(0))
+#define UHCI_OUT_FULL_V 0x1
+#define UHCI_OUT_FULL_S 0
+
+#define UHCI_DMA_OUT_PUSH_REG(i) (REG_UHCI_BASE(i) + 0x18)
+/* UHCI_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: Set this bit to push data in out link descriptor's fifo.*/
+#define UHCI_OUTFIFO_PUSH (BIT(16))
+#define UHCI_OUTFIFO_PUSH_M (BIT(16))
+#define UHCI_OUTFIFO_PUSH_V 0x1
+#define UHCI_OUTFIFO_PUSH_S 16
+/* UHCI_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: This is the data need to be pushed into out link descriptor's fifo.*/
+#define UHCI_OUTFIFO_WDATA 0x000001FF
+#define UHCI_OUTFIFO_WDATA_M ((UHCI_OUTFIFO_WDATA_V)<<(UHCI_OUTFIFO_WDATA_S))
+#define UHCI_OUTFIFO_WDATA_V 0x1FF
+#define UHCI_OUTFIFO_WDATA_S 0
+
+#define UHCI_DMA_IN_STATUS_REG(i) (REG_UHCI_BASE(i) + 0x1C)
+/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: This register stores the errors caused in out link descriptor's data packet.*/
+#define UHCI_RX_ERR_CAUSE 0x00000007
+#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
+#define UHCI_RX_ERR_CAUSE_V 0x7
+#define UHCI_RX_ERR_CAUSE_S 4
+/* UHCI_IN_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_IN_EMPTY (BIT(1))
+#define UHCI_IN_EMPTY_M (BIT(1))
+#define UHCI_IN_EMPTY_V 0x1
+#define UHCI_IN_EMPTY_S 1
+/* UHCI_IN_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_FULL (BIT(0))
+#define UHCI_IN_FULL_M (BIT(0))
+#define UHCI_IN_FULL_V 0x1
+#define UHCI_IN_FULL_S 0
+
+#define UHCI_DMA_IN_POP_REG(i) (REG_UHCI_BASE(i) + 0x20)
+/* UHCI_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: Set this bit to pop data in in link descriptor's fifo.*/
+#define UHCI_INFIFO_POP (BIT(16))
+#define UHCI_INFIFO_POP_M (BIT(16))
+#define UHCI_INFIFO_POP_V 0x1
+#define UHCI_INFIFO_POP_S 16
+/* UHCI_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: This register stores the data pop from in link descriptor's fifo.*/
+#define UHCI_INFIFO_RDATA 0x00000FFF
+#define UHCI_INFIFO_RDATA_M ((UHCI_INFIFO_RDATA_V)<<(UHCI_INFIFO_RDATA_S))
+#define UHCI_INFIFO_RDATA_V 0xFFF
+#define UHCI_INFIFO_RDATA_S 0
+
+#define UHCI_DMA_OUT_LINK_REG(i) (REG_UHCI_BASE(i) + 0x24)
+/* UHCI_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: 1£º the out link descriptor's fsm is in idle state. 0:the out
+ link descriptor's fsm is working.*/
+#define UHCI_OUTLINK_PARK (BIT(31))
+#define UHCI_OUTLINK_PARK_M (BIT(31))
+#define UHCI_OUTLINK_PARK_V 0x1
+#define UHCI_OUTLINK_PARK_S 31
+/* UHCI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to mount on new out link descriptors*/
+#define UHCI_OUTLINK_RESTART (BIT(30))
+#define UHCI_OUTLINK_RESTART_M (BIT(30))
+#define UHCI_OUTLINK_RESTART_V 0x1
+#define UHCI_OUTLINK_RESTART_S 30
+/* UHCI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to start dealing with the out link descriptors.*/
+#define UHCI_OUTLINK_START (BIT(29))
+#define UHCI_OUTLINK_START_M (BIT(29))
+#define UHCI_OUTLINK_START_V 0x1
+#define UHCI_OUTLINK_START_S 29
+/* UHCI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to stop dealing with the out link descriptors.*/
+#define UHCI_OUTLINK_STOP (BIT(28))
+#define UHCI_OUTLINK_STOP_M (BIT(28))
+#define UHCI_OUTLINK_STOP_V 0x1
+#define UHCI_OUTLINK_STOP_S 28
+/* UHCI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: This register stores the least 20 bits of the first out link
+ descriptor's address.*/
+#define UHCI_OUTLINK_ADDR 0x000FFFFF
+#define UHCI_OUTLINK_ADDR_M ((UHCI_OUTLINK_ADDR_V)<<(UHCI_OUTLINK_ADDR_S))
+#define UHCI_OUTLINK_ADDR_V 0xFFFFF
+#define UHCI_OUTLINK_ADDR_S 0
+
+#define UHCI_DMA_IN_LINK_REG(i) (REG_UHCI_BASE(i) + 0x28)
+/* UHCI_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: 1:the in link descriptor's fsm is in idle state. 0:the in link
+ descriptor's fsm is working*/
+#define UHCI_INLINK_PARK (BIT(31))
+#define UHCI_INLINK_PARK_M (BIT(31))
+#define UHCI_INLINK_PARK_V 0x1
+#define UHCI_INLINK_PARK_S 31
+/* UHCI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to mount on new in link descriptors*/
+#define UHCI_INLINK_RESTART (BIT(30))
+#define UHCI_INLINK_RESTART_M (BIT(30))
+#define UHCI_INLINK_RESTART_V 0x1
+#define UHCI_INLINK_RESTART_S 30
+/* UHCI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to start dealing with the in link descriptors.*/
+#define UHCI_INLINK_START (BIT(29))
+#define UHCI_INLINK_START_M (BIT(29))
+#define UHCI_INLINK_START_V 0x1
+#define UHCI_INLINK_START_S 29
+/* UHCI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to stop dealing with the in link descriptors.*/
+#define UHCI_INLINK_STOP (BIT(28))
+#define UHCI_INLINK_STOP_M (BIT(28))
+#define UHCI_INLINK_STOP_V 0x1
+#define UHCI_INLINK_STOP_S 28
+/* UHCI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: 1:when a packet is wrong in link descriptor returns to the descriptor
+ which is lately used.*/
+#define UHCI_INLINK_AUTO_RET (BIT(20))
+#define UHCI_INLINK_AUTO_RET_M (BIT(20))
+#define UHCI_INLINK_AUTO_RET_V 0x1
+#define UHCI_INLINK_AUTO_RET_S 20
+/* UHCI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: This register stores the least 20 bits of the first in link descriptor's
+ address.*/
+#define UHCI_INLINK_ADDR 0x000FFFFF
+#define UHCI_INLINK_ADDR_M ((UHCI_INLINK_ADDR_V)<<(UHCI_INLINK_ADDR_S))
+#define UHCI_INLINK_ADDR_V 0xFFFFF
+#define UHCI_INLINK_ADDR_S 0
+
+#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x2C)
+/* UHCI_DMA_INFIFO_FULL_THRS : R/W ;bitpos:[20:9] ;default: 12'b0 ; */
+/*description: when data amount in link descriptor's fifo is more than this
+ register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/
+#define UHCI_DMA_INFIFO_FULL_THRS 0x00000FFF
+#define UHCI_DMA_INFIFO_FULL_THRS_M ((UHCI_DMA_INFIFO_FULL_THRS_V)<<(UHCI_DMA_INFIFO_FULL_THRS_S))
+#define UHCI_DMA_INFIFO_FULL_THRS_V 0xFFF
+#define UHCI_DMA_INFIFO_FULL_THRS_S 9
+/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to start inserting the packet header.*/
+#define UHCI_SW_START (BIT(8))
+#define UHCI_SW_START_M (BIT(8))
+#define UHCI_SW_START_V 0x1
+#define UHCI_SW_START_S 8
+/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to enable software way to add packet header.*/
+#define UHCI_WAIT_SW_START (BIT(7))
+#define UHCI_WAIT_SW_START_M (BIT(7))
+#define UHCI_WAIT_SW_START_V 0x1
+#define UHCI_WAIT_SW_START_S 7
+/* UHCI_CHECK_OWNER : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to check the owner bit in link descriptor.*/
+#define UHCI_CHECK_OWNER (BIT(6))
+#define UHCI_CHECK_OWNER_M (BIT(6))
+#define UHCI_CHECK_OWNER_V 0x1
+#define UHCI_CHECK_OWNER_S 6
+/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: Set this bit to enable hardware replace ack num in packet header automatically.*/
+#define UHCI_TX_ACK_NUM_RE (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_M (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_V 0x1
+#define UHCI_TX_ACK_NUM_RE_S 5
+/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: Set this bit to enable hardware replace check_sum in packet header
+ automatically.*/
+#define UHCI_TX_CHECK_SUM_RE (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_M (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_V 0x1
+#define UHCI_TX_CHECK_SUM_RE_S 4
+/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to save packet header .*/
+#define UHCI_SAVE_HEAD (BIT(3))
+#define UHCI_SAVE_HEAD_M (BIT(3))
+#define UHCI_SAVE_HEAD_V 0x1
+#define UHCI_SAVE_HEAD_S 3
+/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to disable crc calculation.*/
+#define UHCI_CRC_DISABLE (BIT(2))
+#define UHCI_CRC_DISABLE_M (BIT(2))
+#define UHCI_CRC_DISABLE_V 0x1
+#define UHCI_CRC_DISABLE_S 2
+/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Set this bit to enable decoder to check seq num in packet header.*/
+#define UHCI_CHECK_SEQ_EN (BIT(1))
+#define UHCI_CHECK_SEQ_EN_M (BIT(1))
+#define UHCI_CHECK_SEQ_EN_V 0x1
+#define UHCI_CHECK_SEQ_EN_S 1
+/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Set this bit to enable decoder to check check_sum in packet header.*/
+#define UHCI_CHECK_SUM_EN (BIT(0))
+#define UHCI_CHECK_SUM_EN_M (BIT(0))
+#define UHCI_CHECK_SUM_EN_V 0x1
+#define UHCI_CHECK_SUM_EN_S 0
+
+#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x30)
+/* UHCI_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_STATE0 0xFFFFFFFF
+#define UHCI_STATE0_M ((UHCI_STATE0_V)<<(UHCI_STATE0_S))
+#define UHCI_STATE0_V 0xFFFFFFFF
+#define UHCI_STATE0_S 0
+
+#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x34)
+/* UHCI_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_STATE1 0xFFFFFFFF
+#define UHCI_STATE1_M ((UHCI_STATE1_V)<<(UHCI_STATE1_S))
+#define UHCI_STATE1_V 0xFFFFFFFF
+#define UHCI_STATE1_S 0
+
+#define UHCI_DMA_OUT_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x38)
+/* UHCI_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of out link descriptoir when
+ eof bit in this descriptor is 1.*/
+#define UHCI_OUT_EOF_DES_ADDR 0xFFFFFFFF
+#define UHCI_OUT_EOF_DES_ADDR_M ((UHCI_OUT_EOF_DES_ADDR_V)<<(UHCI_OUT_EOF_DES_ADDR_S))
+#define UHCI_OUT_EOF_DES_ADDR_V 0xFFFFFFFF
+#define UHCI_OUT_EOF_DES_ADDR_S 0
+
+#define UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x3C)
+/* UHCI_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of in link descriptor when eof
+ bit in this descriptor is 1.*/
+#define UHCI_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
+#define UHCI_IN_SUC_EOF_DES_ADDR_M ((UHCI_IN_SUC_EOF_DES_ADDR_V)<<(UHCI_IN_SUC_EOF_DES_ADDR_S))
+#define UHCI_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
+#define UHCI_IN_SUC_EOF_DES_ADDR_S 0
+
+#define UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x40)
+/* UHCI_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of in link descriptor when there
+ are some errors in this descriptor.*/
+#define UHCI_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF
+#define UHCI_IN_ERR_EOF_DES_ADDR_M ((UHCI_IN_ERR_EOF_DES_ADDR_V)<<(UHCI_IN_ERR_EOF_DES_ADDR_S))
+#define UHCI_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF
+#define UHCI_IN_ERR_EOF_DES_ADDR_S 0
+
+#define UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_UHCI_BASE(i) + 0x44)
+/* UHCI_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of out link descriptor when
+ there are some errors in this descriptor.*/
+#define UHCI_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
+#define UHCI_OUT_EOF_BFR_DES_ADDR_M ((UHCI_OUT_EOF_BFR_DES_ADDR_V)<<(UHCI_OUT_EOF_BFR_DES_ADDR_S))
+#define UHCI_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF
+#define UHCI_OUT_EOF_BFR_DES_ADDR_S 0
+
+#define UHCI_AHB_TEST_REG(i) (REG_UHCI_BASE(i) + 0x48)
+/* UHCI_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: The two bits represent ahb bus address bit[20:19]*/
+#define UHCI_AHB_TESTADDR 0x00000003
+#define UHCI_AHB_TESTADDR_M ((UHCI_AHB_TESTADDR_V)<<(UHCI_AHB_TESTADDR_S))
+#define UHCI_AHB_TESTADDR_V 0x3
+#define UHCI_AHB_TESTADDR_S 4
+/* UHCI_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: bit2 is ahb bus test enable £¬bit1 is used to choose wrtie(1)
+ or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
+#define UHCI_AHB_TESTMODE 0x00000007
+#define UHCI_AHB_TESTMODE_M ((UHCI_AHB_TESTMODE_V)<<(UHCI_AHB_TESTMODE_S))
+#define UHCI_AHB_TESTMODE_V 0x7
+#define UHCI_AHB_TESTMODE_S 0
+
+#define UHCI_DMA_IN_DSCR_REG(i) (REG_UHCI_BASE(i) + 0x4C)
+/* UHCI_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in link descriptor's third dword*/
+#define UHCI_INLINK_DSCR 0xFFFFFFFF
+#define UHCI_INLINK_DSCR_M ((UHCI_INLINK_DSCR_V)<<(UHCI_INLINK_DSCR_S))
+#define UHCI_INLINK_DSCR_V 0xFFFFFFFF
+#define UHCI_INLINK_DSCR_S 0
+
+#define UHCI_DMA_IN_DSCR_BF0_REG(i) (REG_UHCI_BASE(i) + 0x50)
+/* UHCI_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in link descriptor's first dword*/
+#define UHCI_INLINK_DSCR_BF0 0xFFFFFFFF
+#define UHCI_INLINK_DSCR_BF0_M ((UHCI_INLINK_DSCR_BF0_V)<<(UHCI_INLINK_DSCR_BF0_S))
+#define UHCI_INLINK_DSCR_BF0_V 0xFFFFFFFF
+#define UHCI_INLINK_DSCR_BF0_S 0
+
+#define UHCI_DMA_IN_DSCR_BF1_REG(i) (REG_UHCI_BASE(i) + 0x54)
+/* UHCI_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in link descriptor's second dword*/
+#define UHCI_INLINK_DSCR_BF1 0xFFFFFFFF
+#define UHCI_INLINK_DSCR_BF1_M ((UHCI_INLINK_DSCR_BF1_V)<<(UHCI_INLINK_DSCR_BF1_S))
+#define UHCI_INLINK_DSCR_BF1_V 0xFFFFFFFF
+#define UHCI_INLINK_DSCR_BF1_S 0
+
+#define UHCI_DMA_OUT_DSCR_REG(i) (REG_UHCI_BASE(i) + 0x58)
+/* UHCI_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out link descriptor's third dword*/
+#define UHCI_OUTLINK_DSCR 0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_M ((UHCI_OUTLINK_DSCR_V)<<(UHCI_OUTLINK_DSCR_S))
+#define UHCI_OUTLINK_DSCR_V 0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_S 0
+
+#define UHCI_DMA_OUT_DSCR_BF0_REG(i) (REG_UHCI_BASE(i) + 0x5C)
+/* UHCI_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out link descriptor's first dword*/
+#define UHCI_OUTLINK_DSCR_BF0 0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_BF0_M ((UHCI_OUTLINK_DSCR_BF0_V)<<(UHCI_OUTLINK_DSCR_BF0_S))
+#define UHCI_OUTLINK_DSCR_BF0_V 0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_BF0_S 0
+
+#define UHCI_DMA_OUT_DSCR_BF1_REG(i) (REG_UHCI_BASE(i) + 0x60)
+/* UHCI_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out link descriptor's second dword*/
+#define UHCI_OUTLINK_DSCR_BF1 0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_BF1_M ((UHCI_OUTLINK_DSCR_BF1_V)<<(UHCI_OUTLINK_DSCR_BF1_S))
+#define UHCI_OUTLINK_DSCR_BF1_V 0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_BF1_S 0
+
+#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x64)
+/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to enable flow control char 0x13 replace when DMA sends data.*/
+#define UHCI_RX_13_ESC_EN (BIT(7))
+#define UHCI_RX_13_ESC_EN_M (BIT(7))
+#define UHCI_RX_13_ESC_EN_V 0x1
+#define UHCI_RX_13_ESC_EN_S 7
+/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to enable flow control char 0x11 replace when DMA sends data.*/
+#define UHCI_RX_11_ESC_EN (BIT(6))
+#define UHCI_RX_11_ESC_EN_M (BIT(6))
+#define UHCI_RX_11_ESC_EN_V 0x1
+#define UHCI_RX_11_ESC_EN_S 6
+/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: Set this bit to enable 0xdb char replace when DMA sends data.*/
+#define UHCI_RX_DB_ESC_EN (BIT(5))
+#define UHCI_RX_DB_ESC_EN_M (BIT(5))
+#define UHCI_RX_DB_ESC_EN_V 0x1
+#define UHCI_RX_DB_ESC_EN_S 5
+/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: Set this bit to enable 0xc0 char replace when DMA sends data.*/
+#define UHCI_RX_C0_ESC_EN (BIT(4))
+#define UHCI_RX_C0_ESC_EN_M (BIT(4))
+#define UHCI_RX_C0_ESC_EN_V 0x1
+#define UHCI_RX_C0_ESC_EN_S 4
+/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable flow control char 0x13 decode when DMA receives data.*/
+#define UHCI_TX_13_ESC_EN (BIT(3))
+#define UHCI_TX_13_ESC_EN_M (BIT(3))
+#define UHCI_TX_13_ESC_EN_V 0x1
+#define UHCI_TX_13_ESC_EN_S 3
+/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable flow control char 0x11 decode when DMA receives data.*/
+#define UHCI_TX_11_ESC_EN (BIT(2))
+#define UHCI_TX_11_ESC_EN_M (BIT(2))
+#define UHCI_TX_11_ESC_EN_V 0x1
+#define UHCI_TX_11_ESC_EN_S 2
+/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Set this bit to enable 0xdb char decode when DMA receives data.*/
+#define UHCI_TX_DB_ESC_EN (BIT(1))
+#define UHCI_TX_DB_ESC_EN_M (BIT(1))
+#define UHCI_TX_DB_ESC_EN_V 0x1
+#define UHCI_TX_DB_ESC_EN_S 1
+/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Set this bit to enable 0xc0 char decode when DMA receives data.*/
+#define UHCI_TX_C0_ESC_EN (BIT(0))
+#define UHCI_TX_C0_ESC_EN_M (BIT(0))
+#define UHCI_TX_C0_ESC_EN_V 0x1
+#define UHCI_TX_C0_ESC_EN_S 0
+
+#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x68)
+/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: This is the enable bit for DMA send data timeout*/
+#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1
+#define UHCI_RXFIFO_TIMEOUT_ENA_S 23
+/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/
+#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20
+/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
+/*description: This register stores the timeout value.when DMA takes more time
+ than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/
+#define UHCI_RXFIFO_TIMEOUT 0x000000FF
+#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
+#define UHCI_RXFIFO_TIMEOUT_V 0xFF
+#define UHCI_RXFIFO_TIMEOUT_S 12
+/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: The enable bit for txfifo receive data timeout*/
+#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1
+#define UHCI_TXFIFO_TIMEOUT_ENA_S 11
+/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/
+#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8
+/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: This register stores the timeout value.when DMA takes more time
+ than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/
+#define UHCI_TXFIFO_TIMEOUT 0x000000FF
+#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
+#define UHCI_TXFIFO_TIMEOUT_V 0xFF
+#define UHCI_TXFIFO_TIMEOUT_S 0
+
+#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x6C)
+
+#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x70)
+/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the packet header received by DMA*/
+#define UHCI_RX_HEAD 0xFFFFFFFF
+#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
+#define UHCI_RX_HEAD_V 0xFFFFFFFF
+#define UHCI_RX_HEAD_S 0
+
+#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x74)
+/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to enable continuously send the same short packet*/
+#define UHCI_ALWAYS_SEND_EN (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_M (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_V 0x1
+#define UHCI_ALWAYS_SEND_EN_S 7
+/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The bits are used to choose which short packet*/
+#define UHCI_ALWAYS_SEND_NUM 0x00000007
+#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
+#define UHCI_ALWAYS_SEND_NUM_V 0x7
+#define UHCI_ALWAYS_SEND_NUM_S 4
+/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable send a short packet*/
+#define UHCI_SINGLE_SEND_EN (BIT(3))
+#define UHCI_SINGLE_SEND_EN_M (BIT(3))
+#define UHCI_SINGLE_SEND_EN_V 0x1
+#define UHCI_SINGLE_SEND_EN_S 3
+/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: The bits are used to choose which short packet*/
+#define UHCI_SINGLE_SEND_NUM 0x00000007
+#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
+#define UHCI_SINGLE_SEND_NUM_V 0x7
+#define UHCI_SINGLE_SEND_NUM_S 0
+
+#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x78)
+/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's first dword*/
+#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
+#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_S 0
+
+#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x7C)
+/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's second dword*/
+#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
+#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_S 0
+
+#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x80)
+/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's first dword*/
+#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
+#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_S 0
+
+#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x84)
+/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's second dword*/
+#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
+#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_S 0
+
+#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x88)
+/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's first dword*/
+#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
+#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_S 0
+
+#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x8C)
+/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's second dword*/
+#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
+#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_S 0
+
+#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x90)
+/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's first dword*/
+#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
+#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_S 0
+
+#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x94)
+/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's second dword*/
+#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
+#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_S 0
+
+#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x98)
+/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's first dword*/
+#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
+#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_S 0
+
+#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x9C)
+/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's second dword*/
+#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
+#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_S 0
+
+#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0xA0)
+/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's first dword*/
+#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
+#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_S 0
+
+#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0xA4)
+/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's second dword*/
+#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
+#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_S 0
+
+#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0xA8)
+/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's first dword*/
+#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
+#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_S 0
+
+#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0xAC)
+/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the content of short packet's second dword*/
+#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
+#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_S 0
+
+#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0xB0)
+/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
+/*description: This register stores the second char used to replace seperator
+ char in data . 0xdc 0xdb replace 0xc0 by default.*/
+#define UHCI_SEPER_ESC_CHAR1 0x000000FF
+#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
+#define UHCI_SEPER_ESC_CHAR1_V 0xFF
+#define UHCI_SEPER_ESC_CHAR1_S 16
+/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: This register stores thee first char used to replace seperator char in data.*/
+#define UHCI_SEPER_ESC_CHAR0 0x000000FF
+#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
+#define UHCI_SEPER_ESC_CHAR0_V 0xFF
+#define UHCI_SEPER_ESC_CHAR0_S 8
+/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
+/*description: This register stores the seperator char seperator char is used
+ to seperate the data frame.*/
+#define UHCI_SEPER_CHAR 0x000000FF
+#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
+#define UHCI_SEPER_CHAR_V 0xFF
+#define UHCI_SEPER_CHAR_S 0
+
+#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0xB4)
+/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
+/*description: This register stores the second char used to replace the reg_esc_seq0 in data*/
+#define UHCI_ESC_SEQ0_CHAR1 0x000000FF
+#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
+#define UHCI_ESC_SEQ0_CHAR1_V 0xFF
+#define UHCI_ESC_SEQ0_CHAR1_S 16
+/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: This register stores the first char used to replace reg_esc_seq0 in data.*/
+#define UHCI_ESC_SEQ0_CHAR0 0x000000FF
+#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
+#define UHCI_ESC_SEQ0_CHAR0_V 0xFF
+#define UHCI_ESC_SEQ0_CHAR0_S 8
+/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
+/*description: This register stores the first substitute char used to replace
+ the seperator char.*/
+#define UHCI_ESC_SEQ0 0x000000FF
+#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
+#define UHCI_ESC_SEQ0_V 0xFF
+#define UHCI_ESC_SEQ0_S 0
+
+#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0xB8)
+/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
+/*description: This register stores the second char used to replace the reg_esc_seq1 in data.*/
+#define UHCI_ESC_SEQ1_CHAR1 0x000000FF
+#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
+#define UHCI_ESC_SEQ1_CHAR1_V 0xFF
+#define UHCI_ESC_SEQ1_CHAR1_S 16
+/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: This register stores the first char used to replace the reg_esc_seq1 in data.*/
+#define UHCI_ESC_SEQ1_CHAR0 0x000000FF
+#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
+#define UHCI_ESC_SEQ1_CHAR0_V 0xFF
+#define UHCI_ESC_SEQ1_CHAR0_S 8
+/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
+/*description: This register stores the flow control char to turn on the flow_control*/
+#define UHCI_ESC_SEQ1 0x000000FF
+#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
+#define UHCI_ESC_SEQ1_V 0xFF
+#define UHCI_ESC_SEQ1_S 0
+
+#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0xBC)
+/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
+/*description: This register stores the second char used to replace the reg_esc_seq2 in data.*/
+#define UHCI_ESC_SEQ2_CHAR1 0x000000FF
+#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
+#define UHCI_ESC_SEQ2_CHAR1_V 0xFF
+#define UHCI_ESC_SEQ2_CHAR1_S 16
+/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: This register stores the first char used to replace the reg_esc_seq2 in data.*/
+#define UHCI_ESC_SEQ2_CHAR0 0x000000FF
+#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
+#define UHCI_ESC_SEQ2_CHAR0_V 0xFF
+#define UHCI_ESC_SEQ2_CHAR0_S 8
+/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
+/*description: This register stores the flow_control char to turn off the flow_control*/
+#define UHCI_ESC_SEQ2 0x000000FF
+#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
+#define UHCI_ESC_SEQ2_V 0xFF
+#define UHCI_ESC_SEQ2_S 0
+
+#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0xC0)
+/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
+/*description: when the amount of packet payload is greater than this value
+ the process of receiving data is done.*/
+#define UHCI_PKT_THRS 0x00001FFF
+#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
+#define UHCI_PKT_THRS_V 0x1FFF
+#define UHCI_PKT_THRS_S 0
+
+#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0xFC)
+/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h16041001 ; */
+/*description: version information*/
+#define UHCI_DATE 0xFFFFFFFF
+#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S))
+#define UHCI_DATE_V 0xFFFFFFFF
+#define UHCI_DATE_S 0
+
+
+
+
+#endif /*_SOC_UHCI_REG_H_ */
+
+
//ToDo: Clean up includes and sync to real rtos
#include "rom/ets_sys.h"
-#include "soc/uart_register.h"
+#include "soc/uart_reg.h"
#include "soc/io_mux_reg.h"
#include "gdbstub.h"
#include "freertos/task.h"
#include "freertos/xtensa_api.h"
-#include "soc/uart_register.h"
+#include "soc/uart_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/dport_reg.h"
#include "soc/rtc_cntl_reg.h"
static void haltOtherCore() {
if (xPortGetCoreID()==0) {
//Kill app cpu
- CLEAR_PERI_REG_MASK(RTC_OPTIONS0, RTC_CNTL_SW_STALL_APPCPU_C1<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
- SET_PERI_REG_MASK(RTC_OPTIONS0, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
- CLEAR_PERI_REG_MASK(RTC_SW_CPU_STALL, RTC_CNTL_SW_STALL_APPCPU_C0<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
- SET_PERI_REG_MASK(RTC_SW_CPU_STALL, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
+ CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C1<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
+ SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
+ CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C0<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
+ SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
} else {
//Kill pro cpu
- CLEAR_PERI_REG_MASK(RTC_OPTIONS0, RTC_CNTL_SW_STALL_PROCPU_C1<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
- SET_PERI_REG_MASK(RTC_OPTIONS0, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
- CLEAR_PERI_REG_MASK(RTC_SW_CPU_STALL, RTC_CNTL_SW_STALL_PROCPU_C0<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
- SET_PERI_REG_MASK(RTC_SW_CPU_STALL, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
+ CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C1<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
+ SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
+ CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C0<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
+ SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
}
}
{
uint32_t ret = 0;
if (cpuid == 0) {
- ret |= GET_PERI_REG_BITS2(PRO_CACHE_CTRL1_REG, cache_mask, 0);
- while (GET_PERI_REG_BITS2(PRO_DCACHE_DBUG_REG0, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
+ ret |= GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0);
+ while (GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
;
}
- SET_PERI_REG_BITS(PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
+ SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
} else {
- ret |= GET_PERI_REG_BITS2(APP_CACHE_CTRL1_REG, cache_mask, 0);
- while (GET_PERI_REG_BITS2(APP_DCACHE_DBUG_REG0, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {
+ ret |= GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0);
+ while (GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {
;
}
- SET_PERI_REG_BITS(APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
+ SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
}
*saved_state = ret;
}
static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
{
if (cpuid == 0) {
- SET_PERI_REG_BITS(PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
- SET_PERI_REG_BITS(PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
+ SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
+ SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
} else {
- SET_PERI_REG_BITS(APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
- SET_PERI_REG_BITS(APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
+ SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
+ SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
}
}
projects / esp-idf / commitdiff