[MIPS GlobalISel] Consider type1 when legalizing shifts after r351882

r351882 allows different type for shift amount then result and value
being shifted. Fix MIPS Legalizer rules to take r351882 into account.

Differential Revision: https://reviews.llvm.org/D66203

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369510 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsLegalizerInfo.cpp b/lib/Target/Mips/MipsLegalizerInfo.cpp
index 456411682caacce4f0977f0f3e64bffa6d7dec50..01dfd4dc19551a2ded3330a07a41e29c6b0fe86b 100644 (file)
--- a/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -84,8 +84,8 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
       .libcallFor({s64});
 
   getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
-    .legalFor({s32, s32})
-    .minScalar(1, s32);
+      .legalFor({{s32, s32}})
+      .clampScalar(1, s32, s32);
 
   getActionDefinitionsBuilder(G_ICMP)
       .legalForCartesianProduct({s32}, {s32, p0})

diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir b/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
index 1e5d50f3d51ae5733d26fb1c8a3e6adc9998158a..e0e230d594f01a42c85e936b2e0a694940af0f41 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
+++ b/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
@@ -20,6 +20,7 @@
   define void @shl(i32) {entry: ret void}
   define void @ashr(i32) {entry: ret void}
   define void @lshr(i32) {entry: ret void}
+  define void @lshr_i64_shift_amount(i32) {entry: ret void}
   define void @shlv(i32, i32) {entry: ret void}
   define void @ashrv(i32, i32) {entry: ret void}
   define void @lshrv(i32, i32) {entry: ret void}
@@ -451,7 +452,7 @@ body:             |
     ; MIPS32: liveins: $a0
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]]
+    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
     ; MIPS32: $v0 = COPY [[SHL]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
@@ -473,7 +474,7 @@ body:             |
     ; MIPS32: liveins: $a0
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]]
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
     ; MIPS32: $v0 = COPY [[ASHR]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
@@ -495,7 +496,7 @@ body:             |
     ; MIPS32: liveins: $a0
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]]
+    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
     ; MIPS32: $v0 = COPY [[LSHR]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
@@ -504,6 +505,30 @@ body:             |
     $v0 = COPY %2(s32)
     RetRA implicit $v0
 
+...
+---
+name:            lshr_i64_shift_amount
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: lshr_i64_shift_amount
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
+    ; MIPS32: $v0 = COPY [[LSHR]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s64) = G_CONSTANT i64 1
+    %2:_(s32) = G_LSHR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
 ...
 ---
 name:            shlv
@@ -517,7 +542,7 @@ body:             |
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]]
+    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
     ; MIPS32: $v0 = COPY [[SHL]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
@@ -539,7 +564,7 @@ body:             |
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]]
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
     ; MIPS32: $v0 = COPY [[ASHR]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
@@ -561,7 +586,7 @@ body:             |
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]]
+    ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
     ; MIPS32: $v0 = COPY [[LSHR]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0