Merging r251622:

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r251622 | vkalintiris | 2015-10-29 10:17:16 +0000 (Thu, 29 Oct 2015) | 17 lines

[mips] Check the register class before replacing materializations of zero with $zero in microMIPS.

Summary:
The microMIPS register class GPRMM16 does not contain the $zero register.
However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses
of the $dst register:

  [d]addiu, $dst, $zero, 0

with the $zero register, without checking for membership in the register
class of the target machine operand.

Reviewers: dsanders

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D13984
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@252158 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index cb46d731da290ab717e4c725d740868448ccc473..2ebfbd17d7d05c94b3383e4b0532016f23453e08 100644 (file)
--- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -115,6 +115,11 @@ bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
       continue;
 
+    // Also, we have to check that the register class of the operand
+    // contains the zero register.
+    if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
+      continue;
+
     MO.setReg(ZeroReg);
   }
 

diff --git a/test/CodeGen/Mips/micromips-zero-mat-uses.ll b/test/CodeGen/Mips/micromips-zero-mat-uses.ll
new file mode 100644 (file)
index 0000000..b38747a
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-zero-mat-uses.ll
@@ -0,0 +1,8 @@
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips,+nooddspreg -O0 < %s | FileCheck %s
+
+; CHECK: addiu    $[[R0:[0-9]+]], $zero, 0
+; CHECK: subu16   $2, $[[R0]], ${{[0-9]+}}
+define i32 @foo() {
+  %1 = sub i32 0, undef
+  ret i32 %1
+}