[MIPS GlobalISel] Lower pointer arguments

Add support for lowering pointer arguments.
Changing type from pointer to integer is already done in
MipsTargetLowering::getRegisterTypeForCallingConv.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D49419

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337912 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsCallLowering.cpp b/lib/Target/Mips/MipsCallLowering.cpp
index cb3c5ef752ddaeadc9d4a3db53ff69d14747c693..e82f62260b3f4eb97623a94237b0cf782b83e529 100644 (file)
--- a/lib/Target/Mips/MipsCallLowering.cpp
+++ b/lib/Target/Mips/MipsCallLowering.cpp
@@ -186,6 +186,8 @@ bool OutgoingValueHandler::handle(ArrayRef<CCValAssign> ArgLocs,
 static bool isSupportedType(Type *T) {
   if (T->isIntegerTy() && T->getScalarSizeInBits() == 32)
     return true;
+  if (T->isPointerTy())
+    return true;
   return false;
 }
 

diff --git a/lib/Target/Mips/MipsLegalizerInfo.cpp b/lib/Target/Mips/MipsLegalizerInfo.cpp
index 3e2fcd6122aa7b96791af6ddf525b27b1b3806f4..da6f9dabdaaff0c0ec54bdfc2629138a9642f0f0 100644 (file)
--- a/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -25,7 +25,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   getActionDefinitionsBuilder(G_ADD).legalFor({s32});
 
   getActionDefinitionsBuilder({G_LOAD, G_STORE})
-      .legalFor({{s32, p0}});
+      .legalForCartesianProduct({p0, s32}, {p0});
 
   getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({s32});

diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
new file mode 100644 (file)
index 0000000..9f469ea
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
@@ -0,0 +1,81 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
+  define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
+  define void @ret_ptr(i8* %p) {entry: ret void}
+
+...
+---
+name:            ptr_arg_in_regs
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptr_arg_in_regs
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LW]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ptr_arg_on_stack
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: ptr_arg_on_stack
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
+    ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 0)
+    ; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LW1]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = COPY $a1
+    %2:gprb(s32) = COPY $a2
+    %3:gprb(s32) = COPY $a3
+    %5:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
+    %4:gprb(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
+    %6:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %6(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ret_ptr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ret_ptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: $v0 = COPY [[COPY]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    $v0 = COPY %0(p0)
+    RetRA implicit $v0
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll b/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
new file mode 100644 (file)
index 0000000..41fe492
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+
+
+define i32 @ptr_arg_in_regs(i32* %p) {
+  ; MIPS32-LABEL: name: ptr_arg_in_regs
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+  ; MIPS32:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p)
+  ; MIPS32:   $v0 = COPY [[LOAD]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %0 = load i32, i32* %p
+  ret i32 %0
+}
+
+define i32 @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {
+  ; MIPS32-LABEL: name: ptr_arg_on_stack
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0, $a1, $a2, $a3
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+  ; MIPS32:   [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+  ; MIPS32:   [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+  ; MIPS32:   [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+  ; MIPS32:   [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
+  ; MIPS32:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p)
+  ; MIPS32:   $v0 = COPY [[LOAD1]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %0 = load i32, i32* %p
+  ret i32 %0
+}
+
+define i8* @ret_ptr(i8* %p) {
+  ; MIPS32-LABEL: name: ret_ptr
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+  ; MIPS32:   $v0 = COPY [[COPY]](p0)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  ret i8* %p
+}

diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir b/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
new file mode 100644 (file)
index 0000000..0dbeb55
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
@@ -0,0 +1,79 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
+  define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
+  define void @ret_ptr(i8* %p) {entry: ret void}
+
+...
+---
+name:            ptr_arg_in_regs
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptr_arg_in_regs
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ptr_arg_on_stack
+alignment:       2
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: ptr_arg_on_stack
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
+    ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LOAD1]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = COPY $a2
+    %3:_(s32) = COPY $a3
+    %5:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %4:_(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
+    %6:_(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %6(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ret_ptr
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ret_ptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: $v0 = COPY [[COPY]](p0)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    $v0 = COPY %0(p0)
+    RetRA implicit $v0
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/pointers.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/pointers.ll
new file mode 100644 (file)
index 0000000..b274167
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/pointers.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define i32 @ptr_arg_in_regs(i32* %p) {
+; MIPS32-LABEL: ptr_arg_in_regs:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lw $2, 0($4)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i32, i32* %p
+  ret i32 %0
+}
+
+define i32 @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {
+; MIPS32-LABEL: ptr_arg_on_stack:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $1, $sp, 16
+; MIPS32-NEXT:    lw $1, 0($1)
+; MIPS32-NEXT:    lw $2, 0($1)
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = load i32, i32* %p
+  ret i32 %0
+}
+
+define i8* @ret_ptr(i8* %p) {
+; MIPS32-LABEL: ret_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    move $2, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  ret i8* %p
+}

diff --git a/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir b/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
new file mode 100644 (file)
index 0000000..7c8dc0a
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
@@ -0,0 +1,82 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
+  define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
+  define void @ret_ptr(i8* %p) {entry: ret void}
+
+...
+---
+name:            ptr_arg_in_regs
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ptr_arg_in_regs
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LOAD]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    %1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %1(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ptr_arg_on_stack
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: ptr_arg_on_stack
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY $a3
+    ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
+    ; MIPS32: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
+    ; MIPS32: [[LOAD1:%[0-9]+]]:gprb(s32) = G_LOAD [[LOAD]](p0) :: (load 4 from %ir.p)
+    ; MIPS32: $v0 = COPY [[LOAD1]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = COPY $a1
+    %2:_(s32) = COPY $a2
+    %3:_(s32) = COPY $a3
+    %5:_(p0) = G_FRAME_INDEX %fixed-stack.0
+    %4:_(p0) = G_LOAD %5(p0) :: (load 4 from %fixed-stack.0, align 0)
+    %6:_(s32) = G_LOAD %4(p0) :: (load 4 from %ir.p)
+    $v0 = COPY %6(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ret_ptr
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: ret_ptr
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: $v0 = COPY [[COPY]](p0)
+    ; MIPS32: RetRA implicit $v0
+    %0:_(p0) = COPY $a0
+    $v0 = COPY %0(p0)
+    RetRA implicit $v0
+
+...