Fix a number of AVX instructions where VEX.vvvv was incorrectly being set

to a register value instead of 1111b as required by the specification.

Reported by: Mark Charney

svn path=/trunk/yasm/; revision=2070

diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index 1f250d10b0d6aed2c3b248f87d18715a36015f51..ef19a408aa790e3720b60c8681708640a06849a8 100755 (executable)
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -4131,7 +4131,7 @@ add_insn("subss",   "xmm_xmm32", modifiers=[0xF3, 0x5C])
 add_insn("ucomiss", "xmm_xmm32", modifiers=[0, 0x2E])
 
 add_insn("vaddss",   "xmm_xmm32", modifiers=[0xF3, 0x58, VEXL0], avx=True)
-add_insn("vcomiss",  "xmm_xmm32", modifiers=[0, 0x2F, VEXL0], avx=True)
+# vcomiss and vucomiss are only two operand
 add_insn("vdivss",   "xmm_xmm32", modifiers=[0xF3, 0x5E, VEXL0], avx=True)
 add_insn("vmaxss",   "xmm_xmm32", modifiers=[0xF3, 0x5F, VEXL0], avx=True)
 add_insn("vminss",   "xmm_xmm32", modifiers=[0xF3, 0x5D, VEXL0], avx=True)
@@ -4140,7 +4140,6 @@ add_insn("vrcpss",   "xmm_xmm32", modifiers=[0xF3, 0x53, VEXL0], avx=True)
 add_insn("vrsqrtss", "xmm_xmm32", modifiers=[0xF3, 0x52, VEXL0], avx=True)
 add_insn("vsqrtss",  "xmm_xmm32", modifiers=[0xF3, 0x51, VEXL0], avx=True)
 add_insn("vsubss",   "xmm_xmm32", modifiers=[0xF3, 0x5C, VEXL0], avx=True)
-add_insn("vucomiss", "xmm_xmm32", modifiers=[0, 0x2E, VEXL0], avx=True)
 
 add_group("ssecmp_128",
     cpu=["SSE"],
@@ -4790,7 +4789,7 @@ add_insn("sqrtsd",   "xmm_xmm64", modifiers=[0xF2, 0x51])
 add_insn("ucomisd",  "xmm_xmm64", modifiers=[0x66, 0x2E])
 
 add_insn("vaddsd",    "xmm_xmm64", modifiers=[0xF2, 0x58, VEXL0], avx=True)
-add_insn("vcomisd",   "xmm_xmm64", modifiers=[0x66, 0x2F, VEXL0], avx=True)
+# vcomisd and vucomisd are only two operand
 # vcvtdq2pd and vcvtps2pd can take ymm, xmm version
 add_insn("vcvtsd2ss", "xmm_xmm64", modifiers=[0xF2, 0x5A, VEXL0], avx=True)
 add_insn("vdivsd",    "xmm_xmm64", modifiers=[0xF2, 0x5E, VEXL0], avx=True)
@@ -4799,7 +4798,6 @@ add_insn("vminsd",    "xmm_xmm64", modifiers=[0xF2, 0x5D, VEXL0], avx=True)
 add_insn("vmulsd",    "xmm_xmm64", modifiers=[0xF2, 0x59, VEXL0], avx=True)
 add_insn("vsubsd",    "xmm_xmm64", modifiers=[0xF2, 0x5C, VEXL0], avx=True)
 add_insn("vsqrtsd",   "xmm_xmm64", modifiers=[0xF2, 0x51, VEXL0], avx=True)
-add_insn("vucomisd",  "xmm_xmm64", modifiers=[0x66, 0x2E, VEXL0], avx=True)
 
 add_insn("addpd",    "xmm_xmm128", modifiers=[0x66, 0x58], cpu=["SSE2"])
 add_insn("andnpd",   "xmm_xmm128", modifiers=[0x66, 0x55], cpu=["SSE2"])
@@ -5277,9 +5275,7 @@ add_insn("vpsignb",    "ssse3", modifiers=[0x08, VEXL0], avx=True)
 add_insn("vpsignw",    "ssse3", modifiers=[0x09, VEXL0], avx=True)
 add_insn("vpsignd",    "ssse3", modifiers=[0x0A, VEXL0], avx=True)
 add_insn("vpmulhrsw",  "ssse3", modifiers=[0x0B, VEXL0], avx=True)
-add_insn("vpabsb",     "ssse3", modifiers=[0x1C, VEXL0], avx=True)
-add_insn("vpabsw",     "ssse3", modifiers=[0x1D, VEXL0], avx=True)
-add_insn("vpabsd",     "ssse3", modifiers=[0x1E, VEXL0], avx=True)
+# vpabsb/vpabsw/vpabsd are 2 operand only
 
 add_group("ssse3imm",
     cpu=["SSSE3"],
@@ -5340,7 +5336,7 @@ add_insn("ptest",      "sse4", modifiers=[0x17])
 add_insn("vpackusdw",   "ssse3", modifiers=[0x2B, VEXL0], avx=True)
 add_insn("vpcmpeqq",    "ssse3", modifiers=[0x29, VEXL0], avx=True)
 add_insn("vpcmpgtq",    "ssse3", modifiers=[0x37, VEXL0], avx=True)
-add_insn("vphminposuw", "ssse3", modifiers=[0x41, VEXL0], avx=True)
+# vphminposuw is 2 operand only
 add_insn("vpmaxsb",     "ssse3", modifiers=[0x3C, VEXL0], avx=True)
 add_insn("vpmaxsd",     "ssse3", modifiers=[0x3D, VEXL0], avx=True)
 add_insn("vpmaxud",     "ssse3", modifiers=[0x3F, VEXL0], avx=True)
@@ -5351,7 +5347,7 @@ add_insn("vpminud",     "ssse3", modifiers=[0x3B, VEXL0], avx=True)
 add_insn("vpminuw",     "ssse3", modifiers=[0x3A, VEXL0], avx=True)
 add_insn("vpmuldq",     "ssse3", modifiers=[0x28, VEXL0], avx=True)
 add_insn("vpmulld",     "ssse3", modifiers=[0x40, VEXL0], avx=True)
-# vptest, however, uses SSE4 style (2 operand only)
+# vptest uses SSE4 style (2 operand only), and takes 256-bit operands
 add_insn("vptest", "sse4", modifiers=[0x17, VEXL0], avx=True)
 
 add_group("sse4imm_256",
@@ -5910,7 +5906,7 @@ add_group("avx_sse4imm",
     vex=128,
     prefix=0x66,
     opcode=[0x0F, 0x3A, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
               Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
 add_group("avx_sse4imm",
@@ -5941,7 +5937,7 @@ add_group("vmovddup",
     vex=128,
     prefix=0x00,
     opcode=[0x0F, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="SIMDReg", size=128, dest="EA")])
 add_group("vmovddup",
     cpu=["AVX"],
@@ -5949,7 +5945,7 @@ add_group("vmovddup",
     vex=128,
     prefix=0x00,
     opcode=[0x0F, 0x00],
-    operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"),
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
               Operand(type="Mem", size=64, relaxed=True, dest="EA")])
 add_group("vmovddup",
     cpu=["AVX"],
@@ -5962,6 +5958,50 @@ add_group("vmovddup",
 
 add_insn("vmovddup",  "vmovddup", modifiers=[0xF2, 0x12])
 
+# Some xmm_xmm64 combinations only take two operands in AVX
+# (VEX.vvvv must be 1111b)
+add_group("avx_xmm_xmm64",
+    cpu=["SSE2"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=128,
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
+add_group("avx_xmm_xmm64",
+    cpu=["SSE2"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=128,
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="Mem", size=64, relaxed=True, dest="EA")])
+
+add_insn("vcomisd",  "avx_xmm_xmm64", modifiers=[0x66, 0x2F], avx=True)
+add_insn("vucomisd", "avx_xmm_xmm64", modifiers=[0x66, 0x2E], avx=True)
+
+# Some xmm_xmm64 combinations only take two operands in AVX
+# (VEX.vvvv must be 1111b)
+add_group("avx_xmm_xmm32",
+    cpu=["SSE"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=128,
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDReg", size=128, dest="EA")])
+add_group("avx_xmm_xmm32",
+    cpu=["SSE"],
+    modifiers=["PreAdd", "Op1Add"],
+    vex=128,
+    prefix=0x00,
+    opcode=[0x0F, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="Mem", size=32, relaxed=True, dest="EA")])
+
+add_insn("vcomiss",  "avx_xmm_xmm32", modifiers=[0, 0x2F], avx=True)
+add_insn("vucomiss", "avx_xmm_xmm32", modifiers=[0, 0x2E], avx=True)
+
 # Some conversion functions take ymm, xmm combination
 add_group("avx_cvt_xmm64",
     cpu=["AVX"],
@@ -5991,6 +6031,22 @@ add_group("avx_cvt_xmm64",
 add_insn("vcvtdq2pd", "avx_cvt_xmm64", modifiers=[0xF3, 0xE6])
 add_insn("vcvtps2pd", "avx_cvt_xmm64", modifiers=[0, 0x5A])
 
+# Some SSE3 opcodes are only two operand in AVX
+# (VEX.vvvv must be 1111b)
+add_group("avx_ssse3_2op",
+    cpu=["AVX"],
+    modifiers=["Op2Add"],
+    vex=128,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x00],
+    operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+              Operand(type="SIMDRM", size=128, relaxed=True, dest="EA")])
+
+add_insn("vpabsb",     "avx_ssse3_2op", modifiers=[0x1C], avx=True)
+add_insn("vpabsw",     "avx_ssse3_2op", modifiers=[0x1D], avx=True)
+add_insn("vpabsd",     "avx_ssse3_2op", modifiers=[0x1E], avx=True)
+add_insn("vphminposuw", "avx_ssse3_2op", modifiers=[0x41], avx=True)
+
 # Some conversion functions take xmm, ymm combination
 # Need separate x and y versions for gas mode
 add_group("avx_cvt_xmm128_x",

diff --git a/modules/arch/x86/tests/avx.hex b/modules/arch/x86/tests/avx.hex
index 39d5c839bc972dd98c050feb6d42eadec675db1f..f0fb5631b4b1faf07ee6481b8afe1e618be7e192 100644 (file)
--- a/modules/arch/x86/tests/avx.hex
+++ b/modules/arch/x86/tests/avx.hex
@@ -1049,15 +1049,15 @@ ca
 2f 
 08 
 c5 
-f1 
+f9 
 2f 
 ca 
 c5 
-f1 
+f9 
 2f 
 08 
 c5 
-f1 
+f9 
 2f 
 08 
 0f 
@@ -1070,15 +1070,15 @@ ca
 2f 
 08 
 c5 
-f0 
+f8 
 2f 
 ca 
 c5 
-f0 
+f8 
 2f 
 08 
 c5 
-f0 
+f8 
 2f 
 08 
 f3 
@@ -3081,15 +3081,15 @@ f2
 12 
 08 
 c5 
-f3 
+fb 
 12 
 ca 
 c5 
-f3 
+fb 
 12 
 08 
 c5 
-f3 
+fb 
 12 
 08 
 c5 
@@ -4120,17 +4120,17 @@ ca
 08 
 c4 
 e2 
-71 
+79 
 1c 
 ca 
 c4 
 e2 
-71 
+79 
 1c 
 08 
 c4 
 e2 
-71 
+79 
 1c 
 08 
 66 
@@ -4150,17 +4150,17 @@ ca
 08 
 c4 
 e2 
-71 
+79 
 1d 
 ca 
 c4 
 e2 
-71 
+79 
 1d 
 08 
 c4 
 e2 
-71 
+79 
 1d 
 08 
 66 
@@ -4180,17 +4180,17 @@ ca
 08 
 c4 
 e2 
-71 
+79 
 1e 
 ca 
 c4 
 e2 
-71 
+79 
 1e 
 08 
 c4 
 e2 
-71 
+79 
 1e 
 08 
 66 
@@ -6024,17 +6024,17 @@ ca
 08 
 c4 
 e2 
-71 
+79 
 41 
 ca 
 c4 
 e2 
-71 
+79 
 41 
 08 
 c4 
 e2 
-71 
+79 
 41 
 08 
 66 
@@ -9465,19 +9465,19 @@ ca
 05 
 c4 
 e3 
-71 
+79 
 09 
 ca 
 05 
 c4 
 e3 
-71 
+79 
 09 
 08 
 05 
 c4 
 e3 
-71 
+79 
 09 
 08 
 05 
@@ -9519,19 +9519,19 @@ ca
 05 
 c4 
 e3 
-71 
+79 
 08 
 ca 
 05 
 c4 
 e3 
-71 
+79 
 08 
 08 
 05 
 c4 
 e3 
-71 
+79 
 08 
 08 
 05 
@@ -10111,15 +10111,15 @@ ca
 2e 
 08 
 c5 
-f1 
+f9 
 2e 
 ca 
 c5 
-f1 
+f9 
 2e 
 08 
 c5 
-f1 
+f9 
 2e 
 08 
 0f 
@@ -10132,15 +10132,15 @@ ca
 2e 
 08 
 c5 
-f0 
+f8 
 2e 
 ca 
 c5 
-f0 
+f8 
 2e 
 08 
 c5 
-f0 
+f8 
 2e 
 08 
 66