[x86] regenerate checks; NFC

This test could be reduced? The check fails for a seemingly unrelated change,
so I'm adding full checks to see what is happening.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297296 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/pr30693.ll b/test/CodeGen/X86/pr30693.ll
index 834365911ed51102c548a43276ec19eb0239d364..ebaf80aeaf9dd2117230ac9272243377b0971d4b 100644 (file)
--- a/test/CodeGen/X86/pr30693.ll
+++ b/test/CodeGen/X86/pr30693.ll
@@ -1,18 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; PR30693
-; RUN: llc < %s | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 
-; CHECK:      .p2align 2
-; CHECK-NEXT: .LCPI0_0:
-; CHECK-NOT:  vmovaps  .LCPI0_0(%rip),
-; CHECK:      .cfi_endproc
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
 
 @var_35 = external local_unnamed_addr global i32, align 4
 @var_14 = external local_unnamed_addr global i16, align 2
 
 ; Function Attrs: uwtable
 define void @_Z3foov() local_unnamed_addr #0 {
+; CHECK-LABEL: _Z3foov:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movslq {{.*}}(%rip), %rax
+; CHECK-NEXT:    movzwl {{.*}}(%rip), %esi
+; CHECK-NEXT:    imull %eax, %esi
+; CHECK-NEXT:    xorl %edi, %edi
+; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vxorps %ymm1, %ymm1, %ymm1
+; CHECK-NEXT:    jmp .LBB0_1
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_7: # %for.cond.cleanup477.loopexit
+; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT:    vpbroadcastd {{.*}}(%rip), %ymm2
+; CHECK-NEXT:    vmovdqu %ymm2, (%rax)
+; CHECK-NEXT:  .LBB0_1: # %vector.ph1520
+; CHECK-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-NEXT:    # Child Loop BB0_3 Depth 2
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    idivl %edi
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    idivq %rdi
+; CHECK-NEXT:    testq %rax, %rax
+; CHECK-NEXT:    jne .LBB0_8
+; CHECK-NEXT:  # BB#2: # %vector.body1512.prol.loopexit
+; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT:    vpbroadcastw %xmm0, %ymm2
+; CHECK-NEXT:    vpbroadcastw %xmm0, %xmm3
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_3: # %for.cond74.loopexit.us
+; CHECK-NEXT:    # Parent Loop BB0_1 Depth=1
+; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-NEXT:    vmovdqu %xmm0, (%rax)
+; CHECK-NEXT:    testb %dil, %dil
+; CHECK-NEXT:    jne .LBB0_3
+; CHECK-NEXT:  # BB#4: # %for.cond337.preheader.lr.ph
+; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT:    vmovups %ymm1, (%rax)
+; CHECK-NEXT:    vmovdqu %ymm2, (%rax)
+; CHECK-NEXT:    vmovdqu %xmm3, (%rax)
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    jg .LBB0_9
+; CHECK-NEXT:  # BB#5: # %for.cond385.preheader
+; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    jle .LBB0_10
+; CHECK-NEXT:  # BB#6: # %for.cond399.preheader.lr.ph.us.1
+; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    jle .LBB0_7
+; CHECK-NEXT:  .LBB0_9: # %for.cond337.preheader.us.preheader
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
+; CHECK-NEXT:  .LBB0_8: # %vector.body1512.prol.preheader
+; CHECK-NEXT:    imull %ecx, %esi
+; CHECK-NEXT:    imull %eax, %esi
+; CHECK-NEXT:    imull %ecx, %esi
+; CHECK-NEXT:    imull %eax, %esi
+; CHECK-NEXT:    addl $36611, %esi # imm = 0x8F03
+; CHECK-NEXT:    vmovd %esi, %xmm0
+; CHECK-NEXT:    vpbroadcastw %xmm0, %ymm0
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
+; CHECK-NEXT:  .LBB0_10: # %for.cond392.preheader.preheader
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
+; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
 entry:
   %0 = load i32, i32* @var_35, align 4
   %1 = load i16, i16* @var_14, align 2