2010-06-29 Geoff Norton <gnorton@novell.com>

	* include/private/gc_locks.h: Implement armv6+ variants of
	GC_test_and_set

svn path=/trunk/mono/; revision=159690

diff --git a/ChangeLog b/ChangeLog
index da66ce5616999c93f25ee4ca33640f81c68a492f..4a0551b0ee232076941a27a49ca4c7e1f007b3cf 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2010-06-29  Geoff Norton  <gnorton@novell.com>
+
+       * include/private/gc_locks.h: Implement armv6+ variants of
+       GC_test_and_set
+
 2010-06-14  Geoff Norton  <gnorton@novell.com>
 
        * dyn_load.c: Fix one other place where l_addr could be null on 

diff --git a/include/private/gc_locks.h b/include/private/gc_locks.h
index 7b8e6e1bda631f6f2fb408a9e8f90bfce204d687..df8736d3d4e0cc5430526798bbcf7b4322a5ed4d 100644 (file)
--- a/include/private/gc_locks.h
+++ b/include/private/gc_locks.h
@@ -224,6 +224,19 @@
 #    endif /* ALPHA */
 #    ifdef ARM32
         inline static int GC_test_and_set(volatile unsigned int *addr) {
+#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__)
+          int ret, tmp;
+          __asm__ __volatile__ (
+                                 "1:\n"
+                                 "ldrex %0, [%3]\n"
+                                 "strex %1, %2, [%3]\n" 
+                                 "teq %1, #0\n"
+                                 "bne 1b\n"
+                                 : "=&r" (ret), "=&r" (tmp)
+                                 : "r" (1), "r" (addr)
+                                 : "memory", "cc");
+          return ret;
+#else
           int oldval;
           /* SWP on ARM is very similar to XCHG on x86.  Doesn't lock the
            * bus because there are no SMP ARM machines.  If/when there are,
@@ -234,6 +247,7 @@
                             : "r"(1), "r"(addr)
                             : "memory");
           return oldval;
+#endif
         }
 #       define GC_TEST_AND_SET_DEFINED
 #    endif /* ARM32 */