bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI,
DominatorTree &DT, bool ForceNestedLoop = false,
bool ForceHardwareLoopPHI = false);
+ bool canAnalyze(LoopInfo &LI);
};
/// This pass provides access to the codegen interfaces that are needed
/// Query the target whether it would be profitable to convert the given loop
/// into a hardware loop.
- bool isHardwareLoopProfitable(Loop *L, LoopInfo &LI,
- ScalarEvolution &SE,
+ bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
AssumptionCache &AC,
TargetLibraryInfo *LibInfo,
HardwareLoopInfo &HWLoopInfo) const;
};
}
+bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
+ // If the loop has irreducible control flow, it can not be converted to
+ // Hardware loop.
+ LoopBlocksRPO RPOT(L);
+ RPOT.perform(&LI);
+ if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
+ return false;
+ return true;
+}
+
bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
LoopInfo &LI, DominatorTree &DT,
bool ForceNestedLoop,
}
bool TargetTransformInfo::isHardwareLoopProfitable(
- Loop *L, LoopInfo &LI, ScalarEvolution &SE, AssumptionCache &AC,
+ Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
- // If the loop has irreducible control flow, it can not be converted to
- // Hardware loop.
- LoopBlocksRPO RPOT(L);
- RPOT.perform(&LI);
- if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
- return false;
return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
}
return true; // Stop search.
HardwareLoopInfo HWLoopInfo(L);
- if (TTI->isHardwareLoopProfitable(L, *LI, *SE, *AC, LibInfo, HWLoopInfo) ||
+ if (!HWLoopInfo.canAnalyze(*LI))
+ return false;
+
+ if (TTI->isHardwareLoopProfitable(L, *SE, *AC, LibInfo, HWLoopInfo) ||
ForceHardwareLoops) {
// Allow overriding of the counter width and loop decrement value.