* x86id.re (retnf_insn, yasm_x86__parse_check_insn): Fix handling of retf

(NASM syntax) in 64-bit mode.  While I'm here, make all ret forms in GAS mode
match GAS output.

Noticed by: Stefan <SMarF@gmx.de>

svn path=/trunk/yasm/; revision=1393

diff --git a/modules/arch/x86/tests/gas64/gas-retenter.asm b/modules/arch/x86/tests/gas64/gas-retenter.asm
index 552598a2d6e10d30afe34cee1f0387f295f6d5a3..d809a5f897b6b21330e346775428a7aa34778dfd 100644 (file)
--- a/modules/arch/x86/tests/gas64/gas-retenter.asm
+++ b/modules/arch/x86/tests/gas64/gas-retenter.asm
@@ -1,3 +1,4 @@
+ret
 retw
 #retl
 retq
@@ -5,7 +6,10 @@ retw $5
 #retl $5
 retq $5
 lretw
-#lretl
+lretl
+lretq
+lretw $5
+lretl $5
 lretq $5
 
 enterw $5000, $5

diff --git a/modules/arch/x86/tests/gas64/gas-retenter.hex b/modules/arch/x86/tests/gas64/gas-retenter.hex
index 7830429286c93327e01ce01a30238bd2c3649043..ab56fdfa92242cd55a40480de9219f3ac3471d16 100644 (file)
--- a/modules/arch/x86/tests/gas64/gas-retenter.hex
+++ b/modules/arch/x86/tests/gas64/gas-retenter.hex
@@ -38,7 +38,7 @@
 00 
 00 
 00 
-d0 
+e0 
 00 
 00 
 00 
@@ -62,6 +62,7 @@ d0
 00 
 01 
 00 
+c3 
 66 
 c3 
 c3 
@@ -74,6 +75,17 @@ c2
 00 
 66 
 cb 
+cb 
+48 
+cb 
+66 
+ca 
+05 
+00 
+ca 
+05 
+00 
+48 
 ca 
 05 
 00 
@@ -270,6 +282,10 @@ ff
 00 
 00 
 00 
+00 
+00 
+00 
+00 
 17 
 00 
 00 
@@ -294,7 +310,7 @@ ff
 00 
 00 
 00 
-5c 
+68 
 00 
 00 
 00 
@@ -358,7 +374,7 @@ ff
 00 
 00 
 00 
-80 
+8c 
 00 
 00 
 00 
@@ -422,7 +438,7 @@ ff
 00 
 00 
 00 
-84 
+90 
 00 
 00 
 00 
@@ -494,7 +510,7 @@ ff
 00 
 00 
 00 
-1b 
+27 
 00 
 00 
 00 

diff --git a/modules/arch/x86/tests/ret.asm b/modules/arch/x86/tests/ret.asm
index ed37bff8f4fd4109ce2590399d8d5ecda87d7a6e..27317d4014ea253d27d8ac85ac8c2d8f3b79b6bd 100644 (file)
--- a/modules/arch/x86/tests/ret.asm
+++ b/modules/arch/x86/tests/ret.asm
@@ -1,7 +1,29 @@
+[bits 16]
 ret
 ret 4
 ret word 2
 retn 6
 retn word 2
+retf
+retf 8
+retf word 2
+
+[bits 32]
+ret
+ret 4
+ret word 2
+retn 6
+retn word 2
+retf
+retf 8
+retf word 2
+
+[bits 64]
+ret
+ret 4
+ret word 2
+retn 6
+retn word 2
+retf
 retf 8
 retf word 2

diff --git a/modules/arch/x86/tests/ret.hex b/modules/arch/x86/tests/ret.hex
index 1b5e664335fb45cd52ac92b2c4c5e976f0aa671d..431c1924628cb84a6ef113991547f997d4dfdf4c 100644 (file)
--- a/modules/arch/x86/tests/ret.hex
+++ b/modules/arch/x86/tests/ret.hex
@@ -11,9 +11,53 @@ c2
 c2 
 02 
 00 
+cb 
 ca 
 08 
 00 
 ca 
 02 
 00 
+c3 
+c2 
+04 
+00 
+c2 
+02 
+00 
+c2 
+06 
+00 
+c2 
+02 
+00 
+cb 
+ca 
+08 
+00 
+ca 
+02 
+00 
+c3 
+c2 
+04 
+00 
+c2 
+02 
+00 
+c2 
+06 
+00 
+c2 
+02 
+00 
+48 
+cb 
+48 
+ca 
+08 
+00 
+48 
+ca 
+02 
+00 

diff --git a/modules/arch/x86/x86id.re b/modules/arch/x86/x86id.re
index 2712436f555b087fefaa86ba326d2f73ed3fe13f..6f79eb2a804039694e4fb06d9c76ba4a1865196f 100644 (file)
--- a/modules/arch/x86/x86id.re
+++ b/modules/arch/x86/x86id.re
@@ -1250,19 +1250,19 @@ static const x86_insn_info jmp_insn[] = {
       {OPT_Mem|OPS_Any|OPTM_Far|OPA_EA, 0, 0} }
 };
 static const x86_insn_info retnf_insn[] = {
-    { CPU_Any, MOD_Op0Add, 0, 0, 0, 1,
+    { CPU_Not64, MOD_Op0Add, 0, 0, 0, 1,
       {0x01, 0, 0}, 0, 0, {0, 0, 0} },
-    { CPU_Any, MOD_Op0Add, 0, 0, 0, 1,
+    { CPU_Not64, MOD_Op0Add, 0, 0, 0, 1,
       {0x00, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0, 0} },
-    /* GAS suffix versions */
-    { CPU_Any, MOD_Op0Add|MOD_GasSufW, 16, 0, 0, 1,
+    { CPU_64, MOD_Op0Add|MOD_OpSizeR, 0, 0, 0, 1,
       {0x01, 0, 0}, 0, 0, {0, 0, 0} },
-    { CPU_Any, MOD_Op0Add|MOD_GasSufW, 16, 0, 0, 1,
+    { CPU_64, MOD_Op0Add|MOD_OpSizeR, 0, 0, 0, 1,
       {0x00, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0, 0} },
-    { CPU_Any, MOD_Op0Add|MOD_GasSufL|MOD_GasSufQ, 0, 0, 0, 1,
-      {0x01, 0, 0}, 0, 0, {0, 0, 0} },
-    { CPU_Any, MOD_Op0Add|MOD_GasSufL|MOD_GasSufQ, 0, 0, 0, 1,
-      {0x00, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0, 0} }
+    /* GAS suffix versions */
+    { CPU_Any, MOD_Op0Add|MOD_OpSizeR|MOD_GasSufW|MOD_GasSufL|MOD_GasSufQ, 0,
+      0, 0, 1, {0x01, 0, 0}, 0, 0, {0, 0, 0} },
+    { CPU_Any, MOD_Op0Add|MOD_OpSizeR|MOD_GasSufW|MOD_GasSufL|MOD_GasSufQ, 0,
+      0, 0, 1, {0x00, 0, 0}, 0, 1, {OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0, 0} }
 };
 static const x86_insn_info enter_insn[] = {
     { CPU_186|CPU_Not64, MOD_GasNoRev|MOD_GasSufL, 0, 0, 0, 1, {0xC8, 0, 0}, 0,
@@ -3942,25 +3942,23 @@ yasm_x86__parse_check_insn(yasm_arch *arch, unsigned long data[4],
        /* Control transfer instructions (unconditional) */
        'call' { RET_INSN(4, call, 0, CPU_Any); }
        'jmp' { RET_INSN(3, jmp, 0, CPU_Any); }
-       'ret' W? { RET_INSN(3, retnf, 0xC2, CPU_Any); }
+       'ret' { RET_INSN(3, retnf, 0x00C2, CPU_Any); }
+       'retw' { RET_INSN_GAS(3, retnf, 0x10C2, CPU_Any); }
        'retl' {
            not64 = 1;
-           RET_INSN_GAS(3, retnf, 0xC2, CPU_Any);
+           RET_INSN_GAS(3, retnf, 0x00C2, CPU_Any);
        }
        'retq' {
            warn64 = 1;
-           RET_INSN_GAS(3, retnf, 0xC2, CPU_Hammer|CPU_64);
-       }
-       'retn' { RET_INSN_NONGAS(4, retnf, 0xC2, CPU_Any); }
-       'retf' { RET_INSN_NONGAS(4, retnf, 0xCA, CPU_Any); }
-       'lretw' { RET_INSN_GAS(4, retnf, 0xCA, CPU_Any); }
-       'lretl' {
-           not64 = 1;
-           RET_INSN_GAS(4, retnf, 0xCA, CPU_Any);
+           RET_INSN_GAS(3, retnf, 0x00C2, CPU_Hammer|CPU_64);
        }
+       'retn' { RET_INSN_NONGAS(4, retnf, 0x00C2, CPU_Any); }
+       'retf' { RET_INSN_NONGAS(4, retnf, 0x40CA, CPU_Any); }
+       'lretw' { RET_INSN_GAS(4, retnf, 0x10CA, CPU_Any); }
+       'lretl' { RET_INSN_GAS(4, retnf, 0x00CA, CPU_Any); }
        'lretq' {
            warn64 = 1;
-           RET_INSN_GAS(4, retnf, 0xCA, CPU_Any);
+           RET_INSN_GAS(4, retnf, 0x40CA, CPU_Any);
        }
        'enter' [wWlLqQ]? { RET_INSN(5, enter, 0, CPU_186); }
        'leave' { RET_INSN_NS(onebyte, 0x4000C9, CPU_186); }