AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364262 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index b5ff27ed0b4b71f4d0d4c1bf9bf69af257657bbf..d5fe3a02a5fb2b7ef367d953b938b341d2a672e3 100644 (file)
--- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1503,12 +1503,16 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       break;
     }
     case Intrinsic::amdgcn_class: {
-      unsigned SrcReg = MI.getOperand(2).getReg();
-      unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
+      unsigned Src0Reg = MI.getOperand(2).getReg();
+      unsigned Src1Reg = MI.getOperand(3).getReg();
+      unsigned Src0Size = MRI.getType(Src0Reg).getSizeInBits();
+      unsigned Src1Size = MRI.getType(Src1Reg).getSizeInBits();
       unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
       OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize);
-      OpdsMapping[2] = AMDGPU::getValueMapping(getRegBankID(SrcReg, MRI, *TRI),
-                                               SrcSize);
+      OpdsMapping[2] = AMDGPU::getValueMapping(getRegBankID(Src0Reg, MRI, *TRI),
+                                               Src0Size);
+      OpdsMapping[3] = AMDGPU::getValueMapping(getRegBankID(Src1Reg, MRI, *TRI),
+                                               Src1Size);
       break;
     }
     }

diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
index d28f06175ad61c64b3e03ae4adec95f6165229c8..6b832e4c46e79d676aa0cd2cf164dde9db4556c0 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
@@ -3,29 +3,66 @@
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 
 ---
-name: class_s
+name: class_ss
 legalized: true
 
 body: |
   bb.0:
-    liveins: $sgpr0
-    ; CHECK-LABEL: name: class_s
-    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s32), 1
-    %0:_(s32) = COPY $sgpr0
-    %1:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, 1
+    liveins: $sgpr0_sgpr1, $sgpr2
+    ; CHECK-LABEL: name: class_ss
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s32) = COPY $sgpr2
+    %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
 ...
 
 ---
-name: class_v
+name: class_sv
 legalized: true
 
 body: |
   bb.0:
-    liveins: $vgpr0
-    ; CHECK-LABEL: name: class_v
-    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s32), 1
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, 1
+    liveins: $sgpr0_sgpr1, $vgpr0
+
+    ; CHECK-LABEL: name: class_sv
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s32) = COPY $vgpr0
+    %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
+...
+
+---
+name: class_vs
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $sgpr0
+    ; CHECK-LABEL: name: class_vs
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = COPY $sgpr0
+    %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
+...
+
+---
+name: class_vv
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; CHECK-LABEL: name: class_vv
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+    ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s64), [[COPY1]](s32)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = COPY $vgpr2
+    %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
 ...