*/
void esp_default_wake_deep_sleep(void);
+/**
+ * @brief Disable logging from the ROM code after deep sleep.
+ *
+ * Using LSB of RTC_STORE4.
+ */
+void esp_deep_sleep_disable_rom_logging(void);
#ifdef __cplusplus
}
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
- * RTC_CNTL_STORE4_REG External XTAL frequency
+ * RTC_CNTL_STORE4_REG External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
* RTC_CNTL_STORE5_REG APB bus frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
+#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
typedef enum {
AWAKE = 0, //<CPU ON
}
return pd_flags;
}
+
+void esp_deep_sleep_disable_rom_logging(void)
+{
+ /* To disable logging in the ROM, only the least significant bit of the register is used,
+ * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+ * you need to write to this register in the same format.
+ * Namely, the upper 16 bits and lower should be the same.
+ */
+ REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+}
if (!clk_val_is_valid(xtal_freq_reg)) {
return RTC_XTAL_FREQ_AUTO;
}
- return reg_val_to_clk_val(xtal_freq_reg);
+ return reg_val_to_clk_val(xtal_freq_reg & ~RTC_DISABLE_ROM_LOG);
}
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
{
+ uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+ if (reg == RTC_DISABLE_ROM_LOG) {
+ xtal_freq |= 1;
+ }
WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
}