[AArch64][SVE] Asm: Support for insert element (INSR) instructions.

Insert general purpose register into shifted vector, e.g.
  insr    z0.s, w0
  insr    z0.d, x0

Insert SIMD&FP scalar register into shifted vector, e.g.
  insr    z0.b, b0
  insr    z0.h, h0
  insr    z0.s, s0
  insr    z0.d, d0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336979 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td
index dc28f14a59d077e86e1d1666e8dba890a2ca85d9..3a59fac70ab4c41391da3672aa1af16fdf160f04 100644 (file)
--- a/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -113,6 +113,8 @@ let Predicates = [HasSVE] in {
   defm SEL_ZPZZ    : sve_int_sel_vvv<"sel">;
 
   defm COMPACT_ZPZ : sve_int_perm_compact<"compact">;
+  defm INSR_ZR : sve_int_perm_insrs<"insr">;
+  defm INSR_ZV : sve_int_perm_insrv<"insr">;
 
   def AND_PPzPP   : sve_int_pred_log<0b0000, "and">;
   def BIC_PPzPP   : sve_int_pred_log<0b0001, "bic">;

diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td
index de9cb79d24641257bc84ebe4ef1a17c8e395d1e0..5420c2b8c6c302a8c4df0e1665c91ac182efeab2 100644 (file)
--- a/lib/Target/AArch64/SVEInstrFormats.td
+++ b/lib/Target/AArch64/SVEInstrFormats.td
@@ -658,6 +658,55 @@ multiclass sve_int_perm_tbl<string asm> {
                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
 }
 
+class sve_int_perm_insrs<bits<2> sz8_64, string asm, ZPRRegOp zprty,
+                         RegisterClass srcRegType>
+: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
+  asm, "\t$Zdn, $Rm",
+  "",
+  []>, Sched<[]> {
+  bits<5> Rm;
+  bits<5> Zdn;
+  let Inst{31-24} = 0b00000101;
+  let Inst{23-22} = sz8_64;
+  let Inst{21-10} = 0b100100001110;
+  let Inst{9-5}   = Rm;
+  let Inst{4-0}   = Zdn;
+
+  let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_int_perm_insrs<string asm> {
+  def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>;
+  def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>;
+  def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>;
+  def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
+}
+
+class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty,
+                         RegisterClass srcRegType>
+: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm),
+  asm, "\t$Zdn, $Vm",
+  "",
+  []>, Sched<[]> {
+  bits<5> Vm;
+  bits<5> Zdn;
+  let Inst{31-24} = 0b00000101;
+  let Inst{23-22} = sz8_64;
+  let Inst{21-10} = 0b110100001110;
+  let Inst{9-5}   = Vm;
+  let Inst{4-0}   = Zdn;
+
+  let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_int_perm_insrv<string asm> {
+  def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>;
+  def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>;
+  def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>;
+  def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
+}
+
+
 //===----------------------------------------------------------------------===//
 // SVE Vector Select Group
 //===----------------------------------------------------------------------===//

diff --git a/test/MC/AArch64/SVE/insr-diagnostics.s b/test/MC/AArch64/SVE/insr-diagnostics.s
new file mode 100644 (file)
index 0000000..e0ec3e6
--- /dev/null
+++ b/test/MC/AArch64/SVE/insr-diagnostics.s
@@ -0,0 +1,45 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid scalar operand size.
+
+insr    z31.b, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.b, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.h, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.h, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.s, x0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.s, x0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.d, w0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.d, w0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.b, h0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.b, h0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.h, s0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.h, s0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.s, d0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.s, d0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+insr    z31.d, b0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: insr    z31.d, b0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/insr.s b/test/MC/AArch64/SVE/insr.s
new file mode 100644 (file)
index 0000000..7e13a1b
--- /dev/null
+++ b/test/MC/AArch64/SVE/insr.s
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+insr    z0.b, w0
+// CHECK-INST: insr    z0.b, w0
+// CHECK-ENCODING: [0x00,0x38,0x24,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 24 05 <unknown>
+
+insr    z0.h, w0
+// CHECK-INST: insr    z0.h, w0
+// CHECK-ENCODING: [0x00,0x38,0x64,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 64 05 <unknown>
+
+insr    z0.s, w0
+// CHECK-INST: insr    z0.s, w0
+// CHECK-ENCODING: [0x00,0x38,0xa4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 a4 05 <unknown>
+
+insr    z0.d, x0
+// CHECK-INST: insr    z0.d, x0
+// CHECK-ENCODING: [0x00,0x38,0xe4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 38 e4 05 <unknown>
+
+insr    z31.b, wzr
+// CHECK-INST: insr    z31.b, wzr
+// CHECK-ENCODING: [0xff,0x3b,0x24,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 24 05 <unknown>
+
+insr    z31.h, wzr
+// CHECK-INST: insr    z31.h, wzr
+// CHECK-ENCODING: [0xff,0x3b,0x64,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 64 05 <unknown>
+
+insr    z31.s, wzr
+// CHECK-INST: insr    z31.s, wzr
+// CHECK-ENCODING: [0xff,0x3b,0xa4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b a4 05 <unknown>
+
+insr    z31.d, xzr
+// CHECK-INST: insr    z31.d, xzr
+// CHECK-ENCODING: [0xff,0x3b,0xe4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b e4 05 <unknown>
+
+insr    z31.b, b31
+// CHECK-INST: insr    z31.b, b31
+// CHECK-ENCODING: [0xff,0x3b,0x34,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 34 05 <unknown>
+
+insr    z31.h, h31
+// CHECK-INST: insr    z31.h, h31
+// CHECK-ENCODING: [0xff,0x3b,0x74,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b 74 05 <unknown>
+
+insr    z31.s, s31
+// CHECK-INST: insr    z31.s, s31
+// CHECK-ENCODING: [0xff,0x3b,0xb4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b b4 05 <unknown>
+
+insr    z31.d, d31
+// CHECK-INST: insr    z31.d, d31
+// CHECK-ENCODING: [0xff,0x3b,0xf4,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 3b f4 05 <unknown>