2011-03-18 Ivan Maidanski <ivmai@mail.ru>

	* src/atomic_ops/sysdeps/gcc/arm.h: Test for all known pre-v6 ARM
	chips instead of all the currently existing v6+ ones.

diff --git a/ChangeLog b/ChangeLog
index 70a183e02cab0ac4bc23e6dc007c86b8ce2a78e4..0c8838af9429f5dcb67435c7665bf29a67c4214f 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2011-03-18  Ivan Maidanski  <ivmai@mail.ru>
+
+       * src/atomic_ops/sysdeps/gcc/arm.h: Test for all the known pre-v6
+       ARM chips instead of all the currently existing v6+ ones.
+
 2011-03-13  Ivan Maidanski  <ivmai@mail.ru>
 
        * src/atomic_ops/sysdeps/emul_cas.h: Fix a typo in a comment;

diff --git a/src/atomic_ops/sysdeps/gcc/arm.h b/src/atomic_ops/sysdeps/gcc/arm.h
index e44f431d465b86a5078ab57366d1660114c14618..094505ad7f694c825219e7395fde0da27f8bf648 100644 (file)
--- a/src/atomic_ops/sysdeps/gcc/arm.h
+++ b/src/atomic_ops/sysdeps/gcc/arm.h
@@ -31,12 +31,13 @@
  * and do not need to access CP15 for ensuring a DMB
 */
 
-/* NEC LE-IT: gcc has no way to easily check the arm architecture
- * but defines only one of __ARM_ARCH_x__ to be true                    */
-#if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
-        || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6ZK__) \
-        || defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
-        || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7R__)
+/* NEC LE-IT: gcc has no way to easily check the arm architecture       */
+/* but it defines only one of __ARM_ARCH_x__ to be true.                */
+#if !defined(__ARM_ARCH_2__) && !defined(__ARM_ARCH_3__) \
+    && !defined(__ARM_ARCH_3M__) && !defined(__ARM_ARCH_4__) \
+    && !defined(__ARM_ARCH_4T__) && !defined(__ARM_ARCH_5__) \
+    && !defined(__ARM_ARCH_5E__) && !defined(__ARM_ARCH_5T__) \
+    && !defined(__ARM_ARCH_5TE__) && !defined(__ARM_ARCH_5TEJ__)
 
 #include "../standard_ao_double_t.h"
 
@@ -44,8 +45,8 @@ AO_INLINE void
 AO_nop_full(void)
 {
 #ifndef AO_UNIPROCESSOR
-        /* issue an data memory barrier (keeps ordering of memory transactions  */
-        /* before and after this operation)                                     */
+        /* Issue a data memory barrier (keeps ordering of memory        */
+        /* transactions before and after this operation).               */
         unsigned int dest=0;
         __asm__ __volatile__("mcr p15,0,%0,c7,c10,5"
                               : "=&r"(dest) : : "memory");