[AArch64] Correct inline assembly test case for S modifier [NFC]

The existing test for the AArch64 inline assembly constraint S uses the
A and L modifiers. These modifiers were implemented in the original
AArch64 backend but were not carried forward to the merged backend. The
A is associated with ADRP and does nothing, the L is associated with
:lo12: . Given that A and L are not supported by GCC and not supported
by the new implementation of constraint S in LLVM (see D46745) I've
altered the test to put :lo12: directly in the string so that A and L
are not needed.

Differential Revision: https://reviews.llvm.org/D46932

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@332606 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/aarch64-inline-asm.c b/test/CodeGen/aarch64-inline-asm.c
index 264df9d5fc032b7862abee1da16cc9dd2b093d20..0889a7157f0b172891c2d4c68fcf0974e00d6f82 100644 (file)
--- a/test/CodeGen/aarch64-inline-asm.c
+++ b/test/CodeGen/aarch64-inline-asm.c
@@ -44,9 +44,9 @@ void test_constraints_immed(void) {
 
 void test_constraint_S(void) {
     int *addr;
-    asm("adrp %0, %A1\n\t"
-        "add %0, %0, %L1" : "=r"(addr) : "S"(&var));
-// CHECK: call i32* asm "adrp $0, ${1:A}\0A\09add $0, $0, ${1:L}", "=r,S"(i64* @var)
+    asm("adrp %0, %1\n\t"
+        "add %0, %0, :lo12:%1" : "=r"(addr) : "S"(&var));
+// CHECK: call i32* asm "adrp $0, $1\0A\09add $0, $0, :lo12:$1", "=r,S"(i64* @var)
 }
 
 void test_constraint_Q(void) {